Storage
system that features the following: a storage device (200, 300, 5000, 8200) comprising a non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221) having a matrix arrangement structure of at least NxM, where N and M are integers equal to or greater than 2; and a test device (100) which is configured to test the storage device (200, 300, 5000, 8200), wherein an error address, which is detected by the test device (100), is transferred to the storage device (200, 300, 5000, 8200) and stored in the non-volatile storage device (340, 1000, 3601-3604, 5100, 7301, 8221), the test device includes a
semiconductor chip, wherein the
semiconductor chip has an error
correction code, ECC,
machine or a built-in self-test, BIST, unit and an error address memory (110, 260) configured to the error address, wherein the error address memory (110, 260) is controlled by a
control unit (130, 270, 360, 4100, 8110), wherein the
control unit (130, 270, 360, 4100, 8110) is configured to check or control the fault address to be stored in the fault address memory (110, 260) and transmitted according to a test command.