51635results about "Semiconductor/solid-state device details" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

In the present disclosure, a first semiconductor element of a bonded structure comprises a semiconductor-containing oxynitride bonding layer formed on a first substrate layer comprising a semiconductor material, e.g., a single crystal silicon. The semiconductor-containing oxynitride bonding layer is formed by exposing an upper surface of the first substrate layer to products of plasma containing nitrogen and oxygen at controlled plasma conditions. The second semiconductor element of the bonded structure may have a second substrate layer comprising a semiconductor material, e.g., a single crystal silicon, and a semiconductor-containing oxynitride bonding layer formed over the second substrate layer in the same way as the first semiconductor element. In some embodiments, the second semiconductor element may have a bonding layer comprising a dielectric material. After initial direct bonding of the first and second semiconductor elements, the bonded structure may go through an annealing process to strengthen the bonding.

Disclosed are methods of microelectronic processing to reveal conductive vias that are at least partially embedded in a bulk semiconductor, and resulting structures. A method of forming a microelectronic structure includes revealing the plurality of conductive vias from a back surface of the bulk semiconductor and forming a protective cap on each of the conductive vias on the back surface of the bulk semiconductor. The protective caps can be patterned or disposed selectively onto the conductive vias. The protective caps can cover the conductive vias or also cover a portion of the bulk semiconductor surrounding the conductive vias. The back surface of the bulk semiconductor is etched to form protruding conductive vias, which can be surrounded by sleeves of the bulk semiconductor. A dielectric layer is deposited over the back surface and planarized to reveal the plurality of conductive vias from the back surface.

A multi-chip package includes a ball-grid-array (BGA) substrate; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the ball-grid-array (BGA) substrate; a plurality of first metal bumps between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package over the ball-grid-array (BGA) substrate, wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate, a non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the circuit substrate and a plurality of second metal bumps under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps under and on the ball-grid-array (BGA) substrate.

To provide a semiconductor package containing an insulating material.SOLUTION: A semiconductor package 1000 contains: a re-wiring structure body 300 that contains a re-wiring layer containing copper (Cu) and an insulation layer 310 surrounding the re-wiring layer; a semiconductor chip 100 that is mounted onto the re-wiring structure body, and contains a plurality of chip-coupling members 130; an internal coupling terminal 134 that is arranged between the re-wiring structure body and the semiconductor chip, and electrically connects the re-wiring layer and a connection pad; an external coupling terminal 600 that is adhered to a lower side of the re-wiring structure body, and is electrically connected to the re-wiring layer; and a sealing member 250 that surrounds the semiconductor chip and the internal coupling terminal on the re-wiring structure body. The insulation layer is made of an insulating material, where K satisfies 20 or more in a TC index.SELECTED DRAWING: Figure 1

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention relates to the technical field of chip heat dissipation, and discloses a photoelectric co-packaging heterogeneous chip heat dissipation integration method, device and equipment, and the method comprises the steps: carrying out the finite element modeling analysis of a photoelectric co-packaging heterogeneous chip, and obtaining a three-dimensional thermal characteristic model; performing signal acquisition and frequency domain characteristic analysis on each functional module of the photoelectric co-packaged heterogeneous chip to generate power consumption prediction data; performing temperature field distribution calculation on the photoelectric co-packaging heterogeneous chip according to the power consumption prediction data and the three-dimensional thermal characteristic model, and constructing a temperature outer ring control model and a heat flow inner ring control model; and performing heat dissipation structure layout optimization calculation based on the temperature outer ring control model and the heat flow inner ring control model, and generating a hybrid heat dissipation layout scheme. Dynamic distribution of heat dissipation power and automatic threshold adjustment are realized, frequent mode switching is avoided, and the thermal characteristic stability of a chip is improved.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

The invention provides a 2.5 D substrate manufacturing method and a packaging structure. The 2.5 D substrate manufacturing method comprises the following steps: providing a first carrier on which a metal part and an intermediate layer are mounted; a metal column is arranged in the intermediate layer; forming a protective layer covering the metal component and the interposer on the first carrier; a first recess is formed on the metal feature. The interposer and the protective layer are ground such that the interposer and protective layer surfaces are lower than the surface of the metal feature. Forming a first dielectric layer with a first opening on the surfaces of the intermediate layer and the protective layer; the first opening exposes the metal column. Forming a seed layer in the first opening; the seed layer extends to the surface of the metal part and fills the first groove. A wiring layer is formed on the seed layer. The bonding force of the seed layer and the first dielectric layer can be improved, the corrosion to the side wall of the interposer in the etching process is prevented, and the packaging quality and precision are improved.

A package structure is provided. The packaging structure comprises a substrate; a package component bonded to the substrate; a cap disposed over the package assembly and the substrate; and an interface structure sandwiched between the package components. The package assembly includes: a first die; a second die laterally spaced apart from the first die by an underfill; and a molding compound adjacent the first die and the second die. The interface structure includes an adhesive layer disposed over the underfill and the molding compound; and a thermal interface material (TIM) layer over the adhesive layer, the first die, and the second die. The embodiment of the invention also relates to a packaging structure and a forming method thereof.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

Ultrasound devices and systems are disclosed in which cooling of an active acoustic element of an ultrasound transducer is achieved via an electrically conductive member that extends beyond a proximal side of the active acoustic element to contact a heat exchanger. The electrically conductive member delivers electrical driving signals to the active acoustic element while conducting heat to the heat exchanger. A region of the proximal surface of the active acoustic element that is free from contact with the electrically conductive member may also absent from contact with a liquid or a solid, thereby facilitating reflection of ultrasound energy. The heat exchanger may include an electrically insulating fluid that contacts the electrically conductive member to remove the heat conducted through the electrically conductive member. The active acoustic element may be a multilayer lateral mode element, and the electrically conductive member may form an electrode of the lateral mode element.

Embodiments of an integrated circuit (IC) package including a package substrate, a first microelectronic assembly including a plurality of first IC die, each first IC die having memory circuitry and a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces; and a second IC die having a first surface and an opposite second surface, wherein the third surfaces of the first IC die are coupled to the second surface of the second IC die, and the first surface of the second IC die is coupled to the package substrate; a third IC die having a first surface and an opposing second surface, wherein the first surface third IC die is coupled to the package substrate; and a plurality of fourth IC die, each fourth IC die including compute circuitry and electrically coupled to the second surface of the third IC die.

An electronic device comprises a heat source and a heat distribution structure coupled to the heat source to distribute heat generated by the heat source during operation of the electronic device.

The invention relates to the technical field of packaging of power electronic devices, in particular to a three-dimensional packaged double-sided heat dissipation power module. The structure comprises an upper active metal brazing base material substrate and a lower active metal brazing base material substrate, a plurality of silicon carbide MOSFET chips, conductive strips and an inserter used for fixing the chips are arranged between the upper active metal brazing base material substrate and the lower active metal brazing base material substrate, the upper half-bridge chip is annularly arranged around a direct-current positive terminal, the lower half-bridge chip is annularly arranged around a direct-current negative terminal, and heat dissipation channels are formed in the upper surface and the lower surface of each chip. The impedance of branches is controlled to be equal, the current of each branch chip is balanced, the distance and layout of the chips are optimized, the overall loop area is reduced, the parasitic stray inductance of the module is reduced, in addition, the chips and the substrate are connected in a crimping mode, the chips and the copper columns are in contact through pressure to achieve electric heat conduction, the crimping materials are graphene sheets and molybdenum sheets, and the cost is low. Good contact between the chip and the copper columns is ensured, and contact resistance and thermal resistance are reduced. According to the invention, the effects of improving the heat dissipation efficiency, reducing parasitic stray inductance, balancing the current distribution of the parallel chips, and enhancing the module reliability and the conversion efficiency are achieved.

The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

The invention relates to the field of pressure sensors, in particular to a pressure sensor and a processing method, and a chip comprises a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode and packaging glass. The device layer comprises a silicon carbide single crystal device layer and a silicon device layer; the silicon carbide single crystal device layer is arranged on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing region and a micro-channel; the sensitive resistance device layer is isolated from the annular sealing area through the micro-channel; the device layer, the silicon dioxide dielectric layer and the silicon substrate are etched to form a cross beam etching area; the silicon substrate is etched to form a silicon pressure cavity and a beam film; the metal electrode is arranged on the top of the device layer; and the packaging glass anode is bonded at the top of the device layer or the bottom of the silicon substrate so as to solve the problems of low high temperature resistance and low sensitivity of the MEMS pressure sensor.

A method for surface defect inspection can comprise obtaining topographical data from one or more portions of a semiconductor element. The semiconductor element can have a surface comprising a dielectric and a plurality of metal pads. The method can further comprise processing the topographical data of the one or more portions of the semiconductor element to determine at least a first property of the plurality of metal pads, computing at least one variability value for the first property, and identifying candidate defects in the one or more portions of the semiconductor element based at least in part on the at least one variability value.

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on / in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: carrying out the etching of a substrate through employing an etching technology, so as to form a high-aspect-ratio etching structure on the substrate; after a periodic cycle step of a preset number of times of etching process is completed every time, a treatment process different from the etching process is used, and partial thickness of a passivation layer deposited on the side wall of an intermediate structure formed before the high aspect ratio etching structure is formed is removed. And removing at least part of the protruding part which exists on the side wall and is exposed from the surface of the residual passivation layer. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

The invention discloses an MEMS device architecture, which comprises a cap layer, a device layer and a substrate layer, the cap layer is bonded with the device layer, the bonded whole is bonded with the substrate layer, the cap layer is manufactured based on a first silicon substrate, the bottom of the cap layer is provided with a cavity structure, and the cap layer is internally provided with a high-deep groove structure. A silicon dioxide film is arranged on the groove wall of the high-deep groove structure, polycrystalline silicon is deposited and filled in the high-deep groove structure, and a silicon dioxide layer is arranged on the upper surface of the first silicon substrate; the device layer is manufactured based on an SOI wafer and comprises a first silicon structure layer composed of top layer silicon, a buried oxide layer and a second silicon structure layer composed of back substrate silicon. The substrate layer comprises a second silicon substrate, a bottom layer cavity is formed in the top face of the second silicon substrate, and exhaust holes are formed in the bottom face of the second silicon substrate. According to the method, deep groove etching, polycrystalline silicon groove filling and bonding technologies are combined, advanced materials such as the SOI wafer and the polyimide layer are utilized, and excellent signal isolation and flexibility of various MEMS IMU applications are achieved.

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.

Structures having registration marks for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer comprising a plurality of nanowire-based or fin-based transistors and a pad laterally adjacent to the plurality of nanowire-based or fin-based transistors, the pad having first grating structures aligned along an X-direction and second grating structures aligned along a Y-direction therein, the first and second grating structures exposed at a backside surface of the front side structure. The front-side also includes a plurality of metallization layers above the plurality of nanowire-based or fin-based transistors. The integrated circuit structure also includes a backside structure below the plurality of nanowire-based or fin-based transistors of the device layer of the front side structure, the backside structure comprising backside metal layers and vias.

The invention provides a 2.5 D substrate packaging method and packaging structure, and relates to the technical field of semiconductor packaging. The 2.5 D substrate packaging method comprises the following steps: providing a carrier; wherein the carrier is provided with a flat part and a boss part; the boss part protrudes out of the flat part. Forming a first wiring layer on the boss part; forming a second wiring layer on the flat part; the first wiring layer and the second wiring layer are independent from each other. Mounting a first chip; the first chip comprises a plurality of first electric connection parts, at least one first electric connection part is electrically connected with the first wiring layer, and at least one first electric connection part is electrically connected with the second wiring layer; the length of the first electric connection part connected with the first wiring layer is smaller than that of the first electric connection part connected with the second wiring layer. Removing the carrier; and forming a solder ball on one side, far away from the first chip, of the second wiring layer. The inductance effect and the parasitic effect are reduced, the transmission path is shortened, the transmission efficiency is improved, and the chip integration level and the product performance are improved.

Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD), the substrate and the interconnect region share a planar interface, and the first IC dies and the second IC die are arranged with the planar interfaces of the first IC dies parallel to each other and orthogonal to the planar interface of the second IC die.