4439 results about "Line width" patented technology

Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between the adjacent conductive layers. Since the centers of the droplets are staggered, parts of the conductive layers each having a widest line width (the widest width of knot) are not connected to each other, and the conductive layers can be formed adjacently with a shorter distance therebetween.

The present invention provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a microwave power generator coupled to the to the chamber body through a waveguild, and one or more coils or magnets disposed around an outer circumference of the chamber body adjacent to the waveguide, and a gas source coupled to the waveguide through a gas delivery passageway.

Provided is a method for patterning a substrate, comprising: forming a layer of radiation-sensitive material on a substrate; preparing a pattern in the layer of radiation-sensitive material using a lithographic process, the pattern being characterized by a critical dimension (CD) and a roughness; following the preparing the pattern, performing a CD shrink process to reduce the CD to a reduced CD; and performing a growth process to grow the reduced CD to a target CD. Roughness includes a line edge roughness (LER), a line width roughness (LWR), or both LER and LWR. Performing the CD shrink process comprises: coating the pattern with a hard mask, the coating generating a hard mask coated resist; baking the hard mask coated resist in a temperature range for a time period, the baking generating a baked coated resist; and developing the baked coated resist in deionized water.

A method for processing a substrate including a processing target layer and an organic film, include: a deposition/trimming process of forming a reinforcement film on a surface of the organic film and, at the same time, trimming a line width of a line portion of the organic film constituting an opening pattern. The deposition/trimming process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto the surface of the organic film and an oxidation process in which the line width of the organic film is trimmed while the adsorbed silicon-containing gas is converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.

The present invention provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.

An overlay target for spectroscopic measurement includes at least two diffraction gratings, one grating overlying the other. The diffraction gratings may include an asymmetry relative to each other in order to improve resolution of the presence as well as the direction of any mis-registration. For example, the asymmetry between the two diffraction gratings may be a phase offset, a difference in pitch, line width, etc. The overlay target may be spectroscopically measuring, for example, using an optical model and a best fit analysis. Moreover, the overlay target may be optimized by modeling the overlay target and adjusting the variable parameters and calculating the sensitivity of the overlay target to changes in variable parameters.

A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

The invention provides a method for forming a film pattern, in which a method for forming a film pattern by the ink-jet method is improved, an increase in film thickness is achieved efficiently with simple steps, a requirement for a decrease in line width is met and, in addition, problems such as breaks and short circuits are not brought about when a conductive film is made. The method can include a first discharging step, wherein droplets are discharged in the whole film formation region with a pitch larger than the diameter of the droplet after being hit onto the substrate. In the second discharging step, droplets are discharged at positions in the whole film formation region different from the discharge positions in the first discharging step with the same pitch as that in the first discharging step. In the third discharging step, droplets are discharged in the whole film formation region with a pitch smaller than the pitch in the first discharging step. The substrate is treated beforehand in order to have the contact angle of 60 degrees or more with respect to the droplets.

A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the second spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.

A scanning exposure apparatus which promptly analyzes a cause for a variation in exposure line width. The scanning exposure apparatus includes a mask stage on which a mask is placed, a wafer stage on which a wafer is placed, a focusing mechanism which detects surface position information of the wafer and adjustment means which adjusts the surface position of the wafer. Control means acquires pose information of the wafer adjusted by the adjustment means at the time of exposure and stores the pose information in a memory in association with preacquired surface shape information of an exposure area. A state in which the exposed surface of the wafer has been exposed with respect to exposure light is known from the pose information and the surface shape information.

The present invention belongs to the field of fine surface structure measuring technology, and relates to one kind of differential confocal scanning detection method with high spatial resolution. Differential confocal microscopic double receiving light path configuration and double detector subtraction form the differential confocal signal in measuring the workpiece. Optical super-resolution confocal microscopic detection method is adopted to raise the transverse resolution, and differential confocal microscopic detection method is adopted to raise the longitudinal resolution, so as to reach differential confocal scanning detection of high spatial resolution. The method can meet the requirements in high spatial resolution, high precision and great measurement range, and is especially suitable for the measurement of fine surface 3D structure, miniature steps, miniature grooves, line width, surface appearance, etc.

A parallel resonant circuit is realized by stacking first to fourth wiring patterns each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node and the other thereof is set to a signal output node. Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

The present invention relates to a novel thermal-sensitive resistive apparatus, such as PTC and NTC, which allocates planar electrode films on the top and bottom surfaces of a prior art thermal-sensitive resistive apparatus, such as a PTC apparatus, to laminate with an outer electrode layer. A plurality of interconnection vias are electroplated with conductive material to connect to any plane. It is convenient to surface mount the apparatus of the present invention on a printed circuit board. The present invention can largely increase the dimensional stability of components and overcome the disadvantage that thermal diffusion of the prior are surface mounted resistive apparatus is affected easily by line width and environments.

An external cavity mirror for use in a semiconductor laser, the external cavity mirror comprising a waveguide formed on a substrate of highly electro-optic material, and including electrically-operated means for determining the reflectance attributes of the external cavity mirror.

Defects in an image forming system may give rise to visible streaks, or one-dimensional defects in an image that run parallel to the process direction. One known method for compensating for streaks introduces a separate tone reproduction curve for each pixel column in the process direction. A compensation pattern according to this invention has a plurality of halftone regions that are lead by, trained by, and separated by rows of fiducial marks. The fiducial marks allow the printer pixel grid and a scanning pixel grid to be correlated. The gray level in each pixel column of each gray level portion is measured and analyzed to produce a local tone reproduction curve for each pixel column and associated line width. The local tone reproduction curves are then used to compensate for the streak defect when printing.