4491 results about "Line width" patented technology

A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a simulation target that is used as the new target within the MBOPC process. The pattern dependent portion of the model is used as the process model in the MBOPC algorithm. This results final mask designs that result in improved across-chip line width variations, and a more robust MBOPC process.

An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.

A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.

A pattern forming method includes preparing a target object including silicon with an initial pattern formed thereon and having a first line width; performing a plasma oxidation process on the silicon surface inside a process chamber of a plasma processing apparatus and thereby forming a silicon oxide film on a surface of the initial pattern; and removing the silicon oxide film. The pattern forming method is arranged to repeatedly perform formation of the silicon oxide film and removal of the silicon oxide film so as to form an objective pattern having a second line width finer than the first line width on the target object.

A phase-shifting mask suited for equal line / space, small pitched, dense line pattern is disclosed. The phase-shifting mask includes a transparent substrate, a partially shielded mesa line pattern of first phase formed on the substrate, and a 100% clear recessed line pattern of second phase etched into the substrate and is disposed right next to the partially shielded mesa line pattern. The partially shielded mesa line pattern has a plurality of alternating 45-degree, oblique areas and 100% transmittance clear regions of the first phase. The partially shielded mesa line pattern and the clear recessed line pattern have the same line width. The light that passes through the clear regions of the first phase and the light that passes through the clear recessed line pattern of second phase have a phase difference of 180 degree.

A security document comprising artwork including a security pattern, characterized in that the security pattern has the form of a line structure in which lines width or line spacing is adjusted to carry predefined data. The artwork is generated by the modifying at least one color of at least a part of the artwork to embed the security pattern in the artwork. Methods for detecting the security pattern include use of a frequency domain structure to detect the security pattern despite rotation and scaling of the document, use of signal tiling to improve signal detection, and use of statistical analyses to verify detection of the security pattern.

An apparatus, method and system that uses a Q-switched laser or a Q-seed source for a seed pulse signal having a controlled high-dynamic-range amplitude that avoids and / or compensates for pulse steepening in high-gain optical-fiber and / or optical-rod amplification of optical pulses. Optionally, the optical output is used for LIDAR or illumination purposes (e.g., for image acquisition). In some embodiments, well-controlled pulse shapes are obtained having a wide dynamic range, long duration, and not-too-narrow linewidth. In some embodiments, upon the opening of a Q-switch in an optical cavity having a gain medium, the amplification builds relatively slowly, wherein each round trip through the gain medium increases the amplitude of the optical pulse. Other embodiments use quasi-Q-switch devices or a plurality of amplitude modulators to obtain Q-seed pulses. These configurations provide optical pulses having wide dynamic ranges that ameliorate problems of pulse steepening, non-linear spectral broadening and the like in very-high-power MOPA devices.