41643 results about "Semiconductor device" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

Disclosed in the present invention are a grid-connect control method and apparatus for a grid-connect inverter. The method comprises: on the basis of a control structure of a grid-connect inverter in a dp domain, passing a deviation signal of a power outer loop through power outer loop controllers, so as to generate reference values of a current inner loop, and comparing the reference values of the current inner loop with an actual output current, so as to obtain error signals, wherein the control structure comprises a PQ power control outer loop and a current control inner loop, and the actual output current is obtained by means of performing phase tracking, on the basis of a synchronous reference frame phase-locked loop, on the voltage of a point of common coupling; and adjusting the error signals by means of a current inner loop controller, so as to generate modulation signals, performing pulse width modulation (PWM) on the modulation signals, so as to generate an on-off signal of an inverter bridge power semiconductor device, and controlling the state of connection and disconnection between the grid-connect inverter and a power grid on the basis of the on-off signal. In the present embodiment, the connection and disconnection between a grid-connect inverter and a power grid are controlled, so as to improve the stability of the grid-connect inverter in weak power grids.

The invention relates to the technical field of intelligent control of test equipment, and discloses a semiconductor device test equipment control system and method based on industrial data processing, and the method comprises the steps: collecting multi-source heterogeneous data of semiconductor device test equipment, and carrying out the preprocessing; constructing a structural causal model, and performing root cause identification through anti-fact reasoning by using the structural causal model; constructing an abnormal test fingerprint and a knowledge base; generating an intervention scheme, evaluating the generated intervention scheme, and selecting an optimal intervention scheme; processing the detected anomaly, and generating and implementing a preventive control strategy based on historical anomaly data and a causal analysis result; according to the invention, by introducing innovative technologies such as causal inference, anti-factual inference, abnormal test fingerprint identification and Monte Carlo tree search, intelligent control of semiconductor test equipment is realized.

The invention discloses a power semiconductor device aging on-line diagnosis method, which relates to the field of power electronics, and comprises the following steps: integrating an intelligent sensor and an aging test circuit, and establishing a multi-physics field coupling simulation model; based on the multi-physics field coupling simulation model, evaluating the aging state of the current device to obtain the health index of the device; based on the multi-dimensional data matrix, constructing an anomaly detection model, and outputting an anomaly detection result; predicting the failure probability and the remaining service life of the semiconductor device according to an abnormal detection result; generating a maintenance suggestion based on the predicted failure probability and remaining useful life of the semiconductor device; according to the method, the maintenance suggestion is generated according to the prediction result, the user is guided to take preventive maintenance measures in time, the accuracy of aging state evaluation is improved, the timeliness of fault early warning is enhanced, and economic losses and technical risks caused by sudden faults are reduced.

The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

To provide a semiconductor device with excellent electric characteristics.SOLUTION: A transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 thereon, an oxide 230a thereon, an oxide 230b thereon, an oxide 243a and an oxide 243b thereon, conductors 242a and 242b on the oxides 243a and 243b, insulators 272a and 272b on the conductors 242a and 242b, an oxide 230c on the oxide 230b, an insulator 250 thereon, and a conductor 260 existing thereon and overlapping with the oxide 230c. The oxide 230c is in contact with each of side surfaces of the oxides 243a and 243b and side surfaces of the conductors 242a and 242b. In an insulator 274 and an insulator 280 on the transistor 200, regions 241a and 241b with higher nitrogen concentration than the other regions are formed near an interface with the conductors 240a and 240b.SELECTED DRAWING: Figure 1

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device and particularly to MOSFET transistors. A semiconductor device including a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region, two first well regions including two source regions, two second well regions, a scatter oxide layer, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two first well regions are adjacent to the first-conductivity-type epitaxy layer and each of the two first well regions is adjacent to one second well region, the JFET region is adjacent to the two second well regions, the scatter oxide layer is adjacent to the two source regions, the two first well regions, the two second well region and the JFET region, and a width of the JFET region is greater near the scatter oxide layer than in part closest to the first-conductivity-type substrate.

A semiconductor device comprises a gate cut portion disposed between a first gate region and a second gate region. The gate cut portion comprises a dielectric liner layer disposed around a vacant area. The dielectric liner layer encloses the vacant area, and the gate cut portion isolates the first gate region from the second gate region.

The invention provides a packaging and sintering evaluation method and device for a power semiconductor device, and the method comprises the steps: carrying out the non-destructive scanning through a high-frequency acoustic microtechnique, carrying out the correction through combining with a temperature-sound velocity relation model, achieving the real-time monitoring of a sintering process, and solving a problem that the transient change cannot be captured. Through frequency domain conversion and an improved inverse Fourier transform algorithm, precise reconstruction of the microstructure of the sintering interface is realized, and the limitation that the microstructure is difficult to evaluate in the prior art is overcome. Based on the reconstructed microstructure, a detailed three-dimensional geometric model is established, and time domain finite element analysis is performed, so that comprehensive thermal stress evolution data is obtained, and the defect of surface information of a traditional method is overcome. And quantitative evaluation is carried out by using the multi-dimensional feature space and the preset discrimination model, so that comprehensive analysis of the sintering quality is realized, and the defect of lack of comprehensive quantitative evaluation capability is overcome. Through organic combination of the steps, the accuracy and comprehensiveness of packaging and sintering evaluation are remarkably improved.

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

A method of fabricating a semiconductor device includes forming a memory cell array stack including a vertical stack of pad portions over a first substrate, forming first bonding pads each coupled to a different one of the pad portions in the vertical stack, forming control circuits including a plurality of sub-word line drivers over a second substrate, forming multi-layer level metal wiring coupled to the sub-word line drivers, forming second bonding pads coupled to the multi-layer level metal wiring, and performing a wafer bonding process for electrical coupling between the memory cell array stack and the control circuits.

The invention discloses an online aging state monitoring method and system for a silicon carbide MOSFET, and belongs to the technical field of semiconductor device monitoring, and the method specifically comprises the steps: collecting the working voltage, working current and junction temperature data of the silicon carbide MOSFET in real time, analyzing and processing the data through a data processing unit, and extracting the aging state characteristic parameters of the MOSFET; a dynamic aging state evaluation model fusing multi-source data and time sequence information is adopted to evaluate the aging state of the silicon carbide MOSFET, and a result is output to a display unit; according to the method, the aging state of the silicon carbide MOSFET is monitored, multi-level alarm strategies are set, different levels of alarm signals are triggered according to the aging state, meanwhile, feedback data are collected to optimize the state evaluation model, real-time and accurate monitoring of the aging state of the silicon carbide MOSFET is achieved, and the reliability and stability of a power electronic system are improved.

The invention discloses a self-adaptive switching system and method for power supply and distribution, and the system comprises a data collection module, an analysis module, a modeling module, a decision module, an execution module and an early warning module, and the data collection module generates a real-time monitoring signal; the analysis module performs dynamic weighted evaluation according to the real-time monitoring signal and generates an evaluation signal; the modeling module constructs a virtual model of the power supply system and generates an analog signal; the decision signal generates a control signal containing a path selection instruction; the execution module controls the semiconductor device to switch the physical connection state of the power supply according to the control signal and generates a switch feedback signal; and the early warning module forms an equipment health assessment result according to the switch feedback signal and an abnormal arc signal when the execution module switches the connection state and transmits the result to the decision module. The self-adaptive switching system for power supply and distribution can solve the problem that a traditional power supply and distribution switching system depends on a single threshold to judge the state of a power supply and cannot comprehensively evaluate the quality of electric energy.

A semiconductor device includes semiconductor elements and conductors. The conductors include a first upper conductor connected to an upper electrode of the first semiconductor element through a first upper solder, a first lower conductor connected to a lower electrode of the first semiconductor element through a first lower solder, a second upper conductor connected to an upper electrode of the second semiconductor element through a second upper solder, a second lower conductor connected to a lower electrode of the second semiconductor element through a second lower solder, and a joint conductor connecting the first upper conductor and the second lower conductor through a relay solder. Each solder contains Cu and Sn. Each solder connection target has an Ni layer. A grain size of at least one of the first upper solder, second upper solder, or relay solder is smaller than a grain size of the first and second lower solders.

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source / drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source / drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source / drain feature; and a power rail disposed under and electrically connected to the first via.

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention discloses an intelligent adaptive semiconductor packaging test optimization method, and relates to the technical field of semiconductor packaging test, and the method comprises the steps: S1, constructing a quantization topology sensing network, and collecting test parameters through a quantum tunneling effect dielectric sensing array and a topology photonic crystal waveguide field reconstruction technology; according to the intelligent self-adaptive semiconductor packaging test optimization method, self-consistent optimization of a high-dimensional dynamic test system is realized through a deep coupling architecture of quantum topology dynamic perception and bionic element learning decision and establishment of an intrinsic manifold space of test parameters, and the problem that the test efficiency is high under advanced packaging of semiconductor devices is solved. A traditional test technology has the problem of space-time frequency domain limitation in multi-dimensional parameter coupling detection.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

The invention discloses a gas distribution device and semiconductor equipment, and the gas distribution device comprises a cover body which is provided with a gas inlet part; the spraying piece is movably arranged on the cover body, and a diffusion cavity communicated with the air inlet part is formed between the spraying piece and the cover body; the lifting isolation device comprises a partition plate part and a lifting part, the lifting part is movably arranged on the partition plate part in a sleeving mode, the top of the lifting part is attached to the cover body so that interaction force can be generated between the lifting part and the partition plate part as well as between the lifting part and the cover body, and the partition plate part is arranged on the spraying part so that the diffusion cavity can be defined into different air chambers through the partition plate part and the lifting part; the driving device is arranged at the bottom of the spraying part and extends out of the cover body, and the driving device is controlled to drive the spraying part and the partition plate part to move away from or towards the cover body, so that the top of the lifting part moves towards or away from the cover body, and the volume of the area defined by the lifting isolation device is adjusted. The semiconductor equipment comprises a gas distribution device and a base which is arranged opposite to the gas distribution device and is used for bearing a substrate. According to the invention, the airflow adjustment flexibility can be improved, and the equipment compatibility is improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The invention discloses a self-adaptive digital twin simulation device and method for semiconductor equipment. The device comprises a data acquisition module, a simulation model construction and operation module and a parameter updating module which are connected through signals. The data acquisition module is used for acquiring production information and process parameter information of a semiconductor product and acquiring actual processing data in real time; the simulation model construction and operation module constructs a process equipment energy consumption simulation model according to a preset process equipment configuration unit, fuses production information and process parameter information of a semiconductor product, operates the process equipment energy consumption simulation model, and gives energy consumption simulation data in real time; and the parameter updating module is used for updating the process parameter information in the process equipment energy consumption simulation model. A real-time data feedback mechanism is introduced by setting a parameter updating module, process parameter information is dynamically updated, and the accuracy and the real-time performance of the process equipment energy consumption simulation model are improved.

The invention relates to the technical field of semiconductor testing, and provides a semiconductor testing method and device.The method comprises the steps that electric signal parameters, temperature data and optical image information of a semiconductor device are collected and processed, and a standardized electric signal sequence, a continuous temperature distribution curve and device surface topography features are obtained; analyzing the standardized electric signal sequence and the continuous temperature distribution curve to generate a dynamic working condition mapping matrix; and performing mode matching on the dynamic working condition mapping matrix by using a preset fault mode library, identifying potential defect types and position coordinates, inputting the device surface topography features and the potential defect types and position coordinates into a composite scoring model, generating a comprehensive quality score, and then performing grading to obtain a semiconductor test result. By generating the comprehensive quality score and then grading, the semiconductor test result is obtained, so that the accuracy of defect identification is improved, and the problems that the multi-dimensional correlation analysis is lacked and the dynamic working condition of the device is difficult to comprehensively evaluate in the semiconductor test are solved.

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

The invention relates to the technical field of semiconductor devices, in particular to an infrared photoelectric detector based on a super lens and a manufacturing method of the infrared photoelectric detector. The infrared photoelectric detector based on the super lens comprises a tube socket, a metal tube cap and a detector chip, the metal tube cap and the tube socket are fixedly connected and form a totally-enclosed packaging structure, the detector chip is packaged between the tube socket and the metal tube cap, a chip electrode of the detector chip is welded with a pin of the tube socket, the super lens is arranged at the top of the metal tube cap, and the super lens is arranged on the top of the metal tube cap. The side wall is a metal tube shell, and the super lens comprises a super lens substrate and super lens units periodically arranged above the super lens substrate. According to the infrared photoelectric detector based on the super lens, the super lens units periodically arranged on the super lens can be utilized, the transmittance of incident light can be improved, the interference effect of reflected light can be restrained, and then the detection rate of the infrared photoelectric detector is improved.

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.

A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.

A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.