59921 results about "Semiconductor device" patented technology

A device including a first integrated device die and a semiconductor device. The first integrated device die can include a die insulating layer and a die conductive feature at least partially embedded in the die insulating layer. The semiconductor device can include a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first heavily doped semiconductor material electrically connected to the device conductive feature. The die conductive feature can be connected to power or ground through at least the first heavily doped semiconductor material.

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

Disclosed in the present invention are a grid-connect control method and apparatus for a grid-connect inverter. The method comprises: on the basis of a control structure of a grid-connect inverter in a dp domain, passing a deviation signal of a power outer loop through power outer loop controllers, so as to generate reference values of a current inner loop, and comparing the reference values of the current inner loop with an actual output current, so as to obtain error signals, wherein the control structure comprises a PQ power control outer loop and a current control inner loop, and the actual output current is obtained by means of performing phase tracking, on the basis of a synchronous reference frame phase-locked loop, on the voltage of a point of common coupling; and adjusting the error signals by means of a current inner loop controller, so as to generate modulation signals, performing pulse width modulation (PWM) on the modulation signals, so as to generate an on-off signal of an inverter bridge power semiconductor device, and controlling the state of connection and disconnection between the grid-connect inverter and a power grid on the basis of the on-off signal. In the present embodiment, the connection and disconnection between a grid-connect inverter and a power grid are controlled, so as to improve the stability of the grid-connect inverter in weak power grids.

The invention relates to the technical field of intelligent control of test equipment, and discloses a semiconductor device test equipment control system and method based on industrial data processing, and the method comprises the steps: collecting multi-source heterogeneous data of semiconductor device test equipment, and carrying out the preprocessing; constructing a structural causal model, and performing root cause identification through anti-fact reasoning by using the structural causal model; constructing an abnormal test fingerprint and a knowledge base; generating an intervention scheme, evaluating the generated intervention scheme, and selecting an optimal intervention scheme; processing the detected anomaly, and generating and implementing a preventive control strategy based on historical anomaly data and a causal analysis result; according to the invention, by introducing innovative technologies such as causal inference, anti-factual inference, abnormal test fingerprint identification and Monte Carlo tree search, intelligent control of semiconductor test equipment is realized.

The invention discloses a power semiconductor device aging on-line diagnosis method, which relates to the field of power electronics, and comprises the following steps: integrating an intelligent sensor and an aging test circuit, and establishing a multi-physics field coupling simulation model; based on the multi-physics field coupling simulation model, evaluating the aging state of the current device to obtain the health index of the device; based on the multi-dimensional data matrix, constructing an anomaly detection model, and outputting an anomaly detection result; predicting the failure probability and the remaining service life of the semiconductor device according to an abnormal detection result; generating a maintenance suggestion based on the predicted failure probability and remaining useful life of the semiconductor device; according to the method, the maintenance suggestion is generated according to the prediction result, the user is guided to take preventive maintenance measures in time, the accuracy of aging state evaluation is improved, the timeliness of fault early warning is enhanced, and economic losses and technical risks caused by sudden faults are reduced.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an interposer disposed on a portion of the package substrate. A first integrated circuit (IC) chip is disposed on the interposer. A first memory device is disposed on the interposer and includes a first port interface including an interposer-compliant mechanical interface for coupling to the first IC chip via a first set of traces formed in the interposer. A second port interface includes a non-interposer-compliant mechanical interface for coupling to an off-interposer device. Transactions between the first IC chip and the off-interposer device pass through the first port interface and the second port interface of the first memory device.

The invention relates to a construction method for predicting the film thickness of a double-sided local coating based on a machine learning simulation model, and belongs to the technical field of electroplating. According to the method, the LR logistic regression model is perfected and constructed through the machine learning simulation model, and the LR logistic regression model is trained by utilizing the constructed logistic regression model, so that the optimal electronic electroplating production conditions of semiconductor devices with different structures can be quickly determined, and the optimal plating piece double-sided local electronic electroplating control mode is further obtained; according to the method, the accuracy of predicting the thickness of the double-sided local coating of the semiconductor device can be realized, the error with the thickness of the coating of an actual electroplating product can be greatly reduced, further improvement of an electronic electroplating module can be realized, the uniformity of the thickness of the double-sided local coating of the semiconductor device can be improved, and the requirement of high quality of the semiconductor device can be met.

The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source / drain (S / D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S / D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S / D electrodes which are separated from the gate protection layer by the first passivation layer.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

To provide: a transistor with favorable electrical characteristics; a transistor with a high on-state current; a transistor with low parasitic capacitance; or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated.SOLUTION: There is provided a transistor including an oxide semiconductor layer, a semiconductor device, or a memory device. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region.SELECTED DRAWING: Figure 1

The invention discloses a high-integration-level matrix type magnetic sensing chip structure and circuit and a manufacturing method thereof, and belongs to the technical field of semiconductor devices, the chip structure comprises a plurality of matrix elements, a switch matrix and a rear-end interface circuit, and each matrix element comprises a cross-shaped horizontal Hall element and a switch device; the switch matrix is composed of switch devices in matrix elements; the cross-shaped horizontal Hall element matrix is an N * M Hall matrix element formed by an integrated 1 * M Hall element matrix in each row; according to the invention, the structure and the circuit of the matrix type magnetic sensing chip which can be used for statically and dynamically measuring multi-dimensional magnetic field distribution in real time in severe environments such as high temperature, high pressure and high radiation are innovated and manufactured; dynamic and static measurement in a multi-dimensional magnetic field space can be achieved, error compensation is carried out through a circuit, it is ensured that the chip can stably work in the high-temperature, high-pressure and high-radiation environment, and it can be ensured that the chip has high linearity, sensitivity and accuracy.

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

The invention discloses a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the steps that a substrate is provided, a stacking layer formed by alternately arranging a plurality of first sacrificial layers and a plurality of second sacrificial layers is formed on the substrate, and the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating through the stack layer, extending into the substrate, and forming a cavity in the substrate; forming a protective layer in the concave cavity of the substrate; taking the protection layer as an etching stop layer, and transversely etching a part of the second sacrificial layer in the stack layer along the vertical opening to form a plurality of side cavities which are arranged at intervals in the vertical direction; forming a plurality of lower electrodes on the surface of the second sacrificial layer exposed by the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, wherein the capacitor dielectric layer is also located in the vertical opening and is in contact with the protection layer; an upper electrode is formed on the surface of the capacitor dielectric layer, and the multiple lower electrodes, the capacitor dielectric layer and the upper electrode form a capacitor structure. The embodiment of the invention can improve the performance of the device.

To provide a semiconductor device with excellent electric characteristics.SOLUTION: A transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 thereon, an oxide 230a thereon, an oxide 230b thereon, an oxide 243a and an oxide 243b thereon, conductors 242a and 242b on the oxides 243a and 243b, insulators 272a and 272b on the conductors 242a and 242b, an oxide 230c on the oxide 230b, an insulator 250 thereon, and a conductor 260 existing thereon and overlapping with the oxide 230c. The oxide 230c is in contact with each of side surfaces of the oxides 243a and 243b and side surfaces of the conductors 242a and 242b. In an insulator 274 and an insulator 280 on the transistor 200, regions 241a and 241b with higher nitrogen concentration than the other regions are formed near an interface with the conductors 240a and 240b.SELECTED DRAWING: Figure 1

A semiconductor device with a spaced supply voltage and ground reference is disclosed. A stack of semiconductor dies includes a first semiconductor die, one or more second semiconductor dies, and first and second contacts. A gap fill is disposed over a distal end of the one or more second semiconductor dies opposite the first semiconductor die. A first rail (e.g., supply voltage) is disposed at a distal end of the gap fill opposite the first semiconductor die, and a first via extends from the first rail to the first contact. A layer of dielectric material is disposed at least partially over the first rail. A second rail (e.g., ground reference) is disposed at the layer of dielectric material, and a second via extends from the second rail to the second contact. Third and fourth exposed contacts are coupled to the first and second rails, respectively.

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A plurality of nanosheet recesses are formed within a substrate. A placeholder structure is formed on a bottom surface within each nanosheet recess. A first source / drain region is formed within a first nanosheet recess. A second source / drain region is formed within the second nanosheet recess. The semiconductor structure is flipped. The substrate is removed respective to a sidewall spacer of the placeholder structure and a first etch stop layer of the placeholder structure. Backside interlayer dielectric is formed. A backside contact trench to the second source drain region is formed by removing a portion of the backside interlayer dielectric over the second source / drain region and removing exposed portions of the first etch stop layer, the sidewall spacer, and a silicon buffer layer of the placeholder structure. A backside contact is formed within the trench.

The invention provides a forming method of a double-shallow-trench isolation structure with different depths and a semiconductor device, and the method comprises the steps: S1, providing a substrate which comprises a first region and a second region; s2, sequentially forming a first dielectric layer, a first hard mask layer and a second hard mask layer on the substrate, wherein the first hard mask layer and the second hard mask layer are made of different materials; s3, forming a first initial opening in the second hard mask layer of the first region, performing etching by taking the second hard mask layer as a mask, and stopping forming a first opening on the surface of the first dielectric layer; s4, forming a second initial opening in the second hard mask layer of the second region, etching by taking the second hard mask layer as a mask, and stopping on the surface of the substrate to form a second opening; s5, removing the second hard mask layer; and S6, etching the first opening and the second opening at the same time by taking the first hard mask layer as a mask, forming a first shallow trench below the first opening, and forming a second shallow trench below the second opening. The depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first dielectric layer.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps of performing primary etching on a semiconductor substrate to form a stack structure, wherein the stack structure comprises an active structure and a first sacrificial layer; forming a pseudo gate structure covering the stacked structure in the gate region; etching the stack structure which is not covered by the pseudo gate structure to form a first deep groove; epitaxially growing a first source drain structure in the first deep groove based on the first active structure in the gate region; removing the pseudo gate structure and the first sacrificial layer to expose the active structure in the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer; reversing and removing the semiconductor substrate; epitaxially growing a second source drain structure in the first deep groove based on a second active structure in the gate region; and depositing a metal material on the second gate dielectric layer to form a second gate electrode layer.

The invention discloses a Micro-LED epitaxial structure suitable for low working current density and a preparation method thereof, and relates to the technical field of semiconductor devices. The Micro-LED epitaxial structure comprises a substrate, a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum well light-emitting layer and a P-type semiconductor layer. The multi-quantum well light-emitting layer comprises a first short-wave multi-quantum well layer, a second long-wave multi-quantum well layer and a third short-wave multi-quantum well layer which are sequentially arranged from bottom to top; the In component in the first short-wave multi-quantum well layer and the In component in the third short-wave multi-quantum well layer are both smaller than the In component in the second long-wave multi-quantum well layer. According to the Micro-LED epitaxial structure, the quality of a multi-quantum well light-emitting layer can be remarkably improved, the matching degree of electron hole concentration in a light-emitting quantum well area is improved, the radiation recombination efficiency of the light-emitting quantum well area is improved, and therefore the lighting effect of a Micro-LED chip under the low working current density is improved, and the service life of the Micro-LED chip is prolonged. The problem that an epitaxial structure of a traditional visible light LED is low in luminous efficiency under the low working current density is solved.

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device and particularly to MOSFET transistors. A semiconductor device including a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region, two first well regions including two source regions, two second well regions, a scatter oxide layer, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two first well regions are adjacent to the first-conductivity-type epitaxy layer and each of the two first well regions is adjacent to one second well region, the JFET region is adjacent to the two second well regions, the scatter oxide layer is adjacent to the two source regions, the two first well regions, the two second well region and the JFET region, and a width of the JFET region is greater near the scatter oxide layer than in part closest to the first-conductivity-type substrate.

A semiconductor device comprises a gate cut portion disposed between a first gate region and a second gate region. The gate cut portion comprises a dielectric liner layer disposed around a vacant area. The dielectric liner layer encloses the vacant area, and the gate cut portion isolates the first gate region from the second gate region.

A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component. A shielding layer is formed over the encapsulant. The shielding layer includes a plurality of graphene-coated metal balls in a matrix. The shielding layer is sintered using intensive pulsed light (IPL) radiation.

The invention provides a packaging and sintering evaluation method and device for a power semiconductor device, and the method comprises the steps: carrying out the non-destructive scanning through a high-frequency acoustic microtechnique, carrying out the correction through combining with a temperature-sound velocity relation model, achieving the real-time monitoring of a sintering process, and solving a problem that the transient change cannot be captured. Through frequency domain conversion and an improved inverse Fourier transform algorithm, precise reconstruction of the microstructure of the sintering interface is realized, and the limitation that the microstructure is difficult to evaluate in the prior art is overcome. Based on the reconstructed microstructure, a detailed three-dimensional geometric model is established, and time domain finite element analysis is performed, so that comprehensive thermal stress evolution data is obtained, and the defect of surface information of a traditional method is overcome. And quantitative evaluation is carried out by using the multi-dimensional feature space and the preset discrimination model, so that comprehensive analysis of the sintering quality is realized, and the defect of lack of comprehensive quantitative evaluation capability is overcome. Through organic combination of the steps, the accuracy and comprehensiveness of packaging and sintering evaluation are remarkably improved.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a gate structure and a side wall on the substrate, and enabling the gate structure to comprise a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer; forming a first patterned photoresist layer covering the NMOS region; forming grooves in the substrate at two sides of the gate structure in the PMOS region, and reserving an amorphous carbon layer with a partial thickness on the second hard mask layer; the first patterned photoresist layer is removed; and removing the amorphous carbon layer by adopting an ashing process. In the process of forming the groove in the PMOS region, the amorphous carbon layer protects the second hard mask layer below the amorphous carbon layer from being thinned, and after the amorphous carbon layer is removed, the thickness of the second hard mask layer in the two regions can be ensured to be consistent, so that the height of the dummy gate is ensured to be consistent, and the electrical performance of the device is improved.

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

Horizontal Cavity Surface Emitting Lasers (HCSELs) with angled facets may be fabricated by a chemical or physical etching process, and the epitaxially grown semiconductor device layers may be transferred through a selective etch and release process from their original epitaxial substrate to a carrier wafer.

A method of fabricating a semiconductor device includes forming a memory cell array stack including a vertical stack of pad portions over a first substrate, forming first bonding pads each coupled to a different one of the pad portions in the vertical stack, forming control circuits including a plurality of sub-word line drivers over a second substrate, forming multi-layer level metal wiring coupled to the sub-word line drivers, forming second bonding pads coupled to the multi-layer level metal wiring, and performing a wafer bonding process for electrical coupling between the memory cell array stack and the control circuits.

A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.