26901 results about "Semiconductor device" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

The invention relates to the technical field of intelligent control of test equipment, and discloses a semiconductor device test equipment control system and method based on industrial data processing, and the method comprises the steps: collecting multi-source heterogeneous data of semiconductor device test equipment, and carrying out the preprocessing; constructing a structural causal model, and performing root cause identification through anti-fact reasoning by using the structural causal model; constructing an abnormal test fingerprint and a knowledge base; generating an intervention scheme, evaluating the generated intervention scheme, and selecting an optimal intervention scheme; processing the detected anomaly, and generating and implementing a preventive control strategy based on historical anomaly data and a causal analysis result; according to the invention, by introducing innovative technologies such as causal inference, anti-factual inference, abnormal test fingerprint identification and Monte Carlo tree search, intelligent control of semiconductor test equipment is realized.

The invention discloses a self-adaptive switching system and method for power supply and distribution, and the system comprises a data collection module, an analysis module, a modeling module, a decision module, an execution module and an early warning module, and the data collection module generates a real-time monitoring signal; the analysis module performs dynamic weighted evaluation according to the real-time monitoring signal and generates an evaluation signal; the modeling module constructs a virtual model of the power supply system and generates an analog signal; the decision signal generates a control signal containing a path selection instruction; the execution module controls the semiconductor device to switch the physical connection state of the power supply according to the control signal and generates a switch feedback signal; and the early warning module forms an equipment health assessment result according to the switch feedback signal and an abnormal arc signal when the execution module switches the connection state and transmits the result to the decision module. The self-adaptive switching system for power supply and distribution can solve the problem that a traditional power supply and distribution switching system depends on a single threshold to judge the state of a power supply and cannot comprehensively evaluate the quality of electric energy.

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention belongs to the technical field of semiconductor device packaging, and discloses a power semiconductor module three-dimensional stacking vertical commutation low-inductance packaging structure. The two vertical commutation structures are stacked and integrated on the same substrate; different from traditional two-dimensional packaging in which all elements are laid on a two-dimensional plane, three-dimensional stacked packaging suitable for power devices is proposed for the first time, and power loops are stacked and integrated; the magnetic fluxes of the stacked power loops are cancelled, so that ultra-low inductance (pH level) integration is realized; under the condition that the areas of the substrates are the same, the capacity of the module is doubled; meanwhile, dynamic current sharing design is considered, and one driving chip simultaneously drives eight GaN chips to realize parallel dynamic current sharing for the first time; the method is suitable for various topological structures including half-bridge structures, full-bridge structures, three-level ANPC structures and the like; the method is suitable for various packaging schemes, including PCB on DBC packaging, DBC substrate welding / sintering packaging and embedded packaging. Taking the packaging of the half-bridge module double-sided parallel PCB on DBC as an example, low-inductance, low-thermal-resistance and high-power-density integration is realized.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

The invention discloses an electromagnetic field simulation grid adaptive generation method based on a neural network. The method comprises the following steps: performing mesh generation on a semiconductor device simulation model to obtain original generation data, and constructing node features; an undirected graph is constructed, graph nodes of the undirected graph adopt node features of grid points, and connecting edges adopt Euclidean distances between the grid points and adjacent grid points; inputting the undirected graph into a double-branch neural network, and outputting a predicted node position; and correcting each node of the original subdivision data by using the predicted node position obtained by the double-branch neural network to form new subdivision data for electromagnetic field simulation. According to the method, physical field information can be fused to efficiently adjust the node density, and the geometric boundary and topological structure characteristics of the device can be strictly kept.

The invention discloses a solar cell performance prediction method and device based on a physical information fusion model, and relates to the technical field of computer data processing and semiconductor characterization. According to the technical scheme provided by the invention, the deep neural network architecture is adopted to perform feature extraction and fusion on the multi-dimensional spectral information, the prediction precision is improved by more than 35%, and the reliability is improved by more than 40%, so that the prediction performance is remarkably improved; an innovative physical information fusion loss function is adopted for training the model and comprises a data-driven prediction loss item and a constraint loss item based on a semiconductor device physical rule, and a prediction task and a physical principle are deeply fused, so that the prediction model can understand a physical causal relationship between spectral characteristics and device performance, and the prediction efficiency is improved. According to the method, more accurate performance prediction and better physical interpretability are realized, multiple physical constraints are adopted to standardize the prediction result, so that the model prediction result conforms to the physical principle of the semiconductor device, and the physical rationality and engineering application value of the prediction result are improved.

The invention provides an LED packaging device and a preparation method and application thereof, and relates to the technical field of semiconductor devices.The preparation method comprises the steps that packaging silica gel and fluorescent powder are mixed according to a preset proportion, and then a film with the preset thickness is prepared through a film scraping machine; curing the membrane at a first preset temperature for a first preset time, and completing primary curing to obtain a semi-cured fluorescent sheet; transferring the semi-cured fluorescent sheet to the flip LED chip which is subjected to die bonding in the bracket, and carrying out vacuum pressure sinking, so that the semi-cured fluorescent sheet is completely attached to the surface and the side surface of the flip LED chip; curing the semi-cured fluorescent sheet subjected to vacuum pressure sinking at a second preset temperature for a second preset time, and completing secondary curing to obtain a cured finished product; according to the LED packaging device and the manufacturing method thereof, the technical problems that in the prior art, the stability of the dispensing glue amount of the LED packaging device is poor, fluorescent powder is not evenly distributed, and consequently the brightness and the concentration degree are reduced can be solved.

The invention provides a semiconductor equipment task scheduling control method and system, equipment and a medium, and the method comprises the steps: collecting multi-factor operation data and operation task data of an operation arm, splitting a task into a plurality of sub-tasks based on the motion type of the operation arm, and carrying out the task scheduling of the operation arm based on a task unique identifier, a sub-task identifier and an operation arm identifier; associating the multi-factor operation data with the operation task data, and constructing a mapping structure; constructing a node set based on the mapping structure, screening the node set to form a candidate node pair set, executing conflict detection according to a conflict detection strategy for each node pair in the candidate node pair set, generating a conflict edge set, and generating a path conflict graph based on the node set and the conflict edge set, the conflict detection strategy comprises station conflict detection, time conflict detection and space conflict detection; and dynamically adjusting the tasks in the candidate sub-task set in real time based on the path conflict graph and the conflict resolution strategy.

A semiconductor device has a first interconnect structure, second interconnect structure, and a semiconductor die disposed between the first interconnect structure and second interconnect structure. The semiconductor die can have a photonic area. An embedded interconnect structure is disposed between the first interconnect structure and second interconnect structure. The embedded interconnect structure has a height sufficient to span a gap between the first interconnect structure and second interconnect structure. The embedded interconnect structure can be a plurality of conductive posts, and a second encapsulant deposited around the conductive posts. The embedded interconnect structure can be a plurality of e-bar structures, and a second encapsulant deposited around the e-bar structures. The embedded interconnect structure can also be a plurality of vertical loop wires, and a second encapsulant deposited around the vertical loop wires. A first encapsulant is deposited around the semiconductor die and embedded interconnect structure.

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

A semiconductor device may include: a first conductive line including an opening passing through the first conductive line; a second conductive line disposed over the first conductive line and spaced apart from the first conductive line; a first electrode layer buried in the opening; a selector layer disposed in the opening and surrounding side surfaces of the first electrode layer; and a variable resistance layer disposed over the selector layer and the first electrode layer.

The invention belongs to the technical field of semiconductor devices, and particularly relates to an optical waveguide device based on a glass substrate, which comprises the glass substrate and a transition layer, an X silicon-based waveguide layer is arranged on the first surface of the transition layer, a heterogeneous material chip layer is integrated on the X silicon-based waveguide layer, the first surface of the X silicon-based waveguide layer is coated with a protective layer, and the protective layer is arranged on the first surface of the transition layer. The protective layer covers the glass substrate, the X silicon-based waveguide layer and the heterogeneous material chip layer at the same time; wherein the transition layer comprises an X element which is the same as that of the X silicon-based waveguide layer, through the above structure, the optical waveguide device with multiple layers of transition function areas is provided, the problems that the surface roughness of a large glass substrate is high, and the warping possibility is higher due to size effect amplification can be solved, and the optical waveguide device is suitable for large glass substrates. On the premise of fully utilizing the advantages of low cost and high performance of the glass substrate, the design of a large-size optical waveguide device for inhibiting packaging warping is realized.

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

The invention relates to the technical field of semiconductor devices, in particular to a low-working-current-density green light Micro-LED epitaxial structure and a preparation method thereof. The epitaxial structure comprises a substrate, a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum well light-emitting layer and a P-type semiconductor layer. The electron blocking layer is not arranged on the multi-quantum-well light-emitting layer, the multi-quantum-well light-emitting layer comprises four sub-layers including a first light blue light multi-quantum-well layer, a second blue light multi-quantum-well layer, a third green light multi-quantum-well layer and a fourth light blue light multi-quantum-well layer, and the In component content in the third green light multi-quantum-well layer is larger than that in other layers. The third cyan light multi-quantum well layer is a main light-emitting unit and is not provided with an electron blocking layer, so that the blocking effect on hole injection can be eliminated, the hole injection efficiency of the P-type semiconductor layer is remarkably improved, and the matching degree of electron hole concentration in a multi-quantum well light-emitting layer region is improved.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

The invention relates to a chip integrated heat dissipation system and a preparation method thereof, and belongs to the technical field of heat dissipation of semiconductor devices. The chip integrated heat dissipation system comprises a nano-diamond transition layer attached to a chip. A micro-column array supporting layer is arranged on one side, far away from the chip, of the nano-diamond transition layer; the micro-column array supporting layer is in contact with one surface of the diamond film, and the other surface of the diamond film is attached to the three-dimensional micro-channel heat dissipation layer. The invention also provides a preparation method of the chip integrated heat dissipation system. The chip integrated heat dissipation system provided by the invention has the advantage of efficient heat dissipation, and through the combination of the three-dimensional structure and the high heat conduction characteristic of diamond, the heat dissipation power density is remarkably improved, the junction temperature of the chip is reduced, and the heat dissipation requirement of a high-power device is met. The heat dissipation performance reliability is high, the thermal stress is eliminated through the gradient structure design, the interlayer binding force is improved, and the stable performance is still kept after multiple thermal cycles. And the preparation process is good in compatibility and convenient for large-scale production.

The invention relates to a simulation method for a semiconductor device, electronic equipment and a computer readable storage medium. The method comprises the steps that a multi-way tree structure is constructed based on grid data of a gridded semiconductor device, the multi-way tree structure at least comprises a root node, a plurality of layers and a plurality of leaf nodes, and each leaf node represents a corresponding polyhedron in a plurality of polyhedrons in the gridded semiconductor device; in response to the determination of the first spatial position of the particle in the semiconductor device, determining a first search path from the root node to a first leaf node in the plurality of leaf nodes based on the corresponding relationship between each leaf node and the corresponding polyhedron; and in response to the particle moving from the first spatial position to a second spatial position within the semiconductor device, determining a second search path in the multi-way tree structure based on the first search path to determine a second leaf node representing the polyhedron where the second spatial position is located. According to the method, the ion implantation simulation performance is effectively improved.

The invention belongs to the technical field of semiconductors, and discloses a method for manufacturing a sigma trench in a semiconductor device, which comprises the following steps of: providing a substrate which comprises a first device region and a second device region; a PMOS (P-channel Metal Oxide Semiconductor) region gate and a PMOS gate mask layer are formed on the first active region of the first device region; exposing the top of the PMOS gate mask layer outside the first device region photoresist layer; depositing a deposition silicon oxide layer on the top of the second device region and the top of the PMOS gate mask layer; removing the photoresist layer in the first device region; etching to remove the natural silicon oxide layer on the surface of the first active region, further etching silicon in the first active region, and forming a U-shaped groove in the semiconductor substrate in the first device region; and carrying out TMAH etching on the U-shaped groove to form a sigma groove. According to the invention, in the process of embedding germanium-silicon into the source and the drain, the height difference between the PMOS and the NMOS is avoided, and the subsequent process is not influenced.

The invention relates to the technical field of sintering evaluation, in particular to a power semiconductor device packaging sintering evaluation method and device based on image analysis. The method comprises the following steps: obtaining a multi-source heterogeneous monitoring image set of a semiconductor device, carrying out multi-modal space corresponding relation identification, carrying out global registration precision compensation, and constructing a multi-modal space registration image matrix; carrying out multi-level voxelization analysis reconstruction based on the multi-modal space registration image matrix, carrying out structure deviation mapping modeling, and constructing a sintering three-dimensional structure deviation distribution map; and performing multi-directional defect detection according to the multi-modal space registration image matrix, performing defect cascade failure modeling, and constructing a multi-defect structure integrity association network. According to the method, accurate three-dimensional sintering structure defect analysis is realized, the quality of the sintering structure is quantified in all directions, and intelligent optimization and rapid iteration of a sintering process are promoted.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

A semiconductor device includes a semiconductor layer having first and second principal surfaces, an insulated gate bipolar transistor (IGBT) region formed in the semiconductor layer, and a diode region formed adjacent to the IGBT region in a first direction. A plurality of gate trenches are arranged in the IGBT region and extend in a second direction intersecting the first direction. Each trench includes a gate conductive layer embedded through a gate insulating layer, and unit cells are defined between adjacent trenches. An emitter region is formed on the first principal surface of each unit cell. The emitter region of a unit cell located closer to the diode region has a smaller area than the emitter region of a unit cell located farther from the diode region.

A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.

The utility model discloses a valve device and a semiconductor device processing device. The valve apparatus includes: a valve body including an external coil therein; the valve plate is movably arranged in the valve body, and the opening degree of the valve equipment is adjusted by adjusting the pose of the valve plate; and an internal coil provided inside the valve plate, the internal coil generating an eddy current through an alternating magnetic field generated in the valve body by an alternating voltage applied to the external coil to inductively heat the valve plate. By means of the valve equipment, the surface of the valve plate can be directly heated, the temperature of the valve plate is increased, and therefore blockage of the valve plate caused by deposition of reaction by-products on the valve plate in the carbon mask deposition process is reduced.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

The invention relates to the technical field of semiconductor device manufacturing, solves the technical problem that in the prior art, automatic grain digging treatment cannot be carried out on detected LED support defective products, and provides a grain digging control method, device and equipment for LED support defective products. Acquiring a real-time image of the to-be-detected LED bracket under a preset target illumination condition; performing visual detection processing on the real-time image, and judging whether the to-be-detected LED bracket is a defective bracket product or not according to a visual detection processing result; when the to-be-detected LED bracket is judged to be a defective bracket product, defect position detection is carried out on the defective bracket product to obtain defect position information; according to the defect position information, defective stent particles in the defective stent products are removed, and particle digging control over the defective stent products is achieved. According to the automatic grain digging device, automatic grain digging treatment can be accurately carried out on the LED support defective products.

Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.

A method of manufacturing a semiconductor device includes: preparing semiconductor substrate having a front surface and a back surface opposite to each other, the semiconductor substrate being of a first conductivity type; forming a device structure in the semiconductor substrate, at the front surface; performing thermal oxidation to form a gate insulating film and depositing a polysilicon to form a plurality of gate electrodes; removing the polysilicon at the back surface of the semiconductor substrate while leaving an oxide film formed at the back surface and a side surface of the semiconductor substrate by the thermal oxidation; forming a surface electrode on the device structure; and forming a plating film on the surface electrode while continuing to leave the oxide film at the back surface and the side surface of the semiconductor substrate.