950 results about "Electron mobility" patented technology

The invention discloses a SiC MOSFET gate oxide layer degradation monitoring method based on turn-off oscillation, and the method comprises the steps: measuring the drain-source current change rate diDS / dt when a SiC MOSFET is turned off through the source stray inductance voltage vcir, and carrying out the measurement of the gate oxide layer degradation of the SiC MOSFET based on the offset of the negative temperature sensitivity of the threshold voltage VTH in the diDS / dt and the positive temperature sensitivity of the electron mobility mu. Zero temperature sensitivity of a source stray inductance voltage negative peak value vcircmin is realized by adjusting a driving resistor RG and a negative voltage VEE during turn-off, and the gate oxide layer degradation degree of the SiC MOSFET is monitored under a selected monitoring driving resistor RGM and a turn-off gate voltage VEEM. The monitoring method is high in universality and has a good monitoring effect on degradation of gate oxide layers of SiC MOSFETs of different models; the temperature influence is extremely small, so that the device can work in an environment with large temperature fluctuation; a pin of a monitored device does not need to be used as a measurement interface, so that the system invasiveness is small; the parameter measurement methods are many and mature; and the method has great online application potential.

Lateral III-N devices such as AlGaN / GaN HEMTs can have structures which serve to improve performance and reduce current degradation. The III-N device can include a conductive substrate and a III-N material structure that includes a III-N buffer layer, a III-N channel layer and a III-N barrier layer where a compositional difference induces a 2DEG channel therein. The first portion is in ohmic contact with the 2DEG channel and the second portion extends over a top surface of the III-N barrier layer and is in direct contact with the top surface of the III-N barrier layer. The device further includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage which is greater than the drain-to-substrate pinch-off voltage, and the 2DEG channel is fully depleted of charge below the second portion of the drain electrode when the III-N device is biased at or above the maximum rated drain-to-source operating voltage.

The invention belongs to the field of organic electroluminescence, and discloses an electron transport layer material and a preparation method and application thereof. The structure of the material of the electron transport layer is as shown in a chemical formula I: # imgabs0 #. The compound of the material of the electron transport layer provided by the invention is composed of 9-alkyl-9-phenylfluorenyl, a triazine group and cyano-substituted aryl or heteroaryl, and the groups have high electron affinity to form an efficient electron transport channel; the organic light-emitting material also has good thermal stability, and as an electron transport layer material of an organic electroluminescent device, the organic light-emitting material has the characteristics of low driving voltage, high luminous efficiency and long service life.

The invention provides a 3C-SiC composite epitaxial structure and device structure based on 4H-SiC, and the composite epitaxial structure comprises a 4H-SiC substrate, an N-type doped epitaxial layer, a P-type doped buried layer, a carrier tunneling region, and a 3C-SiC epitaxial layer. The N-type doped epitaxial layer is arranged on the 4H-SiC substrate; the 3C-SiC epitaxial layer is subjected to secondary epitaxy or bonded on the surface of the N-type doped epitaxial layer; a carrier tunneling region is formed on a contact interface layer of the 3C-SiC epitaxial layer and the N-type doped epitaxial layer; and the P-type doped buried layer ions are implanted into the upper region of the N-type doped epitaxial layer. The structure can effectively solve the problems that in the prior art, when 4H-SiC serves as a substrate to prepare a SiC-MOS device, improvement of interface state density and channel electron mobility is limited, the conduction capacity of the device is poor, and the electrical performance and the long-term reliability are poor. The composite epitaxial structure and the device structure are high in device conduction capability and good in electrical performance and long-term reliability.

The invention discloses a junction temperature testing device and method for a high-electron-mobility transistor. A current measuring module in the junction temperature testing device for the high-electron-mobility transistor is used for acquiring current flowing through a tested device; the power supply module is electrically connected with the other end of the switch module, and the power supply module and the switch module are connected in parallel with the bus capacitor; the control module is electrically connected with the control end, the driving end and the regulation and control end of the switch module, and the control module is used for providing switching signals for the control end, the driving end and the regulation and control end of the switch module so as to control the switching states of the switch protection module, the tested device and the switch module; the heating plate is used for heating a tested device; the temperature detection module is used for measuring the temperature of the detected device; and the waveform analysis module is electrically connected with the control module, the temperature detection module and the current measurement module, and is used for obtaining and forming an experimental oscillogram of the tested device at the temperature according to the temperature, the current and the conduction time of the tested device controlled by the control module.

The utility model relates to the technical field of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) testing, and discloses a power MOSFET junction temperature testing device which comprises a high electron mobility transistor, a driving resistor R3, a current-limiting resistor R2 and a current source Im, the other end of the driving resistor R3 is electrically connected with the grid electrode of the high electron mobility transistor; the other end of the current-limiting resistor R2 is electrically connected with a drain electrode of the high-electron-mobility transistor, a source electrode of the high-electron-mobility transistor is electrically connected with a drain electrode and a grid electrode of the power MOSFET, and the current source Im is electrically connected with the drain electrode and the source electrode of the power MOSFET and provides test current for a body diode of the power MOSFET; during actual use, the current source is used for continuously applying test current to the body diode of the power MOSFET, so that heat loss in the current switching process is avoided, and the accuracy of junction temperature measurement is ensured.

The invention discloses a white organic light-emitting device and a display device, the white organic light-emitting device comprises a first electrode, a second electrode and a light-emitting layer located between the first electrode and the second electrode, the light-emitting layer comprises a green light-emitting layer, a blue light-emitting layer and a plurality of red light-emitting layers which are distributed in a stacked mode, the red light-emitting layer is in contact with the green light-emitting layer; along the direction close to the green light-emitting layer, the hole mobility of the red light-emitting layers is gradually reduced, and the electron mobility of the red light-emitting layers is gradually enhanced. The white organic light-emitting device provided by the embodiment of the invention can effectively improve the color cast problem under high current density.

The invention belongs to the technical field of photoelectric semiconductor devices, and particularly relates to an infrared organic photoelectric sensor, an array and a chip, the infrared organic photoelectric sensor is used for sensing light, and the sensor comprises a cathode, an electron transport layer, a photosensitive layer, a hole transport layer and an anode which are stacked in sequence; the electron mobility of the electron transport layer and the hole mobility of the hole transport layer meet the following relation: 0.01 < = [mu] h / [mu] e < = 100; wherein [mu] h represents the hole mobility of the hole transport layer, and [mu] e represents the electron mobility of the electron transport layer. Transmission, extraction and collection of carriers in a device are balanced by regulating and controlling the relation between the electron mobility of the electron transport layer and the hole mobility of the hole transport layer, and then the sensitivity of the infrared organic photoelectric sensor and the imaging definition and resolution of a focal plane array device of the infrared organic photoelectric sensor are improved.

The invention belongs to the technical field of power semiconductors, and relates to a dynamic on-resistance test circuit of a GaN high electron mobility transistor. The circuit comprises a UIS test circuit, a DPT test circuit, a clamping circuit and a driving circuit, and is characterized in that two semiconductor switches can gate the UIS test circuit and the DPT test circuit, UIS test and subsequent DPT test can be carried out under the condition that a device is not moved, and the introduced clamping circuit can indirectly test the conduction voltage drop of the tested device. The test circuit can be used for testing package-level device products, provides a basis for production, research and development, characteristic characterization, mass production test, reliability evaluation and application evaluation of GaN HEMT, integrates UIS and DPT test circuits together compared with a traditional test circuit, improves the test efficiency and reduces the test cost. Meanwhile, errors caused by the influence of the process and the environment on the result when the device is transferred due to the fact that the time from the application of the electric pressure to the DPT test is too long are reduced.

The invention relates to the field of gallium nitride high electron mobility transistor (GaN HEMT) compact modeling, and provides a p-GaN gate HEMT model establishment method based on a physical guided neural network (PGNN) in order to solve the problem of p-GaN gate HEMT compact model development, and the method comprises the following steps: constructing a p-GaN gate HEMT transistor model by using a TCAD simulation tool, generating a model sample, and extracting simulation data; constructing a DerivNet model and a loss function based on a physical guidance neural network; and finally, performing model training by using the simulation data to obtain the p-GaN gate HEMT model based on the physical guidance neural network.

The invention belongs to the field of organic electroluminescent materials, and discloses a host material, an organic electroluminescent material containing double hosts and an organic electroluminescent device. In the organic light-emitting device containing the double hosts, the first host compound has higher electron mobility and is stable in structure. According to the organic electroluminescent device, triplet excitons are dispersed on two main bodies by using a double-main-body material, triplet-triplet annihilation is reduced, the driving voltage of the organic electroluminescent device is reduced, the luminous efficiency of the device can be improved, and the service life of the device can be prolonged.

A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

The invention belongs to the field of organic electroluminescence, and discloses an organic electroluminescence material as well as a preparation method and application thereof. The structure of the organic electroluminescent material is as shown in a chemical formula I: # imgabs0 #. According to the organic electroluminescent material compound provided by the invention, an aryl-substituted dibenzofuran group and a triarylamine group are bridged through a naphthylene group to form a mother nucleus main body, the rigid dibenzofuran structure can effectively enhance the structural stability, and the existence of the triarylamine group can improve the hole transport efficiency of the material; furthermore, the naphthylene group is bridged between the two main body structures, so that a more efficient conjugated system can be formed, the electron mobility of the whole material is improved, and the device has high luminous efficiency and long service life, and can maintain lower driving voltage at the same time.

A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further comprising: a III-nitride high-electron-mobility transistor (HEMT), the III-nitride HEMT comprising a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and to the first gate terminal; and a short-circuit detection circuit operatively connected to the first drain terminal and the first source terminal, the short-circuit detection circuit being configured to: sense a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit, the first interface circuit being configured, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off, and / or to cause a voltage across the first gate terminal to be reduced.

The invention provides an oxazolobenzocarbazole compound, an organic electroluminescent device and a display device, and relates to the technical field of organic electroluminescent materials. The oxazolobenzocarbazole compound disclosed by the invention has a proper energy level and good electron mobility, and can be used as an electron transport material to effectively reduce the potential barrier of electron transport and effectively block the diffusion of holes to one side of an electron transport layer, so that the luminous efficiency of a device can be further improved, the driving voltage can be reduced, and the service life can be prolonged.

The embodiment of the utility model relates to an enhancement mode high electron mobility transistor device. An enhanced mode high electron mobility transistor device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas. A high electron mobility transistor device includes a gate structure extending over a top surface of a semiconductor body, biased to electrically control a two-dimensional electron gas, and including a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is made of a layer of conductive material, and the functional layer is made of a layer of two-dimensional semiconductor material and includes a first doped portion having P-type conductivity extending over a top surface of the semiconductor body and interposed along a first axis between the semiconductor body and the gate contact. According to the embodiment of the invention, the low power consumption of the transistor in use is ensured, and the integration of the transistor into an electronic circuit in a design step is simplified.

The invention discloses a capacitive desalination flowing electrode material and a preparation method thereof, and an FCDI device and application thereof, the preparation method of the capacitive desalination flowing electrode material comprises the following steps: dispersing polypyrrole and polyvinylpyrrolidone into a methanol solution containing zinc nitrate hexahydrate and / or cobalt nitrate hexahydrate, and stirring for the first time to obtain a solution A; adding 2-methylimidazole into methanol, stirring for the second time to obtain a solution B, dropwise adding the solution B into the solution A, stirring for the third time to obtain a mixed solution, standing the mixed solution, performing suction filtration, washing, drying and grinding to obtain ZIF-coated PPy powder. The flowing electrode material prepared by the preparation method is relatively high in adsorption capacity, relatively high in electron mobility and not easy to aggregate and settle.

A high electron mobility transistor includes a semiconductor structure, a stepped trench, an electrode, and a gate. The semiconductor structure includes a barrier layer and a channel layer. The barrier layer is disposed on the channel layer. A two-dimensional electron gas is formed at an interface between the channel layer and the barrier layer. The stepped trench is disposed in the semiconductor structure. The electrode is disposed in the stepped trench. The gate is disposed on the barrier layer. The stepped trench has a first width and a second width. The first width is greater than the second width.

Provided are a heterocyclic derivative and an organic electroluminescent device thereof, which relates to the field of organic photoelectric materials. The heterocyclic derivative of Formula I has high electron mobility and great hole blocking performance, and thus the organic electroluminescent device prepared by using the heterocyclic derivative as the electron transport region material, especially the hole blocking material, has low drive voltage and high luminous efficiency. The organic electroluminescent device can also include a hole transport region, and the hole transport region, especially the emissive auxiliary layer, contains the triarylamine compound of Formula II. Since the electron transport region and the hole transport region of the device can effectively balance carriers, which reduces the quenching of excitons and improves the recombination probability of carriers, the device shows low drive voltage and high luminous efficiency.

The present disclosure relates to Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) (100) i.e. a semiconductor device (100) which includes a buffer layer (104) formed on the substrate (120). An unintentionally doped (UID) Gallium Nitride (GaN) channel layer (102) is positioned on the buffer layer (104). A barrier layer (106) is formed on the UID channel layer (102) to enable formation of two-dimensional electron gas (2DEG) at interface between UID GaN channel layer (102) and barrier layer (106). A stress transfer layer (116) having tunable intrinsic compressive mechanical stress is deposited on barrier layer (106) to enhance device performance and reliability. Further, the intrinsic stress in the stress transfer layer (116) is tailored to enhance performance in terms of higher threshold voltage and breakdown voltage, and reliability in terms of reduced dynamic RON under DC and switching stress and stable threshold voltage under ON and OFF state gate stress.

The invention discloses a barrier GaN heterojunction transistor with low source-drain resistance and high Al component and a preparation method thereof, the transistor structurally comprises a substrate, a composite buffer layer, a channel layer, an isolation layer, a barrier layer and a cap layer which are sequentially arranged from bottom to top, source and drain electrodes are arranged at two ends of the surface of the cap layer, and a gate electrode is arranged between the source and drain electrodes. Etching is carried out on a partial region below the source and drain electrodes to form a nano groove array structure, inclined-angle ion implantation activation is carried out, N-type heavy doping is formed near a nano groove, and metal is filled in the nano groove to form the source and drain electrodes. Source and drain electrode metal of the structure is in direct contact with 2DEG, and forms ohmic contact after being annealed together with an N-type heavily doped region, so that the contact resistance is reduced. According to the method, the problem that the resistance value of a source-drain electrode contact resistor prepared by a conventional method of a high-Al-component barrier GaN heterojunction material is large is solved, the output current of a GaN heterojunction high-electron-mobility transistor device is increased, and the preparation process is simple, easy to implement and outstanding in effect.

The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

The invention provides a semiconductor laser element with a spin polarization sub-layer. The semiconductor laser element comprises a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer and an upper limiting layer which are sequentially arranged from bottom to top. According to the semiconductor laser element, the spin polarization sub-layers of a multi-layer structure are arranged between the upper limiting layer and the upper waveguide layer in the semiconductor laser element, and the electron mobility distribution characteristic and the piezoelectric polarization coefficient distribution characteristic of each spin polarization sub-layer are limited. Specific electron mobility distribution and piezoelectric polarization coefficient distribution of the spin polarization sub-layer form an asymmetric discrete potential barrier, lattice distortion structure polarization is modulated, charge dipole momentum net accumulation is increased, the piezoelectric polarization effect of the active layer is regulated and controlled, the quantum restriction effect is suppressed, energy band inclination of the active layer is reduced, and hole injection band order is reduced. The overlapping probability of the electron hole wave function is improved, and the internal quantum efficiency is improved.

The embodiment of the invention relates to a high-electron-mobility transistor and a preparation method thereof, and the high-electron-mobility transistor comprises a substrate; the heterojunction structure is located on the substrate and comprises a channel layer and a barrier layer which are sequentially stacked in the direction away from the substrate, and a two-dimensional electron gas channel is formed in the area, close to the barrier layer, of at least part of the channel layer; the source electrode and the drain electrode are distributed on the heterojunction structure at intervals; a gate layer on the heterojunction structure and between the source electrode and the drain electrode; the RESURF structure layer is located on the heterojunction structure and comprises a first structure part adjacent to the gate layer in the direction parallel to the plane where the substrate is located and a second structure part extending from the first structure part to the direction away from the gate layer; the thickness of the part, located between the first structure part and the channel layer, of the barrier layer is smaller than that of the part, located between the second structure part and the channel layer; therefore, the RESURF structure plays a better role in the device.

The invention provides an enhanced gallium nitride high-electron-mobility transistor. The enhanced gallium nitride high-electron-mobility transistor comprises a substrate; the first epitaxial structure is formed on the substrate, and the first epitaxial structure comprises a channel layer and a barrier layer formed on the channel layer; the passivation layer is formed on the first epitaxial structure; the grid electrode comprises a groove, and the groove penetrates through the passivation layer and the barrier layer and extends into the channel layer; the second epitaxial structure part covers the bottom and the side wall of the groove and the upper surface of the passivation layer on the left side and the right side of the top of the groove; and a gate electrode formed on the second epitaxial structure portion. The groove gate enhanced MIS-HEMT device has the beneficial effects that the uniformity, the process repeatability, the robustness and the reliability of the threshold voltage of the groove gate enhanced MIS-HEMT device are improved.

The invention discloses an HEMT device. The HEMT device comprises a substrate; the channel layer is arranged on one side of the substrate, and the material of the channel layer comprises undoped GaN; the heteroepitaxial structure comprises at least one superlattice structure formed by stacking an AlGaN layer and a GaN layer, and in each superlattice structure, the GaN layer is arranged on the side, away from the channel layer, of the AlGaN layer; the barrier layer is arranged on the side, away from the channel layer, of the heteroepitaxial structure, and the material of the barrier layer comprises AlGaN; and the total thickness of the channel layer and the heteroepitaxial structure is 150-350 nanometers. According to the embodiment of the invention, the heteroepitaxial structure is arranged between the channel layer and the barrier layer, so that a plurality of two-dimensional electron gas channels can be formed, the crowding condition of electrons in the single and two-dimensional electron gas channels is reduced, the electron mobility is improved, and the on-resistance is reduced; by designing the total thickness of the channel layer and the heteroepitaxial structure, the chip manufacturing process does not need to be redesigned in the subsequent process, and the situation that the processing difficulty of the chip manufacturing process in the subsequent process is increased is avoided.

The invention provides a high electron mobility transistor epitaxial structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a sapphire substrate; growing a boron-doped first buffer layer on the sapphire substrate: during growth, gradually reducing a boron component in a reaction material from a first preset value to 0 in a first preset duration, and continuously growing for a second preset duration after the boron component is reduced to 0, so that x in the first buffer layer is gradually reduced, and the boron component is gradually reduced to 0 from bottom to top; a boron-free GaN second buffer layer is grown on the first buffer layer, the growth rate of the second buffer layer is lower than that of the first buffer layer, and the thickness of the second buffer layer is larger than that of the first buffer layer; and sequentially growing a GaN high-resistance layer and a GaN epitaxial layer on the second buffer layer. Compared with the prior art, the defect density of the device can be effectively improved, electric leakage is reduced, and the stability and consistency of the device are improved.

The invention discloses a high-electron-mobility transistor packaging structure and a preparation method, which are applied to the field of driving integrated circuit packaging, and the structure comprises a high-electron-mobility transistor and a plurality of triodes arranged on the surface of one side of the high-electron-mobility transistor, a grid electrode of the high-electron-mobility transistor is positioned on the surface of one side, close to the triode, of the high-electron-mobility transistor; an emitter of the triode is arranged on the surface of one side, close to the high-electron-mobility transistor, of the triode, the emitter is conductively connected with the grid electrode, and the remaining electrodes are all conductively connected with the corresponding pins. A triode is arranged on the surface of one side of a high-electron-mobility transistor, a grid electrode in the high-electron-mobility transistor is arranged on the surface of the side, close to the triode, of the high-electron-mobility transistor, and an emitting electrode in the triode is arranged on the surface of the side, close to the high-electron-mobility transistor, of the triode. And the parasitic inductance of the circuit is reduced while the circuit board area occupied by the device is reduced.

The invention discloses a luminescent material composition, ink, a luminescent device and a display device. The luminescent material composition comprises a host material and a polarity adjusting material, and the absolute value of the ratio of the zero field hole mobility to the zero field electron mobility of the host material is not equal to 1. The luminescent material composition provided by the invention can meet the requirements of products with high comprehensive performance.