190results about How to "Improve reading speed" patented technology

A memory including memory cells having active and passive layers may store multiple information bits. The active layer may include an organic polymer that has a variable resistance based on the movement of charged species (ions or ions and electrons) between the passive layer and the active layer. The passive layer may be a super-ionic material that has high ion and electron mobility. The active layer may be self-assembled from a monomer in a liquid or gas.

According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

Apparatus and methods for optical illumination and/or detection with improved flexibility and/or read speed. The apparatus and methods may include mechanisms for selecting and switching between multiple excitation wavelengths and/or simultaneously reading from a plurality of sample sites. The apparatus and methods may be used with microplates, PCR plates, cell culture plates, biochips, chromatography plates, microscope slides, and other substrates for high-throughput screening, genomics, SNPs analysis, pharmaceutical research and development, life sciences research, and other applications.

The invention relates to a block-chain data storage system and method. The system includes a memory database and a disk database. The memory database and the disk database respectively receive block-chain data written by a block-chain node, and store the block-chain data. When the block-chain data are read by the node, reading from the memory database is firstly carried out by the node, and if reading fails, the block-chain data are read from the disk database, and the read block-chain data are synchronized to the memory database. By adopting the system, reading and writing efficiency of the block-chain data can be effectively improved.

The invention discloses a shared storage message queue-based implementation method for high availability of virtual machines and relates to the field of cloud computing. The shared storage message queue-based implementation method for the high availability of the virtual machines comprises the following steps: initializing a piece of contiguous space on shared storage by a server program to serve as a logical volume; distributing a plurality of contiguous sectors from the logical volume to serve as a sector pool of a client program; acquiring the configuration information of the sector pool and the number of a virtual machine, of which the high availability is enabled, by the client program; sending a heartbeat message by the client program, and updating the timestamp of a virtual machine control block maintained by the client program; receiving the heartbeat message by the server program, and updating the timestamp of the virtual machine control block maintained by the server program by utilizing the timestamp carried in the heartbeat message. According to the shared storage message queue-based implementation method disclosed by the invention, the unnecessary stop time of the virtual machines is avoided; system resource consumption is low by adopting a heartbeat detection mechanism; the performance is high; the service life of the disk of the shared storage is prolonged.

The invention discloses a forestry big data construction method based on a map. The forestry big data construction method comprises the following steps of S1, integrating data; S2, fusing the data; S3, performing check and quality inspection on the fused data according to a preset strategy; and S4, copying forestry data in a database according to a preset relation of a relation database. By the method, structural processing of the forestry data is achieved, the storage and reading efficiencies of the forestry data are improved, data mining and analysis are facilitated, and an information island of the forestry data is eliminated.

Methods and devices are disclosed which apply an excitation-emission matrix (EEM) to a heterogeneous, two-dimensional sample, allowing a considerably larger number of emitting, e.g. fluorescent, labels to be used simultaneously. This may be accomplished by employing a spectroscopic method of excitation-emission matrices which allows discrimination of species with similar emission spectra, and also allows positive identification of energy transfer between emitting species. The methods and devices may employ a novel excitation-light scanning technique which allows imaging of the emission from the heterogeneous sample both in two spatial dimensions (length and width) and in two spectral dimensions (excitation and emission wavelength). This light scanning technique maximizes the throughput of excitation light, increasing the sensitivity and hence the reading speed of the instrument.

A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

A recording medium including a ferroelectric layer, a nonvolatile memory device including the recording medium and methods of wiring and reading data in the memory device. The recording medium includes: a lower electrode; a ferroelectric layer to which data is recorded, formed on the lower electrode; a barrier layer formed on the ferroelectric layer; and a semiconductor layer formed on the barrier layer. The nonvolatile memory device includes a probe that reads and writes the data. Furthermore, in the method of writing data, a writing voltage is applied between the probe, which contacts the semiconductor layer, and the lower electrode and, in the method of reading data, a state of a remanent polarization of the ferroelectric layer is determined by applying a reading voltage between the probe and the semiconductor layer.

The embodiment of the invention discloses a solid state hard disc. The hard disc comprises a control module, a ferroelectric memory FRAM buffer module, an interface module and a storage module, wherein, the control module is used for controlling work of the whole solid state hard disc, and transmitting a management information data storage command of the solid state hard disc; the ferroelectric memory FRAM buffer module is used for receiving the management information data storage command, and storing the management information data of the solid state hard disc; the interface module is used for analyzing user data with a specific protocol format transmitted by an external computer to obtain user storage data for storage; and the storage module is used for storing the user storage data acquired by analyzing the interface module. Embodiment of the invention also discloses a method for storing data correspondingly. Through the technical proposal, the reliability of the solid state hard disc is improved, and the reading speed of data is improved.

The invention relates to a two-dimension code and a method for recognizing the same. Code words in the two-dimension code are in the shape of a centrosymmetric polygon and are divided into a positioning portion and a data portion, and the positioning portion comprises a polygonal center point, a polygonal vertex and a positioning point arranged on a connecting line between the center point and the vertex. The data portion consists of a code element region and code elements in the code element region, and the code element region is arranged in the polygon. Compared with the prior art, the two-dimension code in the technical scheme has a wider code value, higher recognition efficiency and better antijamming capability and error correcting capability.

The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.

The present invention is applicable to the field of computer technology, and discloses a data storage method and system, and a terminal device. The method comprises: reading a data block index table,searching for an idle data block according to a data block index table, and updating a data block index node corresponding to the idle data block; allocating a cache for the intra-block index table inthe idle data block; cyclically reading data in a data buffer region of each channel; if the length of the data in the data buffer region of the target channel is greater than or equal to a preset time length, reading data of the preset time length in the data buffer region of the target channel, writing the data of the preset time length into the idle data block, and updating the data block index node corresponding to the idle data block and the intra-block index table in the cache; and, if the idle data block is full, writing the intra-block index table in the cache to the tail end of the idle data block, and continuing executing the step of searching for the idle data block according to the data block index table. The writing positions can be reduced, and the disk writing speed can beimpproved.

The invention provides a method for reading data by utilizing a multilevel cache and a multilevel cache apparatus for caching the data. The data loss risk can be lowered; the time for obtaining cached data can be shortened; the data processing time in a calculation process can be shortened; and the program throughput can be increased. According to the method for reading the data by utilizing the multilevel cache, the multilevel cache comprises N cache regions; the N cache regions have different priorities; and N is an integer greater than 1. The method is characterized by comprising the steps of trying to read required data from the N cache regions according to a sequence of priorities from high to low; and when the data is successfully read in one cache region, returning the data and synchronously caching the data to the cache regions with the priorities higher than the priority of the cache region in which the data is read.

The invention discloses a rapid large-scale point-cloud data reading method based on memory pre-distribution and multi-point writing technology, belongs to the technical field of point-cloud data file reading, and aims to solve the problems that reading time of an existing high and large-scale point-cloud data file is delayed and the existing high and large-scale point-cloud data file is slowly red. The method includes a memory pre-distribution process and a multi-point writing process and includes the steps: firstly, determining the number of points in a point-cloud data file, determining the memory size occupied by all points in the point-cloud data file and pre-distributing memories with the corresponding sizes for point-cloud data; secondly, mapping the point-cloud data file to a mapped memory through a memory mapping file mechanism, then building a thread pool containing a designated number of threads, enabling each thread to be responsible for analyzing parts of point-cloud data information in the mapped memory, and writing analyzed results into the pre-distributed memories to realize multi-point writing. Test results indicate that by the aid of the reading method based on the memory pre-distribution and multi-point writing technology, the reading speed of the point-cloud data file and particularly the large-scale point-cloud data file is increased by 220%-300%.

An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines, splits the circuit into portions which can benefit from having differing threshold levels, and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor. The structure is particularly well suited for forming transistors in a combination of NMOS and PMOS, or solely in NMOS. Memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated.

Adaptive Control Driven System/ACDS 99, supports visual enhancement, mitigation of challenges and with basic image modification algorithms: and any known hardware from contact lenses to IOLs to AR hardware glasses, and enables users to enhance vision with user interface based on a series of adjustments that are applied to move, modify, or reshape image sets and components with full advantage of the remaining useful retinal area, thus addressing aspects of visual challenges heretofore inaccessible by devices which learn needed adjustments.

The invention provides a semi-floating gate transistor of a drain region embedding inversion layer and a manufacturing method thereof. The transistor comprises a semiconductor substrate, a plane channel area, a source region, a drain region, a first insulating layer, a floating gate, a diffusion region, a second insulating layer, a control gate and a metal line, wherein the plane channel area is located in an active region of the semiconductor substrate; the source region and the drain region are located on two sides of the plane channel area respectively; the first insulating layer containing a floating gate opening is arranged on a surface of the drain region; the floating gate covers the floating gate opening and the first insulating layer; the diffusion region is arranged in the drain region below the floating gate opening; the second insulating layer covers the whole floating gate, parts of the source region, a rain region surface and the whole plane channel area; the control gate is located above the second insulating layer; the metal line is used to realize leading out of a transistor gate, a source electrode, a drain electrode and the substrate. The transistor is characterized in that a drain region embedding inversion layer which tunnels between a transistor channel region and a heavy doping drain region is embedded below the control gate in the drain region. In the invention, through adding the embedding inversion layer, doping concentration gradient distribution between an embedded tunneling lattice pipe channel and the drain region is optimized; an incidence rate of band-to-band tunneling is increased; a reading and writing speed of the semi-floating gate transistor is improved and electric leakage of the transistor is reduced.

The invention discloses a server parameter deploying method with no need for restarting. The server parameter deploying method comprises: step 100, a storage space is allocated in a server, and server parameters are written into the storage space; step 110, the server parameters are loaded into a server internal memory when a server is started; step 120, the storage space is accessed to re-deploy the server parameters. Compared with the prior art, the reading speed of the server parameter deploying method and device with no need for restarting through xml is high, server restating is not needed. When assignment operation of related static variables or key/value pairs is finished, the server parameters are also updated and re-deployed.

The invention relates to a caching method for a distributed storage system. The method includes the following steps: 1) a client side uploads a file to a server side, wherein 1a) at first, metadata and data blocks of the file are written in the distributed storage system; and 1b) then the metadata of the file are written in a Memcache of a distributed cache system; 2) the client side reads the file from the server side, wherein 2a) whether the metadata are found or not in the Memcache is judged, if the metadata are found in the Memcache, the metadata in the Memcache are sent back to the client side, and otherwise a step 2b) is executed; 2b) the found metadata are written in the Memcache again through the distributed storage system at first; and 2c) the metadata and data blocks of the file are combined through the distributed storage system to be sent to the client side. Compared with the prior art, the caching method has the advantages that the response time for browsing operation by the client side is quickened, the access pressure of the distributed systems is relieved, and consistency of access files is improved.

A processor on-chip program code memory that is based on a FLASH framework and a method that realizes the execution of the on-chip code belongs to the chip technical field, which is characterized in that the FLASH is in the form of NAND, and the memory comprises an address mapping unit which is logically arranged between the CPU and the NAND FLASH for the conversion between an indexed address of the NAND FLASH and a linear address. The invention leads the program code to be stored in the NAND FLASH to realize the on-chip execution (XIP) by the address mapping unit, and solves the disadvantages of the prior NOR FLASH such as high cost, large area and small capacity. By taking the NAND FLASH as the memory of the processor, the invention breaks the limitations for capacity, and the small volume is convenient for the packaging and integration with a high speed of erasure and more erasing times.

The invention discloses an FPGA-based image scaling processing method and device. The method comprises: original image data are obtained and the original image data are inputted into an FPGA internal cache at a preset inputting speed; the original image data are read from the internal cache at a reading speed corresponding to the preset inputting speed, interpolation calculation is carried out based on an interpolation algorithm and the read original image data to obtain image interpolation data; and according to the image interpolation data, image data after image scaling are obtained. The original image data are inputted into the FPGA internal cache for caching and thus no external storage device is needed for storage, so that costs can be lowered. Data can be read from the FPGA internal cache instead of being read from any external storage device, so that the data reading speed can be increased and the overall image scaling efficiency can be improved. In addition, the original image data are read from the internal cache at the reading speed corresponding to the preset inputting speed and thus data reading is carried out at a reasonable reading speed, so that the reading speed can be guaranteed and data loss caused by too slow reading speed can be avoided. Therefore, the scaling processing efficiency can be improved.

The invention discloses a multipath temporary speed limit post answering device and a multipath temporary speed limit post answering method. The device comprises a radio frequency control module, a baseband processing module and a main control module, wherein the radio frequency control module is used for receiving speed limit post signals and transmitting radio-frequency carrier signals, and comprises a plurality of antennae and a plurality of radio frequency units; each antenna is respectively connected with a corresponding radio frequency unit; an AD/DA converter and an FPGA multipath processing unit in the baseband processing module are connected through a data bus, and the baseband processing module is a transceiving module by taking digital signals as a core; and the main control module is used for scheduling and controlling the work of the whole system, and comprises a data receiving unit, an alarm unit, a control unit, a storage unit and a main control unit. The device has the function of reading and processing multipath speed limit post data in real time, and solves the problem of speed limit chaos because a common answering device cannot timely process multipath speed limit post data in the speed limit process on the basis of reducing system complexity and cost so as to improve driving safety.

The invention relates to a design method of a medical image cloud storage platform, and relates to a medical image storage technology. In order to solve a problem of how to quickly read small image files from a combined file and a problem that an HDFS is not suitable for storing small medical image files, the invention proposes to combine all image files in a plurality of inspection files into a large file which is close to 128MB, wherein the large file is named as an SData file. Before an inspection file is added to a file container, whether the sum of the current capacity of the file container and the size of the inspection file exceeds a threshold or not is judged, and a new file container will be built if the sum exceeds the threshold. Small file sets are combined into a plurality of SData files and then uploaded to the HDFS, and corresponding SD index files are stored in an index pool. The design method effectively reduces the memory consumption of small medical image files for the NameNode in the HDFS, thereby enabling the HDFS to be suitable for storing the small image files. In addition, an index, pre-fetching and caching mechanism is introduced, so that the reading speed of the files is effectively improved.

The invention aims to solve the problems of unavailable real-time reading of underground working parameters and data by oil field underground testing and adjusting equipment, excessively complex operation, low efficiency and the like, provides a power line carrier communication method for the oil field underground testing and adjusting equipment and aims to transmit the acquired working parameters of a water well and an oil well to the ground in a digital mode through a power line when an underground testing and adjusting instrument runs under the well, control the operation of an underground instrument and meet the requirements of the real-time monitoring, adjustment and control of the working situations of the water well and the oil well in an oil field. The method is characterized in that: power carrier communication technology is combined with frequency shift keying (FSK) modulation and demodulation technology; a high-voltage direct current power line (voltage magnitude is between 90 and 190 V) which connects a ground control instrument with the underground testing and adjusting instrument is taken as a transmission medium; and a double-frequency FSK carrier modulation and demodulation mode for bearing binary 1 and 0 by two frequencies is adopted so as to realize real-time communication between the ground control instrument and the underground testing and adjusting instrument.

The invention discloses a radio frequency identification system based on an open type software radio platform. The radio frequency identification system is composed of an open type physical layer processing module, a background processor and an open type hardware interface module. A base band processing module of the open type physical layer processing module achieves conversion between a base band of a physical layer signal and an intermediate frequency signal. An analog to digital (AD)/ digital to analog (DA) module can achieve high-speed conversion of analog to digital. The background processor achieves configuration and control of the platform, and label information, media access control (MAC) layer information and physical (PHY) layer information are shown through a graphical user interface (GUI). An open type hardware interface achieves transmission of platform data signals and control signals. A low-cost open type platform system capable of configuring a system bottom layer flexibly under different environments is provided for radio frequency identification (RFID).

The application discloses a vertebra identification and naming system, method and device. The method comprises the steps of obtaining a plurality of image sections correlated with a plurality of vertebras; obtaining a classifier, wherein the classifier is used to identify the vertebral foramens of the vertebras; utilizing the classifier to identify at least one vertebral foramen in the plurality of image sections; based on the vertebral foramens, determining the vertebras; naming the plurality of vertebras. The method and the system disclosed by the application can identify and name the vertebras automatically, and the diagnosis efficiency of the doctors is improved.

The invention discloses a unified login system, which relates to the technical field of the Internet, and aims at solving the problems of low project development efficiency and poor security when theprior right management system is applied to project management. The main points of the technical scheme are as follows: the background module configures multiple role information and configures resource permissions for each role; The authority verification module calls the external interface module and provides the corresponding employee id number to the external interface module, and the employeeid number is associated with the corresponding role information; The external interface module reads the corresponding authority data in the database according to the role associated with the employee id number and returns the authority data to the authority verification module. The authority verification module judges the authority of the employee according to the returned authority data, and invokes the external interface module to configure the corresponding resources for the employee. After the project is connected to the unified login system, the operation authority of the project is assigned by the unified login system, which has the advantages of high development efficiency and good security.

The invention provides an adaptive reading optimization method for mass data under cloud storage environment. The method comprises the following steps of: recording the data access log information of a local user program; carrying out statistical analysis on the above log information in fixed time to obtain an incidence relationship among data objects; according to the data access request of the user grogram, obtaining a data object set related to the data object which is accessed at present, and pre-reading the data object set to a local cache; and for the data object access request of the user program, firstly reading the data object access request from the local cache, and if a data object to be accessed is in the absence in the local cache, reading the data object access request from the far-end storage node of a distributed file system. The method also comprises the steps of pre-reading the related data object set to the local cache from the far-end storage node of the distributed file system and updating the local cache. By use of the method, according to a data object access log subjected to statistics and analysis, the incidence relationship of the data object is established, and the incidence data object of the current read data object is pre-read to the local cache to improve data reading speed.

A nonvolatile memory cell array is divided into first and second cell arrays, the page buffer circuit is arranged between the first and second cell arrays, a second latch circuit is arranged by the outside edge section of the first cell array, and the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array. The data writing to the first or second cell array is controlled by transmitting the writing data to the page buffer circuit via the global bit line from the second latch circuit, after the writing data is latched in the second latch circuit. The data reading of outputting the data read from the first or second cell array to the external circuit is controlled by transmitting data to the second latch circuit from the page buffer circuit via the global bit line.