309 results about "Memory mapping" patented technology

The invention discloses an android container rendering optimization method based on cross-domain hard real-time Fen synchronization, which comprises the following steps: by taking a swan-mong system as a host and an android system as a container, creating a hash table, a synchronous thread and a shared memory corresponding to a GPU core when the host is started, acquiring VSync cycle registration callback, transmitting shared memory FD to the container, and finishing shared memory mapping and alignment by the container. Registering a GPU queue to complete callback; when the Android application is started, a container obtains a queue and a physical address of a rendering buffer area, creates a Fen and binds the Fen to the queue, after the queue is submitted, metadata is written into a shared memory to inform a host, after the host receives the metadata, nodes are created and stored in a hash table, and an overtime timer is registered; after the GPU completes the command queue, the container calls back an update state and a verification value to notify the host, and after the host is verified to be valid, the corresponding hash table is updated, the timer is reset, and asynchronous screen loading is triggered; and the host executes buffer area synthesis and submission of the display equipment to finish on-screen, so that the stability of the rendering frame rate is improved, and the reliability of cross-domain synchronization is ensured.

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

The invention discloses a deterministic soft bus communication method for a virtualized industrial control system, and relates to the field of industrial automation. According to the method, a soft bus communication mode is adopted, so that the containers are interacted through the intermediate message bus, and direct connection does not need to be directly established; all data streams are managed by a unified bus, so that the number of connections is reduced; and meanwhile, a shared memory zero copy mechanism is adopted to optimize data transmission, and the data is directly shared between a producer and a consumer by using a shared memory and a direct memory mapping mode, so that unnecessary copy operation is avoided, the overhead of data transmission is reduced, and the communication efficiency is improved. According to the invention, a unified and efficient communication channel can be established among a plurality of industrial edge applications on the edge device, real-time communication among local containers is supported, automatic routing capability of remote communication is realized, and the communication requirements of high concurrency and high real-time performance in a virtualized industrial control system are met.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

The invention relates to the technical field of distributed architectures, and discloses a multi-screen cooperative control method based on an OpenHarmony distributed architecture and an all-in-one machine system.The method comprises the steps that a broadcast frame found by equipment is sent through an OpenHarmony distributed soft bus, security authentication is conducted on a plurality of display terminals responding to the broadcast frame, a virtual bus channel is established, and the virtual bus channel is sent to the display terminals; obtaining a virtual device group; creating a distributed industrial data object on the main control equipment of the virtual equipment group and synchronizing the distributed industrial data object to each slave display terminal to obtain a distributed data model; mapping the anonymous shared memory to an annular buffer area; and writing real-time data acquired by the industrial field equipment into an annular buffer area, and transmitting the real-time data to each slave display terminal of the virtual equipment group, in the method, each display terminal accesses an agent instance of an industrial data object through a distributed data management framework; and the requirements of high reliability, low delay and high consistency on multi-screen cooperative control in an industrial field are met.

The invention provides a memory overflow program exception positioning method and device based on intelligent analysis, and the method comprises the steps: employing a memory mapping tool to detect the use of a memory index, and collecting the distribution information, object reference relation and stack tracking of a memory when the use of the memory is detected to reach a preset threshold value; performing data cleaning, format conversion and feature extraction on the collected memory data, and extracting the creation and destruction time and the occupied memory size of the object; constructing a memory overflow anomaly detection model, inputting the processed data into the memory overflow anomaly detection model, and if memory overflow anomaly is detected, classifying anomaly types; according to a classification result, a source code of the program and environment information during operation, analyzing an object reference chain of the abnormal object, a memory allocation path and corresponding program logic, determining a reason of memory overflow abnormality and a specific code position, and generating an abnormality reason report; and displaying the content to a program development end through a visual interface.

The invention relates to the technical field of signal processing, and discloses a multichannel data acquisition system and method based on an FPGA (Field Programmable Gate Array), an acquisition module drives a global counter by using a global synchronous clock, writes acquired data into an annular buffer area with a physical address and a counter value in a linear mapping relationship, and establishes implicit time index storage. When a trigger event occurs, the system broadcasts the locked global trigger timestamp, and the acquisition module backtracks and reads historical data according to the global trigger timestamp, and packages the historical data into a sparse matrix type data packet in combination with the channel validity mask. And after receiving the data packet, the data processing module directly calculates a memory mapping address by using global time information in the data packet, and writes a data load into a corresponding position of the waveform reconstruction buffer area. According to the method, through strict binding of the physical address and the absolute time, independent time label redundancy is eliminated, high-precision synchronization of distributed multiple channels is ensured, and out-of-order automatic in-situ recombination and efficient waveform reconstruction of data of a receiving end are achieved.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

A memory mapping method includes: obtaining a memory failed row address of a first memory; obtaining, by a matching and searching circuit, an address mapping table, where the address mapping table includes a mapping relationship between the memory failed row address and a memory remapping row address corresponding to the memory failed row address; and when an access target of the first memory is the memory failed row address, obtaining, based on the address mapping table, the memory remapping row address to which the memory failed row address is mapped, where a memory area indicated by the memory remapping row address is in reserved space of the first memory.

The invention relates to a reconfigurable multi-channel polynomial multiplier architecture and an implementation method thereof, and belongs to the technical field of post-quantum cryptography hardware acceleration. The architecture comprises a scheduler, a twiddle factor memory bank, a bank address routing module, a bank array and a reconfigurable butterfly unit array. According to the architecture, a cyclic decoupling multi-channel NTT / INTT / PWM algorithm is used, flexible configuration of the degree of parallelism and the flow line depth can be supported, and the adaptability of a memory access control strategy is improved; a conflict-free memory mapping scheme based on interleaved storage is adopted, so that storage and read-write of polynomial coefficients are irrelevant to polynomial length and a calculation stage, NTT / INTT / PWM access modes are unified, and hardware resource overhead is greatly reduced; and a conflict-free detection algorithm oriented to multi-channel assembly line design is adopted, so that the utilization rate of hardware resources is remarkably improved.

The invention provides a data transmission method and a data receiving method, which can be applied to the technical field of servers. The data transmission method comprises the following steps: in response to a received asynchronous interrupt signal sent by a basic input / output system, analyzing an asynchronous request frame from a shared memory which is commonly accessed by the basic input / output system and a management controller through a memory mapping management controller interface; according to a data request type indicated by the asynchronous request frame, accessing a preset cache partition in a management controller to obtain target data; wherein historical data transmitted in the data interaction process through the memory mapping management controller interface is stored in the preset cache partition; and writing the target data into the shared memory through the memory mapping management controller interface, and triggering a response event through the interrupt controller, so that the basic input / output system reads the target data by querying the response event under the condition that a preset triggering condition is met.

The invention discloses an audio test data processing method, system and device based on zero-copy NIO and a dynamic sliding window, and the method comprises the following steps: S1, building a memory mapping file channel, and directly mapping an audio file to a process address space; s2, constructing a double-buffer processing pipeline, and realizing asynchronous decoupling of a collection thread and a calculation thread by adopting a producer-consumer mode; and S3, a dynamic sliding window mechanism is adopted to maintain a real-time audio data interval, and the window size is dynamically adjusted according to a television CPU load. According to the technical scheme of the invention, the problems of high memory occupation, high detection delay and low cross-application data reading efficiency existing in audio testing of a television system in a multi-application concurrent scene are solved.

The embodiment of the invention provides a page popularity evaluation method and device, a storage medium and electronic equipment, and relates to the field of computers.The method comprises the steps that cache layer access information of a virtual machine is obtained, and the cache layer access information is used for indicating page access information of a cache of the virtual machine; physical page access information of the virtual machine is obtained based on memory mapping information of the virtual machine, the physical page access information is used for indicating page access information of a physical memory corresponding to the virtual machine, and the memory mapping information is used for indicating a mapping relation between the virtual machine and the physical memory; based on the physical page access information and the cache layer access information, determining comprehensive popularity characteristics of the page of the virtual machine; and determining an access popularity state of the page according to the comprehensive popularity feature.

The invention relates to a protocol calculation optimization method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps that address mapping processing is conducted on a target register, memory mapping addresses corresponding to all threads in the target register are determined, a target initialization value is determined according to the operation type of protocol calculation, then data stored in the memory mapping addresses corresponding to all the threads are initialized into the target initialization value, protocol calculation is executed, and the target initialization value is stored in the memory mapping addresses corresponding to all the threads. And obtaining a protocol calculation result. By adopting the method, the calculation efficiency of protocol calculation can be improved.

The invention provides a method for realizing multi-CPU (central processing unit) architecture large cluster simulation and pressure testing, which belongs to the technical field of cloud containers, and comprises the following steps: (1) directly agenting apisever through an ipvs (internet protocol version) mode; (2) averagely distributing pods of the kubemark to different agents to share pressure; and (3) the reading and writing speed is increased through an etcd memory mapping mode. By means of the method, simulation and pressure testing of a large cluster can be smoothly achieved.

The invention discloses a big language model dialogue system for Token-level resident memory and a use method. The big language model dialogue system comprises an inference engine module, a big language model module, an independent memory model module and an external storage module, relates to the technical field of big language model memory enhancement, after a current dialogue Token sequence is received, whether historical dialogue information is needed or not is judged through a big language model module, and if yes, the historical dialogue information is called from an external storage module through an independent memory model module, so that information displayed by finally responding to the Token sequence is more complete, and user experience is improved. The problems that a model cannot completely retain and utilize long-distance historical information, so that questions cannot be answered and information is forgotten are solved; an external storage module is arranged, and model parameters of an independent memory model module and Token-level data of all historical conversations are resided through a memory mapping technology; and zero occupation of the GPU video memory is realized.

The invention provides a Gaussian data tree index construction method and device supporting incremental updating and a rendering method.The Gaussian data tree index construction method comprises the steps that firstly, normalization processing and integer format conversion are conducted on original Gaussian data, spatial index key values are generated based on coordinates of an integer format, and the spatial index key values serve as coded values corresponding to the original Gaussian data; segmenting the original Gaussian data into a plurality of data blocks according to the coded values; then constructing a local octree; then, generating a global octree; a storage offset is distributed to each node of the global octree, and a byte range corresponding to each node is determined based on the storage offset; each data block stores the original Gaussian data according to the corresponding storage offset and the sequence of the coded values. The subsequent query efficiency can be improved by storing the data blocks according to the coded value sequence, meanwhile, the memory mapping technology is adopted to process the oversized node data so as to reduce IO overhead, and the storage layout and the output mode effectively improve the data writing efficiency and the subsequent reading performance.

The present application relates to the technical field of memory management, and discloses a memory allocation method, a computer device, a storage medium, and a product. The method comprises: defining a special application program interface (API) for allocating a compute express link (CXL) memory; acquiring an invocation request for invoking an API; when the invocation request is used for invoking the special API, generating a CXL memory identifier representing allocation of the CXL memory; and by means of a memory mapping interface, transmitting the CXL memory identifier to a kernel mode, and allocating in the kernel mode a hardware resource related to the CXL memory. According to the present application, a special API for allocating a CXL memory is defined, and a user invokes the special API to implement allocation of the CXL memory, such that the CXL memory can be stably used; and when the user needs to allocate the CXL memory, it is only necessary to modify the invoked API, and the amount of code modification is small, thereby reducing labor costs caused by code modification.

The invention discloses an inter-host process migration method and system, computer equipment and a medium. The inter-host process migration method comprises the steps of obtaining a memory snapshot, file descriptor information, network state information and register state information of a target process in a source host; determining memory mapping information based on the memory snapshot; sending the memory mapping information, the file descriptor information, the network state information and the register state information to a target host; and performing target process reconstruction in the target host by utilizing the memory mapping information, the file descriptor information, the network state information and the register state information. According to the scheme provided by the invention, the memory copying and recovery of the running process can be realized, the resource continuity and the migration reliability are ensured by combining the file descriptor information, the network state information and the register state information, and the method is suitable for dynamic load balancing and fault recovery scenes in cloud computing and distributed systems.

The invention provides a rock-soil acoustic emission signal monitoring system and method, and belongs to the technical field of rock-soil monitoring, in the scheme, an acoustic emission probe is in contact with rock-soil to monitor fracture sound waves in real time and transmit the fracture sound waves to a signal processing module, and the signal processing module filters acoustic emission signals and then transmits the acoustic emission signals to an upper computer; the upper computer extracts rock-soil fracture acoustic emission signal features and displays the rock-soil fracture acoustic emission signal features; the upper computer circularly receives the data uploaded by the FPGA acquisition card and directly accesses the uploaded data through memory mapping; setting multiple threads for concurrently processing acoustic emission signal data, adopting a lock-free queue for communication among the threads, and triggering the queue by using semaphore; and after the thread queue reaches a triggering condition, storing the acoustic emission signal and displaying a pulse waveform. The method has the beneficial effects that the problems of poor real-time performance and high false alarm rate in the rock-soil fracture acoustic emission monitoring process are solved, and the situation of missed alarm due to hardware communication delay is avoided.

The invention relates to the technical field of photovoltaic power generation system control, and provides an MPPT control method and system based on an adaptive fuzzy neural network, and the method comprises the steps: synchronously collecting voltage, current, illumination and temperature signals, and generating original sensing data; transmitting the generated original sensing data to a memory mapping area through a hardware channel; sensing data is obtained from the memory mapping area, calculation is executed, a power variation and an illumination variation are predicted, a fuzzy reasoning algorithm is operated based on the power variation and the illumination variation, and a power point decision scheme is obtained; a fuzzy rule is updated based on the predicted power variation and illumination variation, the updated fuzzy rule is fed back to the dual-core heterogeneous processor in real time, and fuzzy reasoning logic is optimized; and driving the four-phase interlaced power topological structure to work in an interlaced manner according to the power point decision scheme so as to realize maximum power point tracking. According to the invention, rapid tracking and high-precision stable control of the maximum power point of the photovoltaic array in a complex environment can be realized.

The invention provides a data management system and method for a multi-modal robot cluster, a medium, a terminal and a program product. The system comprises a data container module, a data storage module and a data management module, wherein the data container module is used for segmenting each bag file into a plurality of theme files and index files; the I / O transponder module is used for responding to a write-in operation request, respectively writing input multi-modal data into corresponding theme files according to theme types, and adding index entries generated based on a hot update mechanism into index files; and / or, in response to a read operation request, retrieving a time sequence index mapped by the memory, and forwarding the offset parameter to each theme file to read message data; the theme management module is used for creating a hash table; and the time sequence index caching module is used for caching the updated index file and refreshing the cached index file back to the storage device. According to the method, the requirement of efficient real-time data exchange of the multi-modal robot cluster can be met, and the data read-write efficiency is improved.

The invention discloses a server BIOS log transmission method based on function decoupling, and the method comprises the steps: a processor obtains to-be-transmitted log data and corresponding log attributes, determines the log type of the log data based on the log attributes, calls a specified real-time clock, determines the generation timestamp of the log data, and transmits the log data to a server; sending the log data to a baseboard management controller to enable the log data to carry a generation timestamp, calling a log transmission path corresponding to the log type, and sending the log data to the baseboard management controller; the baseboard management controller sorts the high-level logs and the basic logs according to the sequence of the generated timestamps from morning to evening to obtain a global log queue; mapping the log data in the global log queue into a memory through memory mapping, and backing up the log data to a flash memory; and outputting the basic logs in the global log queue to a network console according to the sequence from front to back. According to the method, the conflict between high throughput and starting timeliness in the log transmission process can be effectively solved.

To provide an information processing device that enables overlapping of communication and calculation without buffering the communication between calculation processes on a host.SOLUTION: In an information processing device, a coprocessor-host memory translation function maps a calculation process virtual memory for a calculation process in a coprocessor provided in the information processing device to an offloading function virtual address for collective communication offloading. The collective communication offloading function uses the mapped offloading function virtual address to perform remote direct memory access (RDMA) for another information processing device connected via a network, and implements communication between the calculation process and a calculation process of the other information processing device.SELECTED DRAWING: Figure 1

A memory management method and module, a chip, an electronic device, and a storage medium. The memory management method comprises: scanning memory pages to which virtual addresses of a discontinuous memory mapping space are mapped to acquire a compressible memory page as a first memory page; compressing memory data in the first memory page to acquire corresponding memory compressed data; storing the memory compressed data in a data storage module, the data storage module being located in memory space outside the discontinuous memory mapping space; after storing the memory compressed data in the data storage module, releasing the first memory page; and setting the corresponding virtual address as a page fault address. The memory utilization is improved.

The invention discloses a simulation method, system and device of an automobile thermal management system and a storage medium. In the scheme, a one-dimensional system simulation model of a target automobile thermal management system and a three-dimensional flow field simulation model of a target component are constructed. Running the one-dimensional model to obtain system-level parameters, writing the system-level parameters into the memory mapping file and generating a first flag file; after the first flag file is detected, the three-dimensional model runs based on the system-level parameters to obtain the flow field parameters, the flow field parameters are written into the memory mapping file, and a second flag file is generated. And after the second flag file is detected, the one-dimensional model obtains corrected system-level parameters based on the flow field parameters, the corrected system-level parameters are written into the memory mapping file, the first flag file is regenerated, and the steps are repeated. Real-time interaction of the parameters is realized through the memory mapping file, a closed-loop circulation mechanism is formed by means of the mark file, efficient, ordered and synchronous data interaction is ensured, instantaneous change of the system parameters can be captured in real time, and the accuracy and reliability of simulation of the automobile thermal management system are further improved.

The invention provides a soft board card servo motion control and data interaction system based on an OPCUA. Comprising a server connection module used for selecting an OPCUA according to a server address, establishing a client session and outputting a session handle; the variable analysis module is used for generating an analysis rule from a logic variable name to an OPCUA node identifier and outputting variable metadata; the memory mapping module is used for creating subscriptions in batches under a session handle, binding data change callback and writing change of server variables into a local data storage area; the control module is used for providing a data read-write interface and a shaft control interface for an upper computer; and determining an instruction state based on the completion mark, the error code and the busy mark, and providing the instruction state and the shaft state quantity as readable variables to the data read-write interface. According to the application, the unification of variable analysis and OPCUA node addressing, subscription-driven local data mirroring and low-delay read-write, axis control parameterization execution closed loop and unified state judgment based on completion / error / busy can be realized.

An apparatus for executing a software program, comprising: a processing unit; at least one memory component, each memory component connected to the processing unit and mapped to a memory address range of the processing unit; a memory mapping circuit connected to the processing unit and the memory component and configured to: in each of a plurality of iterations: access a statistical counter collected while the processing unit executes the software program; in a case where a first range and a second range are identified according to an analysis of the statistical counter, generate a mapping between the first memory address range and the second memory address range; in response to a memory access command including a first memory address within the first range received from the processing unit, replace the first memory address in the memory access command with a second memory address within the second range according to the mapping.