381 results about "Memory mapping" patented technology

The invention discloses a real-time interactive digital human system supporting high concurrency and an implementation method thereof, and relates to the technical field of digital human interaction.The system comprises a model instance pool module used for loading the weight of a deep learning model to a shared memory area through the memory mapping technology; the multi-thread scheduling module is used for scheduling user requests by adopting a lock-free queue and a dynamic priority algorithm; the asynchronous pipeline processing module is composed of decoupled micro-services, and the modules are connected in series through asynchronous message queues; the client SDK is used for dynamically switching a rendering mode according to terminal hardware performance and network conditions; the elastic capacity expansion and contraction module is used for monitoring resource loads in real time and automatically adjusting the number of service instances; and the audio and video synchronization calibration module is used for ensuring that the synchronization error of the audio and video frames is lower than a preset threshold value through a timestamp alignment algorithm. According to the scheme, core challenges in a high-concurrency digital human interaction scene can be systematically solved, and innovative support is provided for large-scale real-time application.

The invention discloses an android container rendering optimization method based on cross-domain hard real-time Fen synchronization, which comprises the following steps: by taking a swan-mong system as a host and an android system as a container, creating a hash table, a synchronous thread and a shared memory corresponding to a GPU core when the host is started, acquiring VSync cycle registration callback, transmitting shared memory FD to the container, and finishing shared memory mapping and alignment by the container. Registering a GPU queue to complete callback; when the Android application is started, a container obtains a queue and a physical address of a rendering buffer area, creates a Fen and binds the Fen to the queue, after the queue is submitted, metadata is written into a shared memory to inform a host, after the host receives the metadata, nodes are created and stored in a hash table, and an overtime timer is registered; after the GPU completes the command queue, the container calls back an update state and a verification value to notify the host, and after the host is verified to be valid, the corresponding hash table is updated, the timer is reset, and asynchronous screen loading is triggered; and the host executes buffer area synthesis and submission of the display equipment to finish on-screen, so that the stability of the rendering frame rate is improved, and the reliability of cross-domain synchronization is ensured.

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

The invention discloses a cross-host memory sharing method, system and device and a medium, the memory sharing system comprises a master node and a plurality of slave nodes, the memory sharing method is applied to the master node, and the method comprises the steps that a memory application request of a target slave node is received; applying for a target memory in a target memory sharing area according to a memory size requirement corresponding to the request, feeding back memory information of the target memory to a target slave node, so that the target slave node judges a corresponding memory type according to the memory information, and if a process corresponding to the target slave node executes a memory mapping method, sending the target memory to the target slave node. If yes, the target memory can be mapped to the proceeding virtual address space according to the target type and the offset corresponding to the target memory, so that the process can use the distributed target memory. Therefore, it can be guaranteed that when one node writes the memory, other nodes cannot synchronously write the memory, and then the data consistency of the shared memory accessed by multiple hosts is guaranteed.

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

A firmware management operation. The firmware management operation includes providing an information handling system with a distributed BIOS, the distributed BIOS including a BIOS component and a BIOS variable; identifying a processor environment installed on an information handling system from a plurality of processor environments; performing a unified BIOS memory mapping operation, the unified BIOS memory mapping operation managing mapping firmware interrupts based upon the processor environment installed on the information handling system.

The invention discloses a deterministic soft bus communication method for a virtualized industrial control system, and relates to the field of industrial automation. According to the method, a soft bus communication mode is adopted, so that the containers are interacted through the intermediate message bus, and direct connection does not need to be directly established; all data streams are managed by a unified bus, so that the number of connections is reduced; and meanwhile, a shared memory zero copy mechanism is adopted to optimize data transmission, and the data is directly shared between a producer and a consumer by using a shared memory and a direct memory mapping mode, so that unnecessary copy operation is avoided, the overhead of data transmission is reduced, and the communication efficiency is improved. According to the invention, a unified and efficient communication channel can be established among a plurality of industrial edge applications on the edge device, real-time communication among local containers is supported, automatic routing capability of remote communication is realized, and the communication requirements of high concurrency and high real-time performance in a virtualized industrial control system are met.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

The invention discloses a data transmission system, method and device, a storage medium and a computer program product, and relates to the technical field of communication. The data transmission system comprises a virtual machine, a virtual RDMA device and a host, wherein the virtual RDMA device runs between the virtual machine and the host. Wherein the virtual machine is used for running an application; the virtual RDMA equipment is used for registering a virtual memory and a virtual RDMA connection corresponding to the virtual machine, configuring a memory mapping relation between the virtual memory and a physical memory and a connection mapping relation between the virtual RDMA connection and the physical RDMA connection, and issuing the memory mapping relation and the connection mapping relation to the host; and the host is used for transmitting the RDMA data of the application according to the memory mapping relation and the connection mapping relation. Decoupling of the front-end virtual machine and the rear-end host is realized, the expansibility of connection is improved, a data transmission system is more modularized and is easy to manage, and the overhead of the host is reduced.

The invention relates to an online action detection method based on multi-stage memory mapping. The method comprises the following specific steps: S1, feature extraction: extracting frame-level features from a video stream by using a pre-training model; s2, memory division: dividing the extracted features into long-term memory and short-term memory according to time; s3, multi-stage mapping memory encoding: adopting a multi-stage mapping encoder for long-term memory, including segmented compression and global compression branches, compressing and extracting key information, and inhibiting irrelevant backgrounds; s4, cyclic decoding and updating: dynamically updating the short-term memory by adopting a cyclic decoder, and generating pre-judgment information of future actions; s5, model training and optimization: improving a loss function through design, optimizing the fusion effect of local features and global dependence in the model, and improving the overall detection performance; and S6, on-line action detection: detecting actions in real time based on the memory features updated by cyclic decoding, and evaluating performance according to actual action labels. According to the invention, the accuracy and robustness of action detection are improved.

The invention relates to the technical field of distributed architectures, and discloses a multi-screen cooperative control method based on an OpenHarmony distributed architecture and an all-in-one machine system.The method comprises the steps that a broadcast frame found by equipment is sent through an OpenHarmony distributed soft bus, security authentication is conducted on a plurality of display terminals responding to the broadcast frame, a virtual bus channel is established, and the virtual bus channel is sent to the display terminals; obtaining a virtual device group; creating a distributed industrial data object on the main control equipment of the virtual equipment group and synchronizing the distributed industrial data object to each slave display terminal to obtain a distributed data model; mapping the anonymous shared memory to an annular buffer area; and writing real-time data acquired by the industrial field equipment into an annular buffer area, and transmitting the real-time data to each slave display terminal of the virtual equipment group, in the method, each display terminal accesses an agent instance of an industrial data object through a distributed data management framework; and the requirements of high reliability, low delay and high consistency on multi-screen cooperative control in an industrial field are met.

The invention provides a memory overflow program exception positioning method and device based on intelligent analysis, and the method comprises the steps: employing a memory mapping tool to detect the use of a memory index, and collecting the distribution information, object reference relation and stack tracking of a memory when the use of the memory is detected to reach a preset threshold value; performing data cleaning, format conversion and feature extraction on the collected memory data, and extracting the creation and destruction time and the occupied memory size of the object; constructing a memory overflow anomaly detection model, inputting the processed data into the memory overflow anomaly detection model, and if memory overflow anomaly is detected, classifying anomaly types; according to a classification result, a source code of the program and environment information during operation, analyzing an object reference chain of the abnormal object, a memory allocation path and corresponding program logic, determining a reason of memory overflow abnormality and a specific code position, and generating an abnormality reason report; and displaying the content to a program development end through a visual interface.

The present application is applied to the technical field of data interaction. Provided are a data interaction method, a computer system, an electronic device, and a non-volatile computer-readable storage medium. The method may comprise: determining a first data packet to be sent to a baseboard management controller, and segmenting the first data packet into a plurality of data blocks of a target size; determining repeated string sequences in the plurality of data blocks, and determining position information of the repeated string sequences in the first data packet; on the basis of non-repeated string sequences and the repeated string sequences in the plurality of data blocks, and the position information, generating a second data packet; and sending the second data packet to the baseboard management controller by means of a memory-mapped baseboard management controller interface. The volume of data transmitted between a basic input / output system and a baseboard management controller can be significantly reduced, thereby improving the efficiency of data transmission, and thus avoiding excessive bandwidth occupation by data transmission and also improving the use efficiency of circular buffers.

The invention relates to the technical field of signal processing, and discloses a multichannel data acquisition system and method based on an FPGA (Field Programmable Gate Array), an acquisition module drives a global counter by using a global synchronous clock, writes acquired data into an annular buffer area with a physical address and a counter value in a linear mapping relationship, and establishes implicit time index storage. When a trigger event occurs, the system broadcasts the locked global trigger timestamp, and the acquisition module backtracks and reads historical data according to the global trigger timestamp, and packages the historical data into a sparse matrix type data packet in combination with the channel validity mask. And after receiving the data packet, the data processing module directly calculates a memory mapping address by using global time information in the data packet, and writes a data load into a corresponding position of the waveform reconstruction buffer area. According to the method, through strict binding of the physical address and the absolute time, independent time label redundancy is eliminated, high-precision synchronization of distributed multiple channels is ensured, and out-of-order automatic in-situ recombination and efficient waveform reconstruction of data of a receiving end are achieved.

A mixture-of-experts artificial intelligence model according to the present invention comprises: a CXL control unit that manages a CXL protocol; an NDP control unit that includes a memory mapping register set for communicating with a host; a memory unit composed of a plurality of memory chips that provide a memory capacity to the host; and an NDP core unit that processes MoEs existing in the memory unit, wherein the NDP core unit transmits only hot experts to a GPU accelerator while memory-based calculation is performed on cold experts that exist in the memory unit.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

The invention discloses a memory performance detection method, device and equipment and a memory medium, and relates to the technical field of memory performance detection. Memory with the same capacity of a data path port of a memory box is mapped to an endpoint port, the mapped memory is converted into an extended memory which can be identified by a host node, and then the memory performance of the extended memory is subjected to a consistency test, so that a memory mapping relationship can be quickly and effectively established; according to the embodiment of the invention, the host nodes can schedule the memory capacity required by the host nodes in the memory box, and the inconsistency caused by different mapped memory spaces is eliminated by configuring extended memories with the same capacity for the host nodes, so that the memory performance of the plurality of host nodes tends to be consistent on the premise, and the effectiveness of the consistency test is improved.

A memory mapping method includes: obtaining a memory failed row address of a first memory; obtaining, by a matching and searching circuit, an address mapping table, where the address mapping table includes a mapping relationship between the memory failed row address and a memory remapping row address corresponding to the memory failed row address; and when an access target of the first memory is the memory failed row address, obtaining, based on the address mapping table, the memory remapping row address to which the memory failed row address is mapped, where a memory area indicated by the memory remapping row address is in reserved space of the first memory.

The invention relates to a reconfigurable multi-channel polynomial multiplier architecture and an implementation method thereof, and belongs to the technical field of post-quantum cryptography hardware acceleration. The architecture comprises a scheduler, a twiddle factor memory bank, a bank address routing module, a bank array and a reconfigurable butterfly unit array. According to the architecture, a cyclic decoupling multi-channel NTT / INTT / PWM algorithm is used, flexible configuration of the degree of parallelism and the flow line depth can be supported, and the adaptability of a memory access control strategy is improved; a conflict-free memory mapping scheme based on interleaved storage is adopted, so that storage and read-write of polynomial coefficients are irrelevant to polynomial length and a calculation stage, NTT / INTT / PWM access modes are unified, and hardware resource overhead is greatly reduced; and a conflict-free detection algorithm oriented to multi-channel assembly line design is adopted, so that the utilization rate of hardware resources is remarkably improved.

The invention discloses a method for communication between jailhome partitions. The method comprises the following steps: configuring a jailhome cell configuration file according to hardware platform resources and task requirements in a cell; compiling and operating jailhouse, starting an inmate cell, and completing registration of a destination port and a source port and memory mapping of an FIFO annular buffer area; sending data to the virtual PCI device through a source port, filling in a Doorbell register after data sending is completed, and sending an interrupt signal to a destination port through a Hypervisor; reading data from the virtual PCI device through the destination port; and after the application program of the destination port receives the data, executing the predefined task. According to the method, the controllability, verifiability and adaptation flexibility of communication behaviors are enhanced, and the method is suitable for safety key scenes with strict requirements for high-frequency, small-data-volume, low-delay and deterministic communication.

The invention provides a data transmission method and a data receiving method, which can be applied to the technical field of servers. The data transmission method comprises the following steps: in response to a received asynchronous interrupt signal sent by a basic input / output system, analyzing an asynchronous request frame from a shared memory which is commonly accessed by the basic input / output system and a management controller through a memory mapping management controller interface; according to a data request type indicated by the asynchronous request frame, accessing a preset cache partition in a management controller to obtain target data; wherein historical data transmitted in the data interaction process through the memory mapping management controller interface is stored in the preset cache partition; and writing the target data into the shared memory through the memory mapping management controller interface, and triggering a response event through the interrupt controller, so that the basic input / output system reads the target data by querying the response event under the condition that a preset triggering condition is met.

The invention discloses an audio test data processing method, system and device based on zero-copy NIO and a dynamic sliding window, and the method comprises the following steps: S1, building a memory mapping file channel, and directly mapping an audio file to a process address space; s2, constructing a double-buffer processing pipeline, and realizing asynchronous decoupling of a collection thread and a calculation thread by adopting a producer-consumer mode; and S3, a dynamic sliding window mechanism is adopted to maintain a real-time audio data interval, and the window size is dynamically adjusted according to a television CPU load. According to the technical scheme of the invention, the problems of high memory occupation, high detection delay and low cross-application data reading efficiency existing in audio testing of a television system in a multi-application concurrent scene are solved.

The embodiment of the invention provides a system-on-chip bus verification method and device and electronic equipment, and relates to the technical field of chips. The method comprises the steps of obtaining a source memory mapping configuration file in a preset format, performing format conversion to obtain a target memory mapping configuration file which comprises a class method of an access address of a slave device, determining a device combination, obtaining access related information by calling the class method of the slave device in the device combination, and generating a corresponding verification case, and performing verification. A source memory mapping configuration file is converted into a target memory mapping configuration file in a System Verilog language format with a clear code structure, so that when a verification case corresponding to a master device combination needs to be generated, the verification case corresponding to the master device combination is generated by calling a class method of an access address of each slave device corresponding to the combination in the target memory mapping configuration file; therefore, the access related information of each slave device required for generating the verification case can be obtained, so that the generation efficiency of the verification case is effectively improved.

The embodiment of the invention provides a page popularity evaluation method and device, a storage medium and electronic equipment, and relates to the field of computers.The method comprises the steps that cache layer access information of a virtual machine is obtained, and the cache layer access information is used for indicating page access information of a cache of the virtual machine; physical page access information of the virtual machine is obtained based on memory mapping information of the virtual machine, the physical page access information is used for indicating page access information of a physical memory corresponding to the virtual machine, and the memory mapping information is used for indicating a mapping relation between the virtual machine and the physical memory; based on the physical page access information and the cache layer access information, determining comprehensive popularity characteristics of the page of the virtual machine; and determining an access popularity state of the page according to the comprehensive popularity feature.

The invention relates to a protocol calculation optimization method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps that address mapping processing is conducted on a target register, memory mapping addresses corresponding to all threads in the target register are determined, a target initialization value is determined according to the operation type of protocol calculation, then data stored in the memory mapping addresses corresponding to all the threads are initialized into the target initialization value, protocol calculation is executed, and the target initialization value is stored in the memory mapping addresses corresponding to all the threads. And obtaining a protocol calculation result. By adopting the method, the calculation efficiency of protocol calculation can be improved.

The invention provides a method for realizing multi-CPU (central processing unit) architecture large cluster simulation and pressure testing, which belongs to the technical field of cloud containers, and comprises the following steps: (1) directly agenting apisever through an ipvs (internet protocol version) mode; (2) averagely distributing pods of the kubemark to different agents to share pressure; and (3) the reading and writing speed is increased through an etcd memory mapping mode. By means of the method, simulation and pressure testing of a large cluster can be smoothly achieved.

The invention discloses a big language model dialogue system for Token-level resident memory and a use method. The big language model dialogue system comprises an inference engine module, a big language model module, an independent memory model module and an external storage module, relates to the technical field of big language model memory enhancement, after a current dialogue Token sequence is received, whether historical dialogue information is needed or not is judged through a big language model module, and if yes, the historical dialogue information is called from an external storage module through an independent memory model module, so that information displayed by finally responding to the Token sequence is more complete, and user experience is improved. The problems that a model cannot completely retain and utilize long-distance historical information, so that questions cannot be answered and information is forgotten are solved; an external storage module is arranged, and model parameters of an independent memory model module and Token-level data of all historical conversations are resided through a memory mapping technology; and zero occupation of the GPU video memory is realized.

The invention provides a Gaussian data tree index construction method and device supporting incremental updating and a rendering method.The Gaussian data tree index construction method comprises the steps that firstly, normalization processing and integer format conversion are conducted on original Gaussian data, spatial index key values are generated based on coordinates of an integer format, and the spatial index key values serve as coded values corresponding to the original Gaussian data; segmenting the original Gaussian data into a plurality of data blocks according to the coded values; then constructing a local octree; then, generating a global octree; a storage offset is distributed to each node of the global octree, and a byte range corresponding to each node is determined based on the storage offset; each data block stores the original Gaussian data according to the corresponding storage offset and the sequence of the coded values. The subsequent query efficiency can be improved by storing the data blocks according to the coded value sequence, meanwhile, the memory mapping technology is adopted to process the oversized node data so as to reduce IO overhead, and the storage layout and the output mode effectively improve the data writing efficiency and the subsequent reading performance.