204 results about "Memory mapping" patented technology

The invention discloses an android container rendering optimization method based on cross-domain hard real-time Fen synchronization, which comprises the following steps: by taking a swan-mong system as a host and an android system as a container, creating a hash table, a synchronous thread and a shared memory corresponding to a GPU core when the host is started, acquiring VSync cycle registration callback, transmitting shared memory FD to the container, and finishing shared memory mapping and alignment by the container. Registering a GPU queue to complete callback; when the Android application is started, a container obtains a queue and a physical address of a rendering buffer area, creates a Fen and binds the Fen to the queue, after the queue is submitted, metadata is written into a shared memory to inform a host, after the host receives the metadata, nodes are created and stored in a hash table, and an overtime timer is registered; after the GPU completes the command queue, the container calls back an update state and a verification value to notify the host, and after the host is verified to be valid, the corresponding hash table is updated, the timer is reset, and asynchronous screen loading is triggered; and the host executes buffer area synthesis and submission of the display equipment to finish on-screen, so that the stability of the rendering frame rate is improved, and the reliability of cross-domain synchronization is ensured.

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

The invention relates to the technical field of distributed architectures, and discloses a multi-screen cooperative control method based on an OpenHarmony distributed architecture and an all-in-one machine system.The method comprises the steps that a broadcast frame found by equipment is sent through an OpenHarmony distributed soft bus, security authentication is conducted on a plurality of display terminals responding to the broadcast frame, a virtual bus channel is established, and the virtual bus channel is sent to the display terminals; obtaining a virtual device group; creating a distributed industrial data object on the main control equipment of the virtual equipment group and synchronizing the distributed industrial data object to each slave display terminal to obtain a distributed data model; mapping the anonymous shared memory to an annular buffer area; and writing real-time data acquired by the industrial field equipment into an annular buffer area, and transmitting the real-time data to each slave display terminal of the virtual equipment group, in the method, each display terminal accesses an agent instance of an industrial data object through a distributed data management framework; and the requirements of high reliability, low delay and high consistency on multi-screen cooperative control in an industrial field are met.

The invention relates to the technical field of signal processing, and discloses a multichannel data acquisition system and method based on an FPGA (Field Programmable Gate Array), an acquisition module drives a global counter by using a global synchronous clock, writes acquired data into an annular buffer area with a physical address and a counter value in a linear mapping relationship, and establishes implicit time index storage. When a trigger event occurs, the system broadcasts the locked global trigger timestamp, and the acquisition module backtracks and reads historical data according to the global trigger timestamp, and packages the historical data into a sparse matrix type data packet in combination with the channel validity mask. And after receiving the data packet, the data processing module directly calculates a memory mapping address by using global time information in the data packet, and writes a data load into a corresponding position of the waveform reconstruction buffer area. According to the method, through strict binding of the physical address and the absolute time, independent time label redundancy is eliminated, high-precision synchronization of distributed multiple channels is ensured, and out-of-order automatic in-situ recombination and efficient waveform reconstruction of data of a receiving end are achieved.

The invention relates to a reconfigurable multi-channel polynomial multiplier architecture and an implementation method thereof, and belongs to the technical field of post-quantum cryptography hardware acceleration. The architecture comprises a scheduler, a twiddle factor memory bank, a bank address routing module, a bank array and a reconfigurable butterfly unit array. According to the architecture, a cyclic decoupling multi-channel NTT / INTT / PWM algorithm is used, flexible configuration of the degree of parallelism and the flow line depth can be supported, and the adaptability of a memory access control strategy is improved; a conflict-free memory mapping scheme based on interleaved storage is adopted, so that storage and read-write of polynomial coefficients are irrelevant to polynomial length and a calculation stage, NTT / INTT / PWM access modes are unified, and hardware resource overhead is greatly reduced; and a conflict-free detection algorithm oriented to multi-channel assembly line design is adopted, so that the utilization rate of hardware resources is remarkably improved.

The invention discloses a big language model dialogue system for Token-level resident memory and a use method. The big language model dialogue system comprises an inference engine module, a big language model module, an independent memory model module and an external storage module, relates to the technical field of big language model memory enhancement, after a current dialogue Token sequence is received, whether historical dialogue information is needed or not is judged through a big language model module, and if yes, the historical dialogue information is called from an external storage module through an independent memory model module, so that information displayed by finally responding to the Token sequence is more complete, and user experience is improved. The problems that a model cannot completely retain and utilize long-distance historical information, so that questions cannot be answered and information is forgotten are solved; an external storage module is arranged, and model parameters of an independent memory model module and Token-level data of all historical conversations are resided through a memory mapping technology; and zero occupation of the GPU video memory is realized.

The invention discloses an inter-host process migration method and system, computer equipment and a medium. The inter-host process migration method comprises the steps of obtaining a memory snapshot, file descriptor information, network state information and register state information of a target process in a source host; determining memory mapping information based on the memory snapshot; sending the memory mapping information, the file descriptor information, the network state information and the register state information to a target host; and performing target process reconstruction in the target host by utilizing the memory mapping information, the file descriptor information, the network state information and the register state information. According to the scheme provided by the invention, the memory copying and recovery of the running process can be realized, the resource continuity and the migration reliability are ensured by combining the file descriptor information, the network state information and the register state information, and the method is suitable for dynamic load balancing and fault recovery scenes in cloud computing and distributed systems.

The invention discloses a server BIOS log transmission method based on function decoupling, and the method comprises the steps: a processor obtains to-be-transmitted log data and corresponding log attributes, determines the log type of the log data based on the log attributes, calls a specified real-time clock, determines the generation timestamp of the log data, and transmits the log data to a server; sending the log data to a baseboard management controller to enable the log data to carry a generation timestamp, calling a log transmission path corresponding to the log type, and sending the log data to the baseboard management controller; the baseboard management controller sorts the high-level logs and the basic logs according to the sequence of the generated timestamps from morning to evening to obtain a global log queue; mapping the log data in the global log queue into a memory through memory mapping, and backing up the log data to a flash memory; and outputting the basic logs in the global log queue to a network console according to the sequence from front to back. According to the method, the conflict between high throughput and starting timeliness in the log transmission process can be effectively solved.

A memory management method and module, a chip, an electronic device, and a storage medium. The memory management method comprises: scanning memory pages to which virtual addresses of a discontinuous memory mapping space are mapped to acquire a compressible memory page as a first memory page; compressing memory data in the first memory page to acquire corresponding memory compressed data; storing the memory compressed data in a data storage module, the data storage module being located in memory space outside the discontinuous memory mapping space; after storing the memory compressed data in the data storage module, releasing the first memory page; and setting the corresponding virtual address as a page fault address. The memory utilization is improved.

The invention provides a memory mapping verification method, a management controller, a system and a medium, and relates to the technical field of computers. In the invention, in order to map the memory space of the management controller, a host needs to send an address space remapping request to the management controller, and the request needs to contain information to be verified and address information to be mapped. The management controller can verify the to-be-verified information and the to-be-mapped address information, and only when the to-be-verified information passes verification and a target memory area corresponding to the to-be-mapped address information in a memory of the management controller is located in a preset mappable area, a confirmation response is sent to the host, and the host is allowed to perform address remapping on the target memory area. Therefore, the host can be prevented from randomly accessing any memory area of the management controller, and the security of accessing the memory of the management controller by the host can be improved.

The present disclosure relates to a data processing method, device, system, computer device and storage medium. The method comprises: in the case of listening to an agent process updating a data set file corresponding to a service process, performing in-memory mapping on the updated target data set file to obtain a virtual memory address of the target data set file; releasing data in an original data set file in a physical memory of the service process; and writing data in the target data set file into the physical memory according to the virtual memory address of the target data set file. The embodiment of the present disclosure can reduce memory consumption.

The invention relates to the technical field of dynamic instrumentation, in particular to a method and system for dynamically instrumenting a swan NEXT Native layer function. The method comprises the following steps: obtaining a process identifier of a target application process, and reading a corresponding memory mapping file to obtain a loading base address and a file path of a Native layer ELF shared object; an ELF file corresponding to the file path is read, and an index relation table of the target function symbol name of each item in the PLT section, the PLT item and the file offset of the PLT section is established; adding the loading base address and the file offset of the PLT section to calculate the initial address of the memory of the PLT section; and calculating the memory absolute address of the PLT entry of the target function according to the PLT entry of the to-be-intercepted function in the index relation table. According to the method, the index relationship between the symbol and the address is established by analyzing the memory mapping file and the ELF shared object file of the target process, and accurate function interception is realized at the PLT entry level.

Embodiments described herein may include apparatus, systems, techniques, and / or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers. By using scan-sealing methods and / or preserving the data in host connectivity registers during in-operation testing, performance and user experience are not degraded.

The invention discloses a PLC (Programmable Logic Controller) power failure data retention system based on a Linux memory mapping technology. The PLC power failure data retention system comprises a hardware subsystem and a software subsystem, the hardware subsystem comprises a CPU module for running a real-time Linux operating system; the power failure detection module is used for monitoring the voltage of an external power supply and triggering hardware interruption; the super capacitor power supply module is used for providing backup power after power failure; and the EMMC storage module is used for storing PLC key data. The software subsystem comprises a memory mapping driving module for mapping a physical space of the EMMC storage module to a system space to form a shared memory mapping area; the synchronization guarantee module is used for realizing lock-free synchronous access control by operating a state register; and the power failure control module responds to hardware interruption to start a data synchronization process. According to the system, lock-free synchronous access control between a user mode and a kernel mode is achieved through atomic bit flipping and exclusive-OR logic, it is ensured that a complete data block is synchronized to an EMMC storage module, the reliability problem of power-down data retention of a PLC system is solved, and the data synchronization efficiency and the system stability are improved.

This invention provides a memory management method and apparatus, relating to the field of computer technology. The method includes: receiving a forced memory mapping request for a target virtual address range; locking the target virtual address range; determining a first Virtual Address Management (VMA) for managing overlapping ranges; replacing the determined first VMA with a second VMA; removing a first mapping relationship between the overlapping range and the mapped physical memory region from the page table; if the second VMA is the VMA corresponding to the overlapping range, recording a second mapping relationship between the VMA corresponding to the overlapping range and the new physical memory region indicated by the forced memory mapping request in the page table; if the second VMA is a placeholder VMA, replacing the placeholder VMA with the VMA corresponding to the overlapping range and recording the second mapping relationship in the page table; and unlocking the target virtual address range. Applying the memory management scheme provided in this application can improve the security of the operating system.

Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.

The application discloses a virtual PCI device for multi-domain isolated communication and an implementation method thereof, which comprises the following steps: dividing the memory mapping IO address space of the virtual PCI device into a general configuration space and a private configuration space, storing a first type of register for generally configuring a plurality of data channels in the general configuration space, and storing a second type of register for specially configuring a single data channel in the private configuration space. The protocol limitation of the virtual PCI device can be broken, and a plurality of data channels can be served by one virtual PCI device.

The present disclosure provides a serialization and deserialization method of an FPGA-based IPU acceleration service grid. The serialization and deserialization method of the FPGA-based IPU acceleration service grid comprises: determining all message objects of remote procedure calls to be sent and received; allocating a sending descriptor ring and a receiving descriptor ring and configuring a control register through a memory-mapped I / O operation; defining a message format of a remote procedure call through a domain-specific language for serialization and deserialization; when in a transmission mode, creating a sending descriptor and filling it into the sending descriptor ring; the FPGA obtains the sending descriptor from the sending descriptor ring and sends encoded data to a system-on-chip; and the system-on-chip sends the encoded data through a network transmission protocol. The embodiments of the present disclosure solve the problems of performance bottleneck, high delay and high CPU resource occupation in the prior art.

The invention relates to a method and a device for managing LLC (Logical Link Control) resources. There is provided a method for managing LLC resources, comprising: receiving a memory mapping request from user mode software, the memory mapping request requesting to map a virtual memory address of the user mode software to a physical address of an LLC SRAM block; in response to the memory mapping request, allocating at least one LLC SRAM block from an LLC SRAM resource pool, where the LLC SRAM resource pool is a storage resource dynamically configured in an SRAM mode by configuring a first control state register in the LLC; establishing mapping from a virtual memory address of the user mode software to a physical address of the allocated LLC SRAM block, and configuring a page table item attribute of the mapping as a non-cache mode; and enabling the allocated LLC SRAM block by a second control state register.

The invention provides a weight memory mapping method and system for generating streaming operation of artificial intelligence hardware on a large scale. A weight memory mapping system according to one embodiment may include: a weight memory storing a weight matrix for a pre-trained artificial intelligence model; an input register that stores a plurality of input data; a first hardware arithmetic unit that processes a matrix multiplication operation between the plurality of input data and the weight matrix, and that multiplexes a partial sum of the matrix multiplication operation to calculate a final sum in a lane unit during the proceeding of the matrix multiplication operation; and a second hardware arithmetic unit for processing the next matrix multiplication operation by using the final sum in advance during the proceeding of the matrix multiplication operation.

This invention discloses an information processing system, an information processing method, and a program product. The information processing system includes a memory and a processor. The memory has a smaller memory capacity than the required capacity for executing multiple functions without switching memory mappings. The processor stores the usage history of the multiple functions for each user. When a user is logged in, the processor performs a process to switch the memory mappings based on the usage history of the logged-in user.

This invention relates to the field of game video generation technology, and particularly to a method for real-time generation of interactive pixel-style game videos. The method includes the following steps: establishing a real-time interactive driving mechanism based on a diffusion transformer; establishing a memory consistency constraint mechanism based on a Transformer memory mapping module; constructing a pixel-style optimization module using an encoder and decoder; reconstructing pixel-style video frames using an end-to-end diffusion transformer architecture; and generating interactive pixel-style game videos in real-time based on these pixel-style video frames. This supports core scenarios such as real-time development and live interactive streaming of pixel-style games.

The application discloses a device state analysis method and system based on DSL and dynamic compilation technology, wherein the method comprises the following steps: S1, importing a DSL file of device state parameters; S2, analyzing the DSL file through a T4 text template engine to dynamically generate C# intermediate code; S3, using a Roslyn compiler to dynamically compile to generate an assembly; S4, loading the assembly through reflection to receive a device state byte array data frame; S5, matching a structure type corresponding to the byte array to convert the byte array into a structure instance through memory mapping; S6, calling built-in or extended analysis methods through reflection to convert the structure into a general parameter class object; S7, outputting the instantiated object; and S8, transmitting, displaying or saving the device parameter instantiated object according to actual requirements. The application greatly shortens the analysis rule configuration time; and a new device protocol only needs to write a DSL file, without the need of redeploying the system; in addition, the application supports plug-in extension of custom analysis methods.

The application discloses a PMC parallel collection system and method of an ARM heterogeneous multi-core processor. By identifying the type of CPU core responsible for the collection task, a configured PMC event set is created for each online CPU core, and a performance counter is configured and enabled. During the sampling process, all threads use a unified sampling strategy and start sampling synchronously. Each sampling thread periodically reads the PMC counter value of its binding core, dynamically measures the actual sampling overhead of each core, and calculates the optimal sampling ratio in real time according to the load state and core type. Finally, for large and small core PMC data, the decision criteria are dynamically adjusted, a termination signal is sent to the sampling thread after data analysis, the performance event is closed, the memory mapping is released, and the resources are released. The method provides high-precision PMC collection performance monitoring and excellent collection efficiency, and greatly reduces the time overhead of collection.

The invention discloses a file processing method, electronic equipment, a storage medium and a computer program product, and relates to the technical field of cloud computing and cloud products. The method comprises the steps that in response to a file opening operation instruction, file content of a target disk file under a target disk is obtained based on first record information, the first record information is used for recording the corresponding relation between the target disk file and the target disk, and the target disk is a virtual disk corresponding to a target application; memory mapping operation is conducted on the file content, a read-only disk file is obtained, and the read-only disk file is a mirror image file of the target disk file in a memory; and performing file operation on the read-only disk file. According to the method and the device, the technical problems of poor system performance and poor stability caused by data inconsistency in writing and reading of a file processing scheme provided in related technologies are solved.

A zero trust content delivery framework secures proprietary data from autonomous AI scraping agents and link-bypassing attacks. The framework implements a multi-stage stateful handshake protocol requiring physical and computational Proof of Humanity. A verification engine analyzes human analog dynamics, including mouse jitter and device-specific accelerometer tilt, while a client-side SHA-256 Proof of Work imposes an asymmetric cryptographic tax. Content is delivered via just-in-time (JIT) memory-mapped streaming, rendered as volatile pixel data on a GPU-accelerated canvas to remove searchable text from a Document Object Model (DOM). An active counter-intelligence engine identifies bot signatures and serves shadow intelligence to degrade unauthorized training sets.

The invention discloses a zero-copy serialization method and device based on memory mapping, equipment and a medium, and relates to the field of data processing. In the method, a root object to be serialized is received, the root object and sub-objects are analyzed, and a field to be serialized is identified; constructing an object graph containing the reference relationship between the objects; in the object graph, recursively calculating the data size required for serializing the root object and the sub-object to obtain the total serialization size; according to the total serialization size, selecting and distributing a corresponding memory block from a preset layered memory pool, creating a memory mapping file corresponding to the memory block, and establishing a memory mapping buffer area based on the memory mapping file; traversing the object graph, and writing data of the root object and the sub-object into a memory mapping buffer area; the total length of the data is actually written into the memory mapping buffer area, and the total length of the data is written back into the reserved head area of the memory mapping buffer area. By implementing the technical scheme provided by the invention, the data serialization efficiency is improved.

This application discloses a data processing method, apparatus, computer device, and computer-readable storage medium. By performing memory mapping processing on a first file based on a target process, a mapped region of the first file in the virtual address space of the target process is obtained. The first file contains first target data and storage space-related data associated with the first target data. In response to a first data access instruction, the storage space-related data in the first file is obtained based on the mapped region. A first data object is generated based on the storage space-related data. Based on the first data object and the storage space-related data encapsulated in the first data object, a portion of the first target data in the first file is obtained. Responding to the first data access instruction based on the portion of the first target data allows the first data object generated in the target process to contain a small amount of storage space-related data, rather than all the data in the first file, thus reducing data usage in memory.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.