19302results about "Nanoinformatics" patented technology

A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C. during fabrication.

A thin film semiconductor and a method of its fabrication use induced crystallization and aggregation of a nanocrystal seed layer to form a merged-domain layer. The nanocrystal seed layer is deposited onto a substrate surface within a defined boundary. A reaction temperature below a boiling point of a reaction solution is employed. A thin film metal-oxide transistor and a method of its production employ the thin film semiconductor as a channel of the transistor. The merged-domain layer exhibits high carrier mobility.

A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C. during fabrication.

Copper chromite particles can advantageously be used as black particles in electrophoretic media and displays. Preferably, the copper chromite particles are coated with a silica coating and a polymer coating.

A demultiplexer for a two-dimensional array of a plurality of nanometer-scale switches (molecular wire crossbar network) is disclosed. Each switch comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting said pair of crossed wires in said junction. The connector species comprises a bi-stable molecule. The demultiplexer comprises a plurality of address lines accessed by a first set of wires in the two-dimensional array by randomly forming contacts between each wire in the first set of wires to at least one of the address lines. The first set of wires crosses a second set of wires to form the junctions. The demultiplexer solves both the problems of data input and output to a molecular electronic system and also bridges the size gap between CMOS and molecules with an architecture that can scale up to extraordinarily large numbers of molecular devices. Further, the demultiplexer is very defect tolerant, and can work despite a large number of defects in the system.

In a method for manufacturing semiconductor devices and other finely structured parts, a projection objective (5) is used in order to project the image of a pattern arranged in the object plane of the projection objective onto a photosensitive substrate which is arranged in the region of the image plane (12) of the projection objective. In this case, there is set between an exit surface (15), assigned to the projection objective, for exposing light and an incoupling surface (11), assigned to the substrate, for exposing light a small finite working distance (16) which is at least temporarily smaller in size and exposure time interval than a maximum extent of an optical near field of the light emerging from the exit surface. As a result, projection objectives with very high numerical apertures in the region of NA>0.8 or more can be rendered useful for contactless projection lithography.

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and my have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and / or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.

The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

A dielectrophoretic display comprises a substrate having walls defining at least one cavity, the cavity having a viewing surface and a side wall inclined to the viewing surface; a suspending fluid contained within the cavity; a plurality of at least one type of particle suspended within the suspending fluid; and means for applying to the substrate an electric field effect effective to cause dielectrophoretic movement of the particles to the side wall of the cavity.

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like.

Provided are organic n-doped electron transport layers comprising at least one electron transport material and at least one electron rich dopant material and organic p-doped hole transport layers comprising at least one hole transport material and at least one electron deficient dopant material.

A molecular-wire crossbar interconnect for signal routing and communications between a first level and a second level in a molecular-wire crossbar is provided. The molecular wire crossbar comprises a two-dimensional array of a plurality of nanometer-scale switches. Each switch is reconfigurable and self-assembling and comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. Each level comprises at least one group of switches and each group of switches comprises at least one switch, with each group in the first level connected to all other groups in the second level in an all-to-all configuration to provide a scalable, defect-tolerant, fat-tree networking scheme. The primary advantage is ease of fabrication, because an active switch is formed any time two wires cross. This saves tremendously on circuit area (a factor of a few times ten), since no other wires or ancillary devices are needed to operate the switch or store the required configuration. This reduction of the area of a configuration bit and its switch to just the area of two crossing wires is a major advantage in constructing a defect-tolerant interconnect network.

Microchannels having at least an acrylic inner surface and methods of their use in electrophoretic applications are provided. The subject microchannels may be in the form of a variety of configurations suitable for holding an electrophoretic medium. The subject microchannels give rise to substantially reduced EOF and / or adsorption as compared to fused silica under conditions of electrophoresis and find use in a variety of electrophoretic applications in which charged entities are moved through a medium under the influence of the an applied electric field.

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Compositions are provided comprising aqueous dispersions of at least one polypyrrole and at least one colloid-forming polymeric acids at methods of making such compositions. The new compositions are useful in electronic devices including organic electronic devices such as organic light emitting diode displays, memory storage, electromagnetic shielding, electrochromic displays,and thin film transistors, field effect resistance devices.

One or more highly-oriented, multi-walled carbon nanotubes are grown on an outer surface of a substrate initially disposed with a catalyst film or catalyst nano-dot by plasma enhanced hot filament chemical vapor deposition of a carbon source gas and a catalyst gas at temperatures between 300° C. and 3000° C. The carbon nanotubes range from 4 to 500 nm in diameter and 0.1 to 50 μm in length depending on growth conditions. Carbon nanotube density can exceed 104 nanotubes / mm2. Acetylene is used as the carbon source gas, and ammonia is used as the catalyst gas. Plasma intensity, carbon source gas to catalyst gas ratio and their flow rates, catalyst film thickness, and temperature of chemical vapor deposition affect the lengths, diameters, density, and uniformity of the carbon nanotubes. The carbon nanotubes of the present invention are useful in electrochemical applications as well as in electron emission, structural composite, material storage, and microelectrode applications.

The present invention is directed to methods for patterning a substrate by imprint lithography. An imprint lithography method includes placing a curable liquid on a substrate. A template may be contacted with the curable liquid. Surface forces at the interface of the curable liquid and the template cause the curable liquid to gather in an area defined by a lower surface of the template. Alternately, the curable liquid may fill one or more relatively shallow recesses in the template and the area under the template lower surface. Activating light is applied to the curable liquid to form a patterned layer on the substrate.

Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and / or oriented nanostructures, devices that include populations of positioned and / or oriented nanostructures, systems for positioning and / or orienting nanostructures, and related devices, systems and methods.