3497results about "Nanoinformatics" patented technology

The invention relates to the technical field of quantum computing and molecular electronic devices, in particular to a probabilistic bit device based on polyfluoroaryl methyl free radicals and a preparation method of the probabilistic bit device. According to the probabilistic bit device, the coupling efficiency of molecules and electrodes is improved by virtue of the characteristic that the paramagnetic unpaired electron spin state of tri (polyfluoroaryl) methyl free radical molecules can be used as a random expansion physical entropy source and high electronegativity and stability formed by modification of a plurality of strong electron-withdrawing fluorine atoms in the molecules. During the operation period of the device, the spin fluctuation can efficiently regulate and control tunneling current passing through molecules, promote random conversion between output high and low current states, show excellent random binary fluctuation characteristics, and simultaneously have high sensitivity and long coherence time. Compared with the prior art, the device has remarkable advantages in the aspects of device stability, energy efficiency ratio and external field controllability. The preparation method is simple and convenient to operate, mild in reaction condition and beneficial to large-scale production.

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

Systems and methods for characterizing an interaction between a compound and a polymer include obtaining a plurality of sets of atomic coordinates. Each set of atomic coordinates comprises the compound bound to the polymer in a corresponding pose in a plurality of poses. Each respective set of atomic coordinates, or an encoding thereof, is sequentially inputted into a neural network, to obtain a corresponding initial embedding as output, thereby obtaining a plurality of initial embeddings. Each initial embedding corresponds to a set of atomic coordinates in the plurality of sets of atomic coordinates. An attention mechanism is applied to the plurality of initial embeddings, in concatenated form, to obtain an attention embedding. A pooling function is applied to the attention embedding to derive a pooled embedding. The pooled embedding is inputted into a model to obtain an interaction score of the interaction between the compound and the polymer.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

A system may include a robotic control circuit configured to control one or more robotic functions of a robot. A system may include a plurality of sensors configured to collect data. A system may include a governance analysis circuit configured to analyze the data and select one or more governance frameworks based on the analyzed data. A system may include a governance model circuit configured to generate a model that applies the one or more governance frameworks to determine one or more governance actions, wherein the robotic control circuit is configured to control the one or more robotic functions in accordance with the one or more governance actions, wherein the robotic control circuit, the governance analysis circuit, and the governance model circuit are integrated on a single substrate.

In a general aspect, modular quantum processor configurations and methods, including integrating superconducting circuit quantum processor chips with a module integration plate that includes inter-module connections to form modular quantum processors are presented. In some cases, a quantum processing unit includes quantum processor chips, a module integration plate, and one or more caps. Each quantum processor chip includes a plurality of qubit devices. The quantum processor chips are disposed between the module integration plate and the one or more caps. The module integration plate includes recesses that house respective subsets of the quantum processor chips; and inter-module coupler devices that provide communication between the subsets of quantum processor chips housed in distinct recesses. The one or more cap wafers each includes signal lines that provide communication between at least one of the quantum processor chips and a control system.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source / drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

Manufacturing integrated circuit (IC) devices having adjacent transistors with different channel materials. A transistor includes a stack of nanoribbons coupling source and drain bodies, and a nanoribbon has a thickness at a midpoint of the nanoribbon greater than a thickness away from the midpoint. A second transistor may include a stack of nanoribbons coupling source and drain bodies, and the first transistor nanoribbons may have larger thickness variations than the second transistor nanoribbons. The first transistor nanoribbons may have a first element also in the second transistor nanoribbons and a second element absent in the second transistor nanoribbons. The second element may be added into the first transistor nanoribbons by depositing on the first transistor nanoribbons a layer having the second element, depositing a retaining layer over the second-element layer, and diffusing the second element into the first transistor nanoribbons.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source / drain region having the second conductivity type, on the first well; a first source / drain contact extending in a second direction and electrically connected to the first power rail, on the first source / drain region, a first connection wiring electrically connected to the first source / drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.

A quantum processor is discussed. the quantum processor having a flux compensation circuit communicatively coupled to a first qubit. The flux compensation circuit includes a quantum flux parametron (QFP) flux pump circuit with a first QFP in communication with the first qubit and a storage circuit with a second Josephson junction and a storage loop coupled in series with the QFP flux pump circuit. The communication between the QFP flux pump circuit and the storage loop is mediated by the second Josephson junction. A first control line is in communication with the first Josephson junction and a second control line is in communication with the second Josephson junction. In use. flux stored in the storage loop back acts on the first qubit.

An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source / drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source / drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source / drain region from the semiconductor substrate.

A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source / drain feature connected to the channel member and adjacent to the gate structure, a source / drain contact disposed below and connected to the source / drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source / drain contact. The first dielectric layer includes a low-k dielectric material.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.

This disclosure relates to quantum computing systems including a quantum processor that implements one or more operations on multiple qubits and a distributed data processing system programmed to perform calculations to determine control sequences that, when applied to the quantum processor, reduces decoherence, decoherence-induced errors, and control-imperfection-induced errors on the one or more operations on the multiple qubits. A user interface device remote from the distributed data processing system receives from a user of the quantum processor characteristics of the quantum processor including operational constraints and / or desired performance, and sends the characteristics to the data processing system to cause the data processing system to perform the calculations to determine the control sequence based on the characteristics.

Embodiments include a semiconductor structure having a first lower transistor and a second lower transistor. Upper transistors are formed above the first and second lower transistors, the first lower transistor having a first work function material, the second lower transistor having a second work function material different from the first work function material. A portion of the second work function material extends below a bottom surface of the first work function material.

A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source / drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.

Methods and systems are presented for using optical parametric amplifiers in various ways that enhance a native quadratic coupling strength so that a photonic component of interest can be measured or otherwise observed without demolishing the component of interest at a system output. For example such components may include a number of signal Bogoliubov excitations, a pump modular quadrature, or a signal quadrature squared.

Techniques are provided herein to form semiconductor devices having gate tie-down structures between the device gate and a buried / backside power rail (BPR). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure on a semiconductor region. The semiconductor region can be, for example, a fin or a set of one or more nanowires or nanoribbons that extends between a source region and a drain region. A BPR structure is beneath a dielectric layer that is between the BPR structure and the conductive material of the gate structure. A portion of the conductive material also extends through the dielectric material to provide a conductive via between the gate structure and the underlying BPR structure. The conductive material may be, for example, work function and / or metal fill material of the gate electrode of the gate structure.

An integrated circuit includes a first transistor and a second transistor. A first gate spacer is along a first portion of the common gate structure, the first gate spacer having a first width. A first inner spacer is between the first semiconductor channel layers and having a second width, the first width being greater than the second width. A second gate spacer is along a second portion of the common gate structure and having a third width. A second inner spacer is between the second semiconductor channel layers and having a fourth width, and the third width is greater than the fourth width, and the second width is greater than the fourth width. An isolation structure is in contact with one end of the common gate structure, the isolation structure having a fifth width, and the fifth width is greater than the first width and the third width.

To provide a filter stage system.SOLUTION: A filter stage system includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node. The at least one first impedance node has a higher impedance than the at least one second impedance node. The at least one first impedance node provides a dominant pole, and the at least one second impedance node provides a non-dominant pole. The continuous time baseband filter generates a filtered current. The filter stage system also includes a mirroring component that mirrors the filtered current to an output.SELECTED DRAWING: Figure 2

A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.

A method includes receiving a plurality of quantum systems, wherein each quantum system of the plurality of quantum system includes a plurality of quantum sub-systems in an entangled state, and wherein respective quantum systems of the plurality of quantum systems are independent quantum systems that are not entangled with one another. The method further includes performing a plurality of joint measurements on different quantum sub-systems from respective ones of the plurality of quantum systems, wherein the joint measurements generate joint measurement outcome data and determining, by a decoder, a plurality of syndrome graph values based on the joint measurement outcome data.