6962results about "Nanoinformatics" patented technology

A system may include a robotic control circuit configured to control one or more robotic functions of a robot. A system may include a plurality of sensors configured to collect data. A system may include a governance analysis circuit configured to analyze the data and select one or more governance frameworks based on the analyzed data. A system may include a governance model circuit configured to generate a model that applies the one or more governance frameworks to determine one or more governance actions, wherein the robotic control circuit is configured to control the one or more robotic functions in accordance with the one or more governance actions, wherein the robotic control circuit, the governance analysis circuit, and the governance model circuit are integrated on a single substrate.

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on / in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

A method includes forming a first gate structure across a first active region on a substrate within a memory region, wherein the first gate structure is of a first transistor being of a first conductivity type; forming a second gate structure across a second active region on the substrate within a peripheral region, wherein the second gate structure is of a second transistor being of a second conductivity type, the second conductivity type is opposite to the first conductivity type; forming a first gate contact over the first gate structure, the first gate contact overlapping with the first active region; forming a second gate contact over the second gate structure, the second gate contact non-overlapping with the second active region.

A semiconductor integrated-circuit (IC) chip includes: a first transistor, a second transistor at a same horizontal level as the first transistor, a first oxide layer at the same horizontal level as the first and second transistors, horizontally around the first and second transistors and having a portion horizontally between the first and second transistors; a frontside interconnection scheme under the first and second transistors and first oxide layer, a backside interconnection scheme over the first and second transistor and first oxide layer, and a metal interconnect vertically in the portion of the first oxide layer and coupling the frontside interconnection scheme to the backside interconnection scheme.

A semiconductor device comprises a gate cut portion disposed between a first gate region and a second gate region. The gate cut portion comprises a dielectric liner layer disposed around a vacant area. The dielectric liner layer encloses the vacant area, and the gate cut portion isolates the first gate region from the second gate region.

Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source / drain element of the first transistor to the first interconnect structure. The second contact connects a first source / drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.

Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Methods for enhancing the coherence of superconducting quantum bits with electric fields are disclosed comprising providing at least one qubit electrode comprising detrimental defects and intrinsic qubit resonance; and applying an intrinsic parameter of an electric field to the qubit electrode in order to tune the defects away from the qubit resonance, so that the energy relaxation time T1 of the qubit increases.

Embodiments include mixed complementary field effect and unipolar transistors and methods of forming the same. In an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source / drain region extending laterally from an end of the first semiconductor nanostructure, the first source / drain region having a first conductivity type; a second source / drain region extending laterally from an end of the second semiconductor nanostructure, the second source / drain region having the first conductivity type, the second source / drain region aligned vertically with the first source / drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure.

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

An integrated circuit device may include semiconductor regions; an insulating wall extending in a first lateral direction and passing in a vertical direction between a pair of semiconductor regions adjacent to each other in a second lateral direction among the semiconductor regions, a pair of nanosheet stacks overlapping the pair of semiconductor regions in the vertical direction and facing frontside surfaces of the pair of semiconductor regions, a pair of source / drain regions, and a backside contact. Each nanosheet stack may include a nanosheet having one end contacting a sidewall of the insulating wall in the second lateral direction. A contact end portion of the backside contact may be connected to one of the pair of source / drain regions. A contact sidewall of the backside contact may contact the insulating wall. The second lateral direction may be perpendicular to the first lateral direction.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

A multirail-encoded qubit can be implemented using a quantum system having a state space that includes a number M of distinct modes, where M is an integer greater than 2. The M modes are logically partitioned into two disjoint subsets (or “bands”), with each mode assigned to exactly one of the bands. The multirail encoding is defined such that a state in which any one of the modes in the first band is occupied and all modes in the second band are unoccupied maps to a logical 0 state of the qubit, and a state in which any one of the modes in the second band is occupied and all modes of the first band are unoccupied maps to a logical 1 state. Systems and methods for generating, measuring, and operating on multirail-encoded qubits are disclosed.

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium / aluminum oxide / niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and / or additive patterning. A superconducting metal layer may be deposited by electroplating and / or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

A semiconductor device includes a first transistor adjacent to a second transistor and an etch stop layer within an interlayer dialectic (ILD) to separate a lateral contact and a plurality of backside source / drain region-gate cut dielectric layers. The lateral contact connects a via over a first source / drain region of the first transistor to a second source / drain region of the second transistor.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.

Integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.

Method for operating a quantum computing element (1) with a network (2) of shuttling lanes (4) having multiple junctions (5) and multiple manipulation zones (7), wherein the method respectively comprises for a plurality of spin qubits (9):a) initializing the qubit (9),b) manipulating the qubit (9) in at least one of the manipulation zones (7),c) reading out the qubit (9),wherein at least one of the qubits (9) is shuttled along the network (2) of the shuttling lanes (4) between steps a) and c) so as to pass at least four different of the junctions (5).

A semiconductor structure including a first nanosheet transistor device, a second nanosheet transistor device, a dielectric gate cut structure between and electrically isolating the first nanosheet transistor device from the second nanosheet transistor device, where a first portion of the dielectric gate cut structure has a positive tapered profile, and a second portion of the dielectric gate cut structure has a negative tapered profile.

The present inventive concept relates to a spin qubit transistor (100) comprising a base layer (102), a first qubit comprising, a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged with a distance in the range of 3-10 nm therebetween, a second qubit comprising, a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged with a distance in the range of 3-10 nm therebetween, wherein each of said semiconductor islands has a size causing each of said semiconductor islands to exhibit 3-dimensional quantum confinement of a single electron hole, and wherein each of said semiconductor islands forms a semiconductor heterojunction with the base layer. Each of the semiconductor islands has a corresponding gate (G1-G4), for modulation of the computing islands or readout of the readout islands. Said first computing semiconductor island and said second computing semiconductor island are configured to have a unique resonance frequency respectively. A control electrode arrangement (B) between the computing and the readout islands controls the coupling between the qubits. The present inventive concept further comprises a method for forming a spin qubit transistor and a quantum computer comprising at least one spin qubit transistor.

Provided is a semiconductor device which includes: a channel structure; a gate structure on the channel structure; a 1st source / drain region on the channel structure; a substrate layer below the gate structure; a 1st etch-stop layer below the substrate layer; a backside spacer on side surfaces of the substrate layer and the 1st etch-stop layer; and a backside contact structure on a bottom surface of the 1st source / drain region and a side surface of the backside spacer.

A method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source / drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source / drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.

A method of forming source / drain regions of semiconductor devices is disclosed. The method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, removing a portion of the fin structure adjacent to the polysilicon structure to form an opening, and forming a S / D region in the opening. The forming the S / D region includes exposing the fin structure in the opening to a first flow rate of a precursor gas during a first phase of a gas flow cycle, a second flow rate of the precursor gas during a second phase of the gas flow cycle. The exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process.

A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source / drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.

A semiconductor structure includes a substrate; first nanostructures suspended over and vertically arranged over the substrate; a first gate structure wrapped around each of the first nanostructures; and gate spacers formed on opposite sides of the first gate structure and over a topmost one of the first nanostructures. The semiconductor structure further includes first source / drain features attached to opposite sides of the first nanostructures; and a first bottom dielectric layer formed over the substrate and below the first nanostructures. The first bottom dielectric layer is vertically sandwiched between the substrate and the first gate structure.