4371results about "Nanoinformatics" patented technology

A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

The invention relates to the technical field of quantum computing and molecular electronic devices, in particular to a probabilistic bit device based on polyfluoroaryl methyl free radicals and a preparation method of the probabilistic bit device. According to the probabilistic bit device, the coupling efficiency of molecules and electrodes is improved by virtue of the characteristic that the paramagnetic unpaired electron spin state of tri (polyfluoroaryl) methyl free radical molecules can be used as a random expansion physical entropy source and high electronegativity and stability formed by modification of a plurality of strong electron-withdrawing fluorine atoms in the molecules. During the operation period of the device, the spin fluctuation can efficiently regulate and control tunneling current passing through molecules, promote random conversion between output high and low current states, show excellent random binary fluctuation characteristics, and simultaneously have high sensitivity and long coherence time. Compared with the prior art, the device has remarkable advantages in the aspects of device stability, energy efficiency ratio and external field controllability. The preparation method is simple and convenient to operate, mild in reaction condition and beneficial to large-scale production.

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

In an embodiment, a device includes: a first nanostructure; a source / drain region adjoining a first channel region of the first nanostructure, the source / drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source / drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

The present invention relates to a method for calculating an electronic structure of a material by using quantum computing. Particularly, the method of the present invention for calculating an electronic structure of a material performed linking a quantum computer and a classical computer, may comprise the steps of: fragmenting a target molecule into fragments of a plurality of monomers having a predetermined positional relation; performing a first VQE routine for performing a Hamiltonian matrix calculation for the plurality of monomers on the basis of a calculation of electron density for the plurality of monomers, inputting modified electron density, and repeating the first VQE routine performing the Hamiltonian matrix calculation until the modified electron density according to the Hamiltonian matrix by the result of the first VQE routine converges; and performing a second VQE routine for performing a Hamiltonian matrix calculation on one or more dimers consisting of two monomer pairs of the plurality of monomers.

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

In an embodiment, a device includes: an isolation region on a substrate; first nanostructures above the isolation region; second nanostructures above the isolation region; a first gate spacer on the first nanostructures; a second gate spacer on the second nanostructures; a dielectric wall between the first gate spacer and the second gate spacer along a first direction in a top-down view, the dielectric wall disposed between the first nanostructures and the second nanostructures along a second direction in the top-down view, the first direction perpendicular to the second direction; and a gate structure around the first nanostructures and around the second nanostructures, a first portion of the gate structure filling a first area between the dielectric wall and the first nanostructures, a second portion of the gate structure filling a second area between the dielectric wall and the second nanostructures.

Systems and methods for characterizing an interaction between a compound and a polymer include obtaining a plurality of sets of atomic coordinates. Each set of atomic coordinates comprises the compound bound to the polymer in a corresponding pose in a plurality of poses. Each respective set of atomic coordinates, or an encoding thereof, is sequentially inputted into a neural network, to obtain a corresponding initial embedding as output, thereby obtaining a plurality of initial embeddings. Each initial embedding corresponds to a set of atomic coordinates in the plurality of sets of atomic coordinates. An attention mechanism is applied to the plurality of initial embeddings, in concatenated form, to obtain an attention embedding. A pooling function is applied to the attention embedding to derive a pooled embedding. The pooled embedding is inputted into a model to obtain an interaction score of the interaction between the compound and the polymer.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

A semiconductor structure is provided. The semiconductor structure includes a first plurality of nanostructures between a first source / drain feature and a second source / drain feature, a first gate segment surrounding the first plurality of nanostructures, and a wall structure abutting the first gate segment. A first nanostructure in the first plurality of nanostructures includes a bulk portion and a protrusion, and the protrusion protrudes from a first sidewall of the bulk portion toward the wall structure.

A system may include a robotic control circuit configured to control one or more robotic functions of a robot. A system may include a plurality of sensors configured to collect data. A system may include a governance analysis circuit configured to analyze the data and select one or more governance frameworks based on the analyzed data. A system may include a governance model circuit configured to generate a model that applies the one or more governance frameworks to determine one or more governance actions, wherein the robotic control circuit is configured to control the one or more robotic functions in accordance with the one or more governance actions, wherein the robotic control circuit, the governance analysis circuit, and the governance model circuit are integrated on a single substrate.

In a general aspect, modular quantum processor configurations and methods, including integrating superconducting circuit quantum processor chips with a module integration plate that includes inter-module connections to form modular quantum processors are presented. In some cases, a quantum processing unit includes quantum processor chips, a module integration plate, and one or more caps. Each quantum processor chip includes a plurality of qubit devices. The quantum processor chips are disposed between the module integration plate and the one or more caps. The module integration plate includes recesses that house respective subsets of the quantum processor chips; and inter-module coupler devices that provide communication between the subsets of quantum processor chips housed in distinct recesses. The one or more cap wafers each includes signal lines that provide communication between at least one of the quantum processor chips and a control system.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source / drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

Manufacturing integrated circuit (IC) devices having adjacent transistors with different channel materials. A transistor includes a stack of nanoribbons coupling source and drain bodies, and a nanoribbon has a thickness at a midpoint of the nanoribbon greater than a thickness away from the midpoint. A second transistor may include a stack of nanoribbons coupling source and drain bodies, and the first transistor nanoribbons may have larger thickness variations than the second transistor nanoribbons. The first transistor nanoribbons may have a first element also in the second transistor nanoribbons and a second element absent in the second transistor nanoribbons. The second element may be added into the first transistor nanoribbons by depositing on the first transistor nanoribbons a layer having the second element, depositing a retaining layer over the second-element layer, and diffusing the second element into the first transistor nanoribbons.

A method includes receiving a structure including a first region and a second region, forming a dielectric layer over the first region and the second region, forming a first patterned layer of a first dipole material on the dielectric layer in the first region, performing a first thermal drive-in operation to drive the first dipole material into the dielectric layer, forming a second patterned layer of a second dipole material on the dielectric layer in the second region, performing a second thermal drive-in operation to drive the second dipole material into the dielectric layer, performing a thermal operation to adjust distribution of the first dipole material or both the first and the second dipole materials in the dielectric layer, and forming a gate electrode layer over the dielectric layer. A portion of the first region overlaps with the second region.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

A semiconductor structure including a semiconductor channel member, a first dielectric layer over the semiconductor channel member, a second dielectric layer over the first dielectric layer, a metal layer over the second dielectric layer, first dipole elements distributed between the semiconductor channel member and the first dielectric layer, and second dipole elements distributed in the second dielectric layer.

A semiconductor IC structure includes a stacked transistor that has a top transistor stacked upon a bottom transistor. The bottom transistor includes at least a bottom source / drain region. The semiconductor IC structure further includes a replacement bottom source / drain region contact that includes a deep via region through at least the top semiconductor IC device and a monolithic region within the bottom semiconductor IC device directly coupled against a top surface of the bottom source / drain region. There is no interfacial impedance between the deep via region and the monolithic region. For example, there is no liner (e.g., such as a diffusion barrier, adhesion liner, or the like) between the deep via region and the monolithic region.

According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source / drain region having the second conductivity type, on the first well; a first source / drain contact extending in a second direction and electrically connected to the first power rail, on the first source / drain region, a first connection wiring electrically connected to the first source / drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.

A quantum processor is discussed. the quantum processor having a flux compensation circuit communicatively coupled to a first qubit. The flux compensation circuit includes a quantum flux parametron (QFP) flux pump circuit with a first QFP in communication with the first qubit and a storage circuit with a second Josephson junction and a storage loop coupled in series with the QFP flux pump circuit. The communication between the QFP flux pump circuit and the storage loop is mediated by the second Josephson junction. A first control line is in communication with the first Josephson junction and a second control line is in communication with the second Josephson junction. In use. flux stored in the storage loop back acts on the first qubit.

An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source / drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source / drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source / drain region from the semiconductor substrate.

A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source / drain feature connected to the channel member and adjacent to the gate structure, a source / drain contact disposed below and connected to the source / drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source / drain contact. The first dielectric layer includes a low-k dielectric material.

An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source / drain region in contact with one sidewall of the first nanosheet stack, and a second source / drain region in contact with another sidewall of the first nanosheet stack, wherein a greatest width of the first source / drain region is less than a greatest width of the second source / drain region in the second lateral direction may be provided.