40 results about "Signal routing" patented technology

A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts with a first average pitch, a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts with a second average pitch, and a signal routing structure between the first and second semiconductor devices and including a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a pattern of parallel conductive lines between the first and second pluralities of conductive structures. The pattern of parallel conductive lines has a third average pitch less than the first and second average pitches, and pairs of conductive structures from the first and second pluralities are electrically coupled by different ones of the parallel conductive lines.

An integrated circuit package and related manufacturing method are disclosed, comprising an additional metal pad with a reduced area for metal interconnects to reduce the die-to-substrate gap. The IC package includes a die interconnect with a first metal pad coupled to a metallization layer of the substrate to provide support and signal routing paths. To reduce the gap between the die and the substrate, and thus the height of the IC package, a second additional metal pad having a smaller cross-sectional area than the first metal pad is coupled to the first metal pad. Solder is used to couple the second additional metal pad to the die interconnect to couple the die to the substrate. When the solder is heated to form a solder joint, the solder flows along the reduced cross-sectional area of ​​the second additional metal pad.

This disclosure belongs to the field of semiconductor technology and addresses the problem of complex signal interconnections between memory chips and logic chips in three-dimensional chip stacking structures. It provides a memory chip, a logic chip, a chip stacking structure, and a memory. The memory chip includes 2A channel signal regions arranged sequentially along a first direction. Each channel signal region includes a first data signal region and a second data signal region arranged along the first direction. The first data signal region in the i-th channel signal region is symmetrical to the first data signal region in the (2A-i+1)-th channel signal region about a second axis, and the second data signal region in the i-th channel signal region is symmetrical to the second data signal region in the (2A-i+1)-th channel signal region about the second axis. Thus, after forming a three-dimensional chip stacking structure, the positions of the first and second data signal regions of the memory chip and the logic chip are aligned along a third direction, reducing the complexity of signal routing.

Embodiments herein relate to systems, devices, techniques, or processes for forming a bridge PCB within one or more metal layers of a main PCB. The bridge PCB, which can be fabricated using mSAP techniques, can be formed between the first and second metal layers of the main PCB and can be used for high-speed signal routing between two dies, such as a system-on-chip die and a memory die, located on the main PCB and coupled by the bridge PCB. Further embodiments may be described and / or claimed.

A die is described. The die includes a first seal ring on a periphery of the die, which encloses a core of the die. The die also includes one or more bridge interconnect structures across the first seal ring to route a signal from a test pad outside of the first seal ring to a circuit in the core.

A method includes forming a package component, the package component comprising: an interposer comprising a first redistribution structure; integrated circuit dies attached to the first redistribution structure; forming a package substrate, forming the package substrate comprising: forming a second redistribution structure and a third redistribution structure over opposite sides of a substrate core; singulating the substrate core to form component substrates; attaching a first component substrate and a second component substrate to a carrier, the first component substrate and the second component substrate being laterally displaced by a gap; and forming a bonding layer over the first component substrate and the second component substrate; attaching the package component to the package substrate; and forming external connectors over the package substrate, the external connectors being configured to electrically couple a signal routing, a power routing, or a ground routing of the integrated circuit dies to an another package component.

A box dipole radiating element uses a compact quadrilateral arrangement of substantially coplanar radiating arms that supports tilted polarized radiation in response to differential mode currents generated along four sides of the quadrilateral arrangement and in response to common mode currents that can be generated in substantially the same plane as the differential mode currents. A feed signal routing network is provided that includes a feed signal routing substrate located on portions of the radiating arms, first through fourth signal traces located on a front side of the substrate, and first through fourth ground plane segments located on a back side of the substrate. The first through fourth ground plane segments are capacitively coupled to the radiating arms. Each of the signal traces receives a corresponding feed signal and spans a corresponding air gap between a pair of the radiating arms.

Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. The multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.

An embodiment may include an example method, which may involve scheduling circular beam's downlink and uplink in-phase and quadrature (I / Q) signals, converting massive MIMO beam I / Q signals without actually performing beamforming, maintaining a beams-to-radio-heads mapping where the mapping is either statically configured during installation or dynamically updated using various algorithms, routing a beam's digital downlink signals to radio heads or broadcasting all beams' digital downlink signals to radio heads, digitally summing the digital uplink signals belonging to the same beam, A / D and D / A converting, and transmitting or receiving via antennas to form circular beams.

A device is provided, including a bridge having a first input / output pin and a second input / output pin; a plurality of traces extending horizontally between the first input / output pin and the second input / output pin, the second input / output pin being coupled to a predetermined one or more of the traces; and a first programmable circuit coupled between the first input / output pin and the plurality of traces. The first programmable circuit may include at least one of a demultiplexing section or a multiplexing section. The demultiplexing section may demultiplex a multiplexed signal from the first input / output pin into at least one subset of signals, and route a respective subset of signals to a corresponding one of the traces. The multiplexing section may multiplex the at least one subset of signals from the plurality of traces into the multiplexed signal, and route the multiplexed signal to the first input / output pin.

The present disclosure is directed to a system that includes a radio frequency (RF) board configured to support multiple frequency bands and antenna configurations through dynamic routing and selective component population. The RF board includes an antenna feed, first and second signal paths, and frequency processing sites, allowing a single antenna feed to connect to either path by populating specific components. This configuration enables processing of different signal frequencies without altering PCB substrate pathways. Integrated switches, such as SPDT or PIN diodes, facilitate software-driven routing adjustments in some embodiments, optimizing performance based on real-time requirements. A manufacturing process involves configuring the PCB with pre-existing signal paths and selectively populating components to meet SKU requirements. The RF board's layout supports signal routing to various processing components, ensuring proper impedance and minimal interference. This system provides efficient signal management, scalability, and enhanced performance, while maintaining adaptability across diverse wireless standards.

The present disclosure relates to a display device and display panel. An example display device includes a display panel having a normal area with a plurality of subpixels, an optical area in which an optical electronic device is located, and a link area in which a driving signal line extends from a pad area. A driving circuit is configured to transmit a driving signal through the driving signal line. The optical area includes a first moisture-proof pattern positioned between the optical electronic device and the normal area. The link area includes a second moisture-proof pattern positioned between the pad area and the normal area. By providing distinct moisture proof patterns in both the optical area and the link area, the display panel can block moisture penetration paths associated with the emission layer and with signal routing, thereby improving operational reliability and durability of the display device.

An apparatus, system, and method for signal routing in a system lacking a backplane. One apparatus includes an interface card and a cable having a first connector configured to couple with a storage drive via the interface card, a second connector configured to couple with a motherboard, and a third connector configured to couple with a storage controller located apart from the motherboard. The cable routes control signals and data signals between the storage drive, the storage controller, and the motherboard.

A memory cell includes an active region extending lengthwise along a first direction and first and second gate structures extending lengthwise along a second direction different from the first direction. The first gate structure engages the active region in forming a first transistor, and the second gate structure engages the active region in forming a second transistor. The memory cell further includes a first epitaxial feature disposed on a source region of the first transistor, a second epitaxial feature disposed on a common drain region of the first and second transistors, a backside contact disposed under and in electrical coupling with the first epitaxial feature, a backside signal line disposed under and in electrical coupling with the backside contact, and a first frontside contact disposed above and in electrical coupling with the second epitaxial feature.

This invention relates to optical switch network chips, specifically to an optical switch network chip with multi-wavelength routing capabilities and an optical signal routing method, to address the shortcomings of existing wavelength-routing optical switching network schemes, such as system complexity, large chip area, and crosstalk superposition. The optical switch network chip of this invention with multi-wavelength routing capabilities is used to realize the routing and switching of multi-wavelength optical signals. It includes an input port, an output port, multiple wavelength-routing optical switch units sequentially arranged between the input and output ports, and multiple waveguide interconnect networks connecting adjacent wavelength-routing optical switch units. Each wavelength-routing optical switch unit includes multiple wavelength-selective optical switches for wavelength selection and output, ultimately enabling optical signals input at any input port to alternately pass through multiple wavelength-routing optical switch units and multiple waveguide interconnect networks, and be routed to any output port.

An electronic memory device includes a non-memory cell region and a memory cell region including circuitry formed in a substrate. The memory cell region includes first, second, and third sections. In a top view, the first section is closest to the non-memory cell region. The second and third sections are both farther from the non-memory cell region than the first section. In a cross-sectional side view, a first interconnect structure is disposed over a first side of the substrate. The first interconnect structure includes a first interconnect layer and a second interconnect layer. The first and second interconnect layers are configured to route memory signals to the first and second sections, respectively. A second interconnect structure is disposed on a second side of the substrate. The second interconnect structure includes a third interconnect layer configured to route memory signals to the third section. The present disclosure also relates to methods of fabricating an electronic memory device and methods of modifying an integrated circuit layout design.

The application discloses a kind of computing power node optical switching equipment and optical switching system, belong to optical switching field, considering that optical communication is naturally with the characteristics of larger bandwidth, and by first optical splitter, the optical signal multiplexing of computing power node can be multiple to optical switch, optical switch can flexibly realize the signal routing between each optical port, therefore, first optical splitter in the application includes at least one first end and multiple second ends, the first end is connected with a corresponding computing power node in server, and the second end is connected with optical switch through optical backplane;And optical switch can route the received optical signal to the corresponding target optical port under the control of control module;By controlling optical switch, the optical communication between different computing power node combinations performing the same computing task can be flexibly realized, and has larger bandwidth, and complex fiber layout can be avoided through optical backplane.

For transducer connection to an integrated circuit, a silicon or other wafer-based chip is processed to provide signal routing, such as altering the pitch using wafer process deposited conductors. This chip or silicon interposer may be more simply re-designed to relate the pitch of an array to the integrated circuit I / Os, avoiding redesign of the integrated circuit.

An electronic substrate implements fault-tolerant signal routing in redistribution layers by pairing aligned conductors in different metal layers and periodically tying the pair with vias so the same signal traverses both paths. The redundant geometry maintains electrical continuity when an open defect occurs in one conductor while preserving target resistance by apportioning the total cross-section between the paired traces. Test access structures enable continuity verification from the top surface, supporting single-sided probing of through-silicon-via connectivity and fabric links. The approach applies to high-density interconnects such as chip-to-chip fabrics and memory interfaces on silicon circuit boards and interposer-class substrates, improving yield and reliability at large layout scales without increasing layer count.

A system may include a first DAS station, comprising a first plurality of interrogator units to launch a first plurality of DAS signals in a first direction, wherein a first interrogator unit is configured to launch a first DAS signal at a first interrogation rate and first wavelength, wherein a second interrogator unit is configured to launch a second DAS signal at a second wavelength and second interrogation rate, less than the first interrogation rate. The system may include a loopback array, comprising a plurality of loopbacks, arranged over a plurality of spans, wherein a first set of proximate loopbacks nearest to the first DAS station are configured to route back the first DAS signal to the first DAS station, and wherein a first set of intermediate loopbacks, located further from the first DAS station, are configured to route back the second DAS signal to the first DAS station.

This application discloses an integrated circuit and its routing node, applied in the field of circuit technology, including: a routing module, a network interface, and a system-level functional module; the routing module includes: a routing unit connected to each input signal terminal and each output signal terminal of the routing node for signal routing; N direct-connect switches; each of the N direct-connect switches corresponds one-to-one with the N non-local input signal terminals of the routing node, and the first terminal of each of the N direct-connect switches is connected to its corresponding non-local input signal terminal; the second terminal of any one of the direct-connect switches is connected to the output signal terminal of the routing node according to a preset connection relationship; and a direct-connect control unit, used to control all N direct-connect switches to be turned off when the routing node is in routing mode, and to control all N direct-connect switches to be turned on when the routing node is in shielded mode. Applying the scheme of this application, transmission delay can be effectively reduced in shielded mode, improving the application flexibility of the integrated circuit.

This invention relates to the field of generative artificial intelligence and discloses a semantic processing method for 5G message parsing, comprising: inputting a 5G message text sequence into a generative language model; calculating the information entropy of the intermediate network layer; terminating the calculation and extracting the hidden layer state tensor when the information entropy is lower than a threshold; determining the set of legitimate intentions based on the 5G protocol state and transition topology; modulating the initial logarithmic probability tensor using a mask tensor to mask semantic outputs outside the protocol range; calculating the normalized probability distribution sequence and determining the target parsing intention. This invention maps protocol rules to the boundary of the logarithmic probability space, blocks signaling routing failures caused by probability divergence, resolves the conflict between semantic generation and protocol rigor, and ensures the determinism of service parsing under telecommunications conditions.

The present invention relates to a universal guitar nut system that integrates multiple pickup technologies, AI-driven signal processing, sustain enhancement, and note-bending capabilities into a single modular assembly. The system captures string vibrations directly at the nut, enabling acoustic-like and electric tonal output independent of bridge pickups or body resonance. It supports piezoelectric, magnetic, optical, and future sensing technologies, providing flexible signal routing via wired or wireless outputs. AI modules analyze performance in real-time, dynamically shaping tone, sustain, and harmonic response. A piezo-actuated sustainer provides controlled string vibration for infinite sustain, while integrated note-bender functionality allows pitch modulation directly at the nut. The system is compatible with standard and Floyd Rose-equipped guitars, requiring no structural modifications, offering musicians enhanced tonal versatility, expressive control, and seamless integration with modern digital workflows.

We provide a parametric system simulation device. [Solution] The parametric system simulation apparatus (100) according to the present invention comprises a structural enclosure (102). A parameter input device (104) having a user-operable input device receives numerical parameter values ​​representing baseline indicators related to interacting entities of the simulated system. A signal acquisition interface (106) converts the received parameter values ​​into electrical parameter signals and transmits them via a data communication bus to a parameter storage assembly consisting of a non-volatile memory structure. A signal routing assembly (110) including a selectable switching arrangement activates one of a plurality of stored interaction model structures representing alternative functional relationships between electrical parameter signals. A signal processing assembly (112) consisting of interconnected processing circuits converts the electrical parameter signals and generates state signals representing the equilibrium state between the simulated subsystems.

A compute array employs inter-layer multiplexers between stacked processing layers to maintain continuous signal paths when column segments become defective. Each processing column includes multiple processing elements that generate partial-sum signals transmitted vertically through the stack. The multiplexers dynamically route these signals through adjacent functional column segments, preserving connectivity from the top layer to the output-sum region. A controller identifies defective segments by comparing final output sums and reconfigures multiplexer states without halting computation. The architecture provides column-segment fault tolerance with minimal area and timing overhead.

Hybrid antenna structures for seamless integration of free space and surface electromagnetic wave (SEW) radiation are described. In some examples, the hybrid antenna may comprise a helical antenna free space radiator coupled to an SEW antenna feed point. The system may include a radio frequency switch and reflectometers configured to sense impedance at the helical antenna and SEW feed point, dynamically routing signals based on the sensed impedance. A free space radiation feed line and an SEW radiation feed line may be connected to the radio frequency switch and reflectometers, enabling efficient operation in varying environments. This configuration may allow the antenna to function as a conventional free space radiator or a plasmonic surface wave antenna, optimizing performance without user intervention.

A method of forming a semiconductor device includes forming a package assembly including: an interposer including a first redistribution structure; an integrated circuit die attached to the first redistribution structure; forming a package substrate including: forming a second redistribution structure and a third redistribution structure over opposing sides of a substrate core; singulating the substrate core to form assembly substrates; attaching the first assembly substrate and the second assembly substrate to a carrier, the first assembly substrate and the second assembly substrate laterally offset by a gap; and forming a bonding layer over the first assembly substrate and the second assembly substrate; attaching the package assembly to the package substrate; and forming external connections over the package substrate, the external connections configured to electrically couple signal routing, power routing, or ground routing of the integrated circuit die to another package assembly. Embodiments of the present disclosure also provide semiconductor devices.