396 results about "Signal routing" patented technology

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention discloses a power grid multi-range intelligent sensing method and system based on MEMS integration, and relates to the technical field of intelligent sensing, and the method comprises the steps: connecting an MEMS sensing unit to three parallel measurement channels, and connecting the MEMS sensing unit to a controllable signal routing module in parallel; after gating, the signals are sent to a successive approximation analog-to-digital converter for digitalization through nonlinear gain amplification and anti-aliasing filtering; determining a measuring range based on a sampling sequence and a sliding window ratio, and automatically switching channels through a threshold value and a hysteresis mechanism; performing baseline correction on the switching data and performing weighted fusion according to sensitivity and bandwidth; and after the laboratory performs segmented calibration and consistency verification on the three channels, calibration parameters are written and stored, and are transmitted to an upper system through an isolation power supply according to a preset protocol. Automatic range switching is achieved through a sliding window and a hysteresis mechanism, baseline drift correction and weighting fusion according to the proportion of sensitivity and bandwidth are adopted after channel switching, and measurement continuity and precision consistency are ensured.

A chip includes a power grid, power switches coupled between the power grid and a circuit, and current sensors configured to generate sense currents based on load currents passing through the power switches. The chip also includes a readout circuit having an input and an output, and signal routing coupling the current sensors to the input of the readout circuit.

A box dipole radiating element uses a compact quad arrangement of substantially coplanar radiating arms to support slant-polarized radiation, in response to differential-mode currents generated along four sides thereof and in response to common-mode currents, which may be generated in substantially the same plane as the differential-mode currents. A feed signal routing network is provided, which includes a feed signal routing substrate on portions of the radiating arms, first through fourth signal traces on a forward face of the substrate, and first through fourth ground plane segments on a rear face of the substrate. These first through fourth ground plane segments are capacitively coupled to the radiating arms. Each of the signal traces receives a corresponding feed signal, and spans a corresponding air gap between a pair of the radiating arms.

This disclosure describes an electronic device that can be installed within an access control system in parallel with a legacy interface device. The electronic device may perform steps of determining a set of configuration settings associated with an access control system to which the electronic device is electrically connected, receiving, by the electronic device, a first signal in a format associated with the access control system, configuring, based on the set of configuration settings, one or more signal pathways within the electronic device, generating, by routing the first signal through the one or more signal pathways, a second signal in a second format, and providing the second signal to at least one second electronic device.

A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input / output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

Provided is a semiconductor device which includes a 1st source / drain region; and a 1st contact structure on a 1st portion of the 1st source / drain region; and a 2nd contact structure on a 2nd portion of the 1st source / drain region, wherein at least one of the 1st contact structure and the 2nd contact structure is configured to connect the 1st source / drain region to a voltage source or another circuit element for signal routing.

The invention provides a system and a method for generating CAN (Controller Area Network) mailbox configuration and data routing configuration based on a communication matrix table. The method comprises the following steps of: reading a predefined finished automobile CAN communication network signal routing information table; analyzing the whole vehicle CAN communication network signal routing information table to obtain CAN communication configuration parameters of each CAN channel; the number of receiving mailboxes and the number of sending mailboxes of each CAN channel are distributed according to the maximum number of receiving mailboxes and the maximum number of sending mailboxes supported by the whole vehicle CAN communication network hardware for each CAN channel and CAN communication configuration parameters of each CAN channel; and when the number of the messages to be processed of a certain CAN channel exceeds the allocated mailbox number, classifying the messages, and multiplexing the same mailbox by the messages belonging to the same class. According to the method, CAN mailbox resources are used to the greatest extent, and the reliability of data routing is ensured; when the whole vehicle communication network signal routing table is frequently changed, the reliability of the routing function is ensured, and meanwhile, the development efficiency is improved.

A radio frequency (RF) source may be used to generate a capacitively coupled plasma to perform a plasma-based process on a substrate in a plasma processing chamber. A controller may cause the RF source and a switching element to route an RF signal to electrodes in the pedestal that generate the plasma in the processing chamber as part of a recipe performed on a substrate during etch or deposition processes. Between processes, the controller may cause the same RF source to generate a second RF signal that is instead routed by the switching element to inductive coils to generate an inductively coupled plasma for a cleaning process to remove film deposits on the interior of the plasma processing chamber.

The invention discloses a broadband single-pole double-throw switch MMIC, and belongs to the field of radio frequency / microwave. The switch adopts a symmetrical dual-channel structure, each channel comprises an input end series switch circuit, an output end series switch circuit and two parallel switch branches, channel switching is realized through two complementary control voltages, and impedance matching is carried out between the circuits by adopting microstrip lines. According to the technical scheme, switching tubes, resistors and inductors are utilized to form a circuit network, and a signal transmission path is optimized through the resonance effect of the inductors and switching tube cut-off capacitors in parallel branches in combination with a resistor parallel structure and a microstrip line matching technology. According to the invention, the performance of low insertion loss and high isolation in a broadband is achieved, the voltage standing wave ratio of an off-state output port is reduced, the port matching capability is improved, and an efficient and stable solution is provided for signal routing in a radio frequency system.

A switching circuit comprises a first filter, a second filter and a plurality of switches. The first filter is configured to filter a first frequency band, a second frequency band that is adjacent to the first frequency band and a gap band between the first frequency band and the second frequency band. The second filter is configured to filter the second frequency band. The plurality of switches is configured to route signals from an antenna through one of the first filter and second filter.

Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (“die”) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

A magnetless cryogenic circulator is developed that has three identical resonators in three branches. Each branch connects two ports and each resonator has a capacitor connected across a tunable inductor. A set of tunable inductors modulated with modulation signals that have a relative phase of 0°, 120° and 240° provided through a circuit. A microstrip delay line for providing the modulation signal to the three resonators, wherein the resonators are modulated in time such that the degeneracy of the two inherent counter-rotating modes is lifted, achieving a non-reciprocal signal routing. All capacitors and inductors are monolithically integrated and fabricated using a multi-layer Nb-based process with Nb / AlOx / Nb JJs.

Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to / from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

A measurement probe for producing a test signal for a measurement instrument includes a probe head structured to be connected to at least a first testing point and a second testing point of a Device Under Test (DUT), a current detector in the measurement probe structured to determine a current flowing between the first testing point and the second testing point of the DUT, a first selectable signal path that causes a voltage signal from the first testing point or a voltage signal from the second testing point to be routed to the measurement instrument as a selected voltage test signal, and a second selectable signal path that causes a current signal from an output of the current detector to be routed to the measurement instrument as a selected current test signal. Methods of testing a DUT using the measurement probe are also described, as well as a system for measuring signals from a DUT using the measurement probe.

The invention discloses a storage chip, a storage component, a memory and electronic equipment, which are used for reducing metal resources occupied by power supply wiring. Wherein the memory chip comprises a wafer and an active layer embedded in the wafer, the active layer comprises an active device, the active device is a device in a peripheral circuit of the memory chip, and a first electrode of the active device is in contact with a power supply on the back surface of the wafer or is grounded to realize power supply; and a storage array in the storage chip performs signal routing through metal resources on one side of the active surface of the wafer. Because the peripheral circuit and the storage array are distributed at different positions of the storage chip, the scheme of back power supply in the peripheral circuit can not influence the storage device in the storage array, thereby saving the metal resource which is originally used as the power supply wire at one side of the active surface of the wafer on the basis of keeping the read-write function of the storage chip, and reducing the cost. And the input and output line channels of the storage array in the storage chip are expanded, so that the bandwidth of the storage chip is increased.

Stacked metal-oxide-metal (MoM) capacitor(s) in front side and back side metallization layers of a semiconductor die, and related fabrication methods. The stacked MoM capacitor includes a first, front side, MoM capacitor formed on the front side of the semiconductor layer of a die and in front side metallization layers in a front side interconnect structure. The stacked MoM capacitor also includes a second, back side MoM capacitor formed on the back side of the semiconductor layer in back side metallization layers in a back side interconnect structure. The front side and back side MoM capacitors are coupled to each other through a conducting structure in a second, vertical direction between the front side and back side interconnect structures to form the stacked MoM capacitor. In this manner, capacitance density in the die can be maintained or increase while providing sufficient area in the front side metallization layers for signal routing.

The invention discloses a high-performance dynamic routing circuit for improving S parameter measurement and a multi-port expansion box, and relates to an S parameter test and port expansion technology. The routing circuit applied to the transmitting path comprises four output ends, six transmitting branch port input ends, a transmitting total port input end, four first-stage equalization amplifiers, two first-stage one-to-two switches, two second-stage equalization amplifiers, four first-stage one-to-three switches, a first-stage one-to-four switch and a third-stage equalization amplifier. The internal paths of the circuit are symmetrical, and the transmission path length of signal routing gating is minimized through the arrangement of a total port and branch ports, so that high performance is ensured. The multi-port expansion box comprises a routing circuit applied to a transmitting path, a routing circuit applied to a reference / test receiving path, a transmitting / reference receiving / test receiving standard configuration routing amplification unit, a bi-directional coupler matrix and the like. Port expansion can be flexibly configured and high performance can be ensured.

Aspects disclosed herein include integrated circuit (IC) packages employing capacitor interposer substrates with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies ("dies") electrically coupled to a package substrate that supports electrical signal routing to and from the die (s). A capacitor interposer substrate is disposed between the die (s) and the package substrate. The die (s) are coupled to the embedded capacitor (s) in the capacitor interposer substrate through a die interconnect coupled to an external interconnect of the capacitor interposer substrate. In an exemplary aspect, external interconnects on an outer surface of a capacitor interposer substrate are aligned. In this manner, if the die (s) and the package substrate have a pattern of die interconnects and external interconnects designed to align with each other when coupled to each other, the capacitor interposer substrate may remain compatible with the interconnects of the die (s) and the package substrate.

Integrated circuits (ICs) having a separate signal and power distribution network (PDN) interconnect structures for reduced power signal routing congestion and path lengths, and related three-dimensional (3D) ICs (3DICs) and fabrication methods. The IC includes a separate signal interconnect structure providing input / output (I / O) signal routing, and a PDN interconnect structure for providing power distribution signal routing. The signal interconnect structure is disposed on a first side of a semiconductor layer in the IC, and the PDN interconnect structure is disposed on a second side of the semiconductor layer opposite of the first side. In this manner, performance of semiconductor devices in the semiconductor layer can be improved, because power distribution signals do not have to be routed in a shared interconnect structure that is also used for routing I / O signals, which could otherwise congest and increase power distribution signal routing path lengths in the IC.

The invention relates to the technical field of communication, and particularly discloses a front-end communication circuit and a communication method, and the front-end communication circuit comprises a communication chip, a first external change-over switch and a second external change-over switch. The communication chip is provided with a first transceiver interface, a second transceiver interface and a third transceiver interface. The first external change-over switch is configured to selectively route a middle-high frequency band signal to the first transceiving interface or allow the signal to be input through the second transceiving interface or the third transceiving interface; meanwhile, the second external change-over switch is used for switching the MIMO radio frequency signal to the second transceiver interface or the third transceiver interface. All the selected signals are finally input into the communication chip through corresponding interfaces to be processed. According to the scheme, flexible frequency band combination and carrier aggregation configuration can be supported so as to meet the differentiation requirements of global 5G frequency bands. In addition, through dynamic configuration of an external switch and an interface, a single hardware design can be compatible with module schemes of multiple domestic semiconductor manufacturers, and repeated development investment is avoided.

Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).

The invention discloses an FIR filter circuit structure, and the structure comprises a path control unit which generates a first control signal and a second control signal according to the number and order of filters which are customized by a user; the routing unit correspondingly transmits the filtering data received by the filtering data channel unit to the multiply-add unit array based on the first control signal; the multiply-add unit array comprises N multiply-add units, and the multiply-add units are connected through data selectors; the path control register unit is connected with a selection port of the data selector, and the path control register unit controls a data path of the multiply-add unit array through the data selector based on a second control signal; and the filtering result operation unit adds the multiplication and addition results of the corresponding multiplication and addition unit to obtain the filtering result of the corresponding filter. According to the invention, the multiplication and addition unit structure of the filter circuit can be customized according to user requirements, and the FIR filter circuit with low circuit resource ratio and high operation speed is configured.

Provided is a semiconductor package comprising a layer stack. The layer stack of the semiconductor package comprises a first plurality of conductive layers forming a plurality of antenna elements of an end-fire antenna array, wherein each antenna element is configured for a first polarization and for a second polarization, and at least one conductive signal routing layer adjacent to the first plurality of conductive layers, the conductive signal routing layer comprising first routing traces for the first polarization and second routing traces for the second polarization.

This disclosure relates to systems and methods for improving routing of an audio output signal from an electronic device to an audio output device. Such a system can include at least one inertial measurement unit (IMU) arranged in the audio output device; and at least one processor configured to: receive data from the at least one IMU, determine a current status of the audio output device from the received data as either worn or unworn, route an audio output signal from the electronic device to the audio output device if the current status of the audio output device is worn, and route the audio output signal to an audio output of the electronic device if the current status of the audio output device is unworn.

Systems, apparatus and methods for defining an impairment profile along a polarization quantum channel such as in terms of modal loss and decoherence. The disclosed impairment profile or characterization methods may be used as part of a tool such as to inform a network operator of a weakest span of the communication channel, thus facilitating optimal signal routing decisions.

The disclosed computer-implemented apparatus for bridge-based packaging with direct power delivery can include an first layer stacked on a second layer. The second layer can include an interposer die and a connection die. The first layer can include a chiplet die positioned above the interposer die and a first-layer bridge die spanning across the interposer die and the connection die. The interposer die can include a set of physical interfaces and a set of routing features configured to route signals from the set of physical interfaces to the first-layer bridge die. Various other apparatuses, systems, and methods of manufacture are also disclosed.

The invention relates to the field of testing, and provides a signal routing testing method and system and electronic equipment, and the method comprises the steps: responding to a received testing instruction, and determining the signal type of a testing signal corresponding to the testing instruction; determining a test signal value corresponding to a test signal according to the signal type, and performing fault injection on the test signal according to the signal type to obtain a target signal value; in response to the fact that the target signal value is the same as the test signal value, determining that the test result is that the signal routing is normal; or, in response to the fact that the target signal value is different from the test signal value, determining that the test result is signal routing abnormity. According to the method and the device, the problem that the test coverage is not comprehensive due to the fact that the test on the signal routing of the vehicle is limited by the whole vehicle environment, only some signal states can be tested generally, and all signal states cannot be tested is solved.

The invention relates to a low-power-consumption vibration signal collecting and processing system and method based on a heterogeneous multi-core system. The system comprises an MCU, an MPU, an SOC in-chip interconnection module, a trigger signal module and a data collecting controller module. The SOC in-chip interconnection module comprises a signal routing module, an interruption interconnection module, a shared data address bus and a shared RAM (Random Access Memory); the MCU comprises a first sleep wake-up module, a first data acquisition module, a first data storage module and an MPU wake-up synchronization module; the MPU comprises a second dormancy awakening module, a second data acquisition module, a second data storage module and an MCU acquisition data carrying module; the invention further provides an acquisition method based on the system, the vibration signal acquisition system can be quickly awakened, and loss of signal data in the whole awakening process can be avoided.