258 results about "Signal routing" patented technology

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention discloses a power grid multi-range intelligent sensing method and system based on MEMS integration, and relates to the technical field of intelligent sensing, and the method comprises the steps: connecting an MEMS sensing unit to three parallel measurement channels, and connecting the MEMS sensing unit to a controllable signal routing module in parallel; after gating, the signals are sent to a successive approximation analog-to-digital converter for digitalization through nonlinear gain amplification and anti-aliasing filtering; determining a measuring range based on a sampling sequence and a sliding window ratio, and automatically switching channels through a threshold value and a hysteresis mechanism; performing baseline correction on the switching data and performing weighted fusion according to sensitivity and bandwidth; and after the laboratory performs segmented calibration and consistency verification on the three channels, calibration parameters are written and stored, and are transmitted to an upper system through an isolation power supply according to a preset protocol. Automatic range switching is achieved through a sliding window and a hysteresis mechanism, baseline drift correction and weighting fusion according to the proportion of sensitivity and bandwidth are adopted after channel switching, and measurement continuity and precision consistency are ensured.

The invention provides a system and a method for generating CAN (Controller Area Network) mailbox configuration and data routing configuration based on a communication matrix table. The method comprises the following steps of: reading a predefined finished automobile CAN communication network signal routing information table; analyzing the whole vehicle CAN communication network signal routing information table to obtain CAN communication configuration parameters of each CAN channel; the number of receiving mailboxes and the number of sending mailboxes of each CAN channel are distributed according to the maximum number of receiving mailboxes and the maximum number of sending mailboxes supported by the whole vehicle CAN communication network hardware for each CAN channel and CAN communication configuration parameters of each CAN channel; and when the number of the messages to be processed of a certain CAN channel exceeds the allocated mailbox number, classifying the messages, and multiplexing the same mailbox by the messages belonging to the same class. According to the method, CAN mailbox resources are used to the greatest extent, and the reliability of data routing is ensured; when the whole vehicle communication network signal routing table is frequently changed, the reliability of the routing function is ensured, and meanwhile, the development efficiency is improved.

The invention discloses a broadband single-pole double-throw switch MMIC, and belongs to the field of radio frequency / microwave. The switch adopts a symmetrical dual-channel structure, each channel comprises an input end series switch circuit, an output end series switch circuit and two parallel switch branches, channel switching is realized through two complementary control voltages, and impedance matching is carried out between the circuits by adopting microstrip lines. According to the technical scheme, switching tubes, resistors and inductors are utilized to form a circuit network, and a signal transmission path is optimized through the resonance effect of the inductors and switching tube cut-off capacitors in parallel branches in combination with a resistor parallel structure and a microstrip line matching technology. According to the invention, the performance of low insertion loss and high isolation in a broadband is achieved, the voltage standing wave ratio of an off-state output port is reduced, the port matching capability is improved, and an efficient and stable solution is provided for signal routing in a radio frequency system.

A magnetless cryogenic circulator is developed that has three identical resonators in three branches. Each branch connects two ports and each resonator has a capacitor connected across a tunable inductor. A set of tunable inductors modulated with modulation signals that have a relative phase of 0°, 120° and 240° provided through a circuit. A microstrip delay line for providing the modulation signal to the three resonators, wherein the resonators are modulated in time such that the degeneracy of the two inherent counter-rotating modes is lifted, achieving a non-reciprocal signal routing. All capacitors and inductors are monolithically integrated and fabricated using a multi-layer Nb-based process with Nb / AlOx / Nb JJs.

Stacked metal-oxide-metal (MoM) capacitor(s) in front side and back side metallization layers of a semiconductor die, and related fabrication methods. The stacked MoM capacitor includes a first, front side, MoM capacitor formed on the front side of the semiconductor layer of a die and in front side metallization layers in a front side interconnect structure. The stacked MoM capacitor also includes a second, back side MoM capacitor formed on the back side of the semiconductor layer in back side metallization layers in a back side interconnect structure. The front side and back side MoM capacitors are coupled to each other through a conducting structure in a second, vertical direction between the front side and back side interconnect structures to form the stacked MoM capacitor. In this manner, capacitance density in the die can be maintained or increase while providing sufficient area in the front side metallization layers for signal routing.

Integrated circuits (ICs) having a separate signal and power distribution network (PDN) interconnect structures for reduced power signal routing congestion and path lengths, and related three-dimensional (3D) ICs (3DICs) and fabrication methods. The IC includes a separate signal interconnect structure providing input / output (I / O) signal routing, and a PDN interconnect structure for providing power distribution signal routing. The signal interconnect structure is disposed on a first side of a semiconductor layer in the IC, and the PDN interconnect structure is disposed on a second side of the semiconductor layer opposite of the first side. In this manner, performance of semiconductor devices in the semiconductor layer can be improved, because power distribution signals do not have to be routed in a shared interconnect structure that is also used for routing I / O signals, which could otherwise congest and increase power distribution signal routing path lengths in the IC.

The invention relates to the technical field of communication, and particularly discloses a front-end communication circuit and a communication method, and the front-end communication circuit comprises a communication chip, a first external change-over switch and a second external change-over switch. The communication chip is provided with a first transceiver interface, a second transceiver interface and a third transceiver interface. The first external change-over switch is configured to selectively route a middle-high frequency band signal to the first transceiving interface or allow the signal to be input through the second transceiving interface or the third transceiving interface; meanwhile, the second external change-over switch is used for switching the MIMO radio frequency signal to the second transceiver interface or the third transceiver interface. All the selected signals are finally input into the communication chip through corresponding interfaces to be processed. According to the scheme, flexible frequency band combination and carrier aggregation configuration can be supported so as to meet the differentiation requirements of global 5G frequency bands. In addition, through dynamic configuration of an external switch and an interface, a single hardware design can be compatible with module schemes of multiple domestic semiconductor manufacturers, and repeated development investment is avoided.

The invention discloses an FIR filter circuit structure, and the structure comprises a path control unit which generates a first control signal and a second control signal according to the number and order of filters which are customized by a user; the routing unit correspondingly transmits the filtering data received by the filtering data channel unit to the multiply-add unit array based on the first control signal; the multiply-add unit array comprises N multiply-add units, and the multiply-add units are connected through data selectors; the path control register unit is connected with a selection port of the data selector, and the path control register unit controls a data path of the multiply-add unit array through the data selector based on a second control signal; and the filtering result operation unit adds the multiplication and addition results of the corresponding multiplication and addition unit to obtain the filtering result of the corresponding filter. According to the invention, the multiplication and addition unit structure of the filter circuit can be customized according to user requirements, and the FIR filter circuit with low circuit resource ratio and high operation speed is configured.

Provided is a semiconductor package comprising a layer stack. The layer stack of the semiconductor package comprises a first plurality of conductive layers forming a plurality of antenna elements of an end-fire antenna array, wherein each antenna element is configured for a first polarization and for a second polarization, and at least one conductive signal routing layer adjacent to the first plurality of conductive layers, the conductive signal routing layer comprising first routing traces for the first polarization and second routing traces for the second polarization.

This disclosure relates to systems and methods for improving routing of an audio output signal from an electronic device to an audio output device. Such a system can include at least one inertial measurement unit (IMU) arranged in the audio output device; and at least one processor configured to: receive data from the at least one IMU, determine a current status of the audio output device from the received data as either worn or unworn, route an audio output signal from the electronic device to the audio output device if the current status of the audio output device is worn, and route the audio output signal to an audio output of the electronic device if the current status of the audio output device is unworn.

The embodiment of the invention provides a continuous playing method and system for a multimedia data stream, a storage medium and an electronic device, and the method comprises the steps: transmitting a first data packet corresponding to the multimedia data stream to a mobile terminal when a first playing terminal plays the multimedia data stream, the mobile terminal uses the first data packet to generate a continuous playing instruction data packet required by continuous playing of a second playing terminal in the at least two playing terminals; analyzing a continuous playing instruction data packet sent by the mobile terminal to obtain a continuous playing instruction; generating a control signal according to the playing progress of the first playing terminal, cutting off a signal route of the first playing terminal by using the control signal, and obtaining a continuous playing data stream of the multimedia data stream according to the continuous playing address; and performing format conversion on the continuous playing data stream according to the playing format of the second playing terminal to obtain the target data stream, and playing the target data stream on the second playing terminal, thereby solving the problem of how to improve the continuous playing efficiency of the equipment in a multi-equipment switching playing scene in the related technology.

The present application provides a method and device for automatically generating a controller software routing information configuration file based on the Autosar architecture. By quickly identifying the routing relationships in the CAN matrix, it configures the entire frame routing relationships according to the identified routing relationships, configures the signal routing relationships according to the identified routing relationships, and finally outputs the entire frame routing relationships and signal routing relationships to the arxml file to achieve full-automatic configuration of routing information, improving the time efficiency and configuration quality of AUTOSAR configuration.

The embodiment of the invention discloses a storage method and device compatible with multiple protocols and electronic equipment, and relates to the technical field of computer storage architecture.The method comprises the steps that PCIe interface equipment is integrated on a standard board card through physical layer integration, and the standard board card is connected with a CPU through a PCIe physical layer interface; pCIe interface equipment integrated on a board card is segmented by utilizing a PCIe channel segmentation technology, so that the PCIe interface equipment independently works on the same board card and does not interfere with each other; the bandwidth is automatically allocated according to the load type, and the resource allocation between the PCIe interface devices is dynamically adjusted according to the demand of an actual application scene through an intelligent resource scheduling algorithm; a shared power management unit and a radiator are arranged, and efficient signal routing modes such as flyby topology are adopted, so that the capacity and the performance of PCIe interface equipment are expanded. The problems that in the prior art, cost is high, performance is limited, expansibility is poor, and the high-performance requirements of a high-density server and edge computing are difficult to meet are solved.

The invention discloses a reconfigurable parallel reading architecture and a parallel reading method of an image sensor. The objective of the invention is to solve the technical contradiction that the reading frame rate must be sacrificed when noise reduction or HDR is realized by using time serial processing in the prior art. The signal routing MUX is configured to be switched between at least one high-speed mode and one parallel mode. In the high-speed mode, signals of the first pixel unit and the second pixel unit are controlled to be routed to the first column reading circuit and the second column reading circuit respectively. In a parallel mode, a first pixel unit signal is controlled to be routed concurrently to the first and second column readout circuits. In a parallel mode, noise reduction may be achieved by configuring the two column readout circuits to the same gain and applying different Offsets, or by configuring the two column readout circuits to different gains to achieve HDR. According to the method, time serial processing is replaced by space parallel processing, and high speed, noise reduction and HDR functions are efficiently and flexibly realized on the premise that the frame rate is not sacrificed.

The present invention discloses a wiring method between a printed circuit board, a processor and a memory, and an electronic device. The wiring method includes the steps of: (a) allowing the data signal routing path between the processor and the memory to be first from a first signal layer to a second signal layer, and then from the second signal layer to the first signal layer, wherein a first ground layer serving as a reference layer for the first signal layer and the second signal layer is located between the first signal layer and the second signal layer, and the first signal layer and the second signal layer both have a complete projection on the first ground layer; (b) allowing the address signal routing path between the processor and the memory to be first from a fourth signal layer to the second signal layer, and then from the second signal layer to the fourth signal layer, wherein a power supply layer serving as a reference layer for the fourth signal layer is located between the second signal layer and the fourth signal layer, and the fourth signal layer has a complete projection on the power supply layer.

A device comprises a switch circuit and control lines. The switch circuit comprises a plurality of signal input / output ports, and a plurality of switch nodes, each switch node comprising a superconducting loop which comprises a plurality of Josephson junctions arranged in a ring configuration. The control lines are configured to selectively apply flux bias control signals to the switch nodes. The plurality of switch nodes is arranged to selectively configure a signal routing path between any pairwise combination of signal input / output ports of the plurality of signal input / output ports, in response to flux bias control signals selectively applied to the switch nodes.

The present invention relates to a light-emitting substrate and a method for preparing the same, a display panel, and a display device. The light-emitting substrate includes a base substrate, one side of which is provided with an electrical signal routing layer, a first reflective layer, and a light-emitting unit; the electrical signal routing layer is connected to the light-emitting unit and is used to provide an electrical signal to the light-emitting unit; the first reflective layer is used to reflect and emit light incident on the first reflective layer; the light-emitting substrate also includes a reflective layer upper structure formed on the first reflective layer, the reflective layer upper structure includes at least one functional layer, and the overall light transmittance of the reflective layer upper structure is greater than a set value. The above-mentioned light-emitting substrate has an overall light transmittance of the reflective layer upper structure greater than a set value, which can ensure that the first reflective layer reflects and reuses, and more light is transmitted from the light-transmitting area, and more light will be emitted from the light-emitting surface of the light-emitting substrate.

The disclosure relates to a substrate package that effectively supports signal routing for high data rate applications. An apparatus includes a substrate having a first side and a second side, where the first side is opposite the second side. The apparatus also includes a die positioned on the second side of the substrate and electrically coupled to the substrate. The apparatus includes a signal routing component positioned on a first side of the substrate. The signal routing component is configured to route a signal between the die and the external component through the substrate to the device. The apparatus includes a circuit board positioned on the second side of the substrate. The circuit board is electrically coupled to the substrate.

An antenna and receiver design is described herein that allows a spacecraft to safely and accurately perform an autonomous flight safety system, an ascent, an entry, a re-entry, a landing, and / or an orbit determination. For example, a spacecraft can be equipped with 180-degree dual-opposed antennas and two receivers. A signal captured by a first antenna can be routed to a secondary radio frequency (RF) of the first receiver and to a combiner. A signal captured by a second antenna can be routed to a secondary RF of the second receiver and to the combiner. The mixer can perform the phase combination operation on the signals captured by the first receiver and the second receiver to produce a phase combined signal, and can route the phase combined signal to the primary RF of the first receiver and to the primary RF of the second receiver.

A communication control system according to the present invention comprises a plurality of communication devices and a communication control device. The communication devices each comprise: a plurality of input / output ports; a signal strength monitoring unit that monitors the signal strength of signals passing through the input / output ports and notifies the communication control device only when a measured value of the signal strength is less than a prescribed threshold value; and a route setting unit that switches the input / output port to be used on the basis of a route setting switching instruction acquired from the communication control device. The communication control device comprises: a monitoring object setting unit that controls the signal strength monitoring unit so that only the input / output port through which the signal passes is monitored; an analysis unit that searches for another signal route connecting the plurality of communication devices when the notification is received from the signal strength monitoring unit; and a route setting control unit that transmits, to the plurality of communication devices, the route setting switching instruction to switch to the other signal route searched for by the analysis unit.

A chip (100) comprising: an interconnection layer (110) and a plurality of dies disposed on the interconnection layer (110), the plurality of dies comprising a first die (1) and a second die (2), the first die (1) and the second die (2) being directly interconnected by routing lines in an edge region, wherein the edge region indicates a region outside a frame in the interconnection layer (110), the frame indicating a peripheral boundary of the plurality of dies in the interconnection layer (110). Since the edge region in the interconnection layer (110) is free of signal routing lines and is not disturbed by other data signals, the direct interconnection between the first die (1) and the second die (2) by routing lines in the edge region can reduce the delay of the data signals transmitted between the two dies and improve the data transmission efficiency.

A circuit board apparatus employing a stacked circuit board and with inductor (s) for routing power from a power management integrated circuit (IC) (PMIC) to a secondary circuit board, and related methods of manufacture. The inductor (s) is coupled in a first vertical direction between the first circuit board and the second circuit board as part of a power routing path between the PMIC on the first circuit board and the second electronic component (s) of the second circuit board. In this manner, the PMIC may be shared between the first circuit board and the second circuit board to manage power signals provided to the first electronic component (s) and the second electronic component (s) of the first circuit board. The inductor (s) may also be strategically positioned to provide a shorter power signal routing path to reduce or avoid power performance issues with a reduced impedance between the PMIC and the second electronic component (s).

A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts with a first average pitch, a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts with a second average pitch, and a signal routing structure between the first and second semiconductor devices and including a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a pattern of parallel conductive lines between the first and second pluralities of conductive structures. The pattern of parallel conductive lines has a third average pitch less than the first and second average pitches, and pairs of conductive structures from the first and second pluralities are electrically coupled by different ones of the parallel conductive lines.

Package substrate with a core having metallization layers to facilitate signal routing within the core, and related fabrication methods and integrated circuit (IC) packages. The core includes multiple core metallization layers that can be formed separately and coupled to each other to provide signal routing within the core. Metal interconnects in the multiple core metallization layers are coupled to each other through coupling of the core metallization layers to each other in the core to provide signal routing paths through the core. Including separate core metallization layers in the core provides flexibility in patterning location of the metal interconnects therein for routing flexibility within the core. This is opposed to only including singular body, vertical interconnects extending through the entire height of the core. Metal interconnects can also be patterned to extend laterally within a respective core metallization layer to provide lateral signal routing paths within a core metallization layer.

The present application discloses a display panel and a spliced ​​screen, wherein the display panel includes a circuit substrate, a base substrate, a display component, a cover chip film, a fan-out portion and connecting lines, wherein the circuit substrate includes a mounting area and a connecting area, the circuit substrate includes a routing through-hole located in the connecting area, the base substrate is located on one side of the circuit substrate, the base substrate is arranged in the mounting area, the display component is located on a side of the base substrate away from the circuit substrate, the display component includes a driving circuit layer and a plurality of light-emitting elements, the cover chip film is located on a side of the circuit substrate away from the base substrate, the fan-out portion is located between the circuit substrate and the cover chip film, the fan-out portion includes a plurality of fan-out routing lines, one end of the fan-out routing line is connected to the cover chip film, the first end of the connecting routing line is connected to the driving circuit layer, and the second end of the connecting routing line passes through the routing through-hole and is connected to the other end of the fan-out routing line, thereby eliminating the need to set signal routing lines on both the front and back sides of the base substrate, thereby reducing the difficulty of the display panel manufacturing process.

The invention discloses an integrated circuit and a routing node thereof, which are applied to the technical field of circuits, and comprise a routing module, a network interface and a system-level function module, the routing module comprises a routing unit which is connected with each input signal end and each output signal end of the routing node and is used for carrying out signal routing; n direct connection switches; the N direct connection switches are in one-to-one correspondence with the N non-local input signal ends of the routing node, and the first ends of the N direct connection switches are respectively connected with the non-local input signal ends corresponding to the N direct connection switches; the second end of any direct connection switch is connected to the output signal end of the routing node according to a preset connection relation; and the direct connection control unit is used for controlling the N direct connection switches to be turned off when the routing node is in the routing mode, and controlling the N direct connection switches to be turned on when the routing node is in the shielding mode. By applying the scheme of the invention, the transmission delay can be effectively reduced in the shielding mode, and the application flexibility of the integrated circuit is improved.

Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

An integrated circuit package and related manufacturing method are disclosed, comprising an additional metal pad with a reduced area for metal interconnects to reduce the die-to-substrate gap. The IC package includes a die interconnect with a first metal pad coupled to a metallization layer of the substrate to provide support and signal routing paths. To reduce the gap between the die and the substrate, and thus the height of the IC package, a second additional metal pad having a smaller cross-sectional area than the first metal pad is coupled to the first metal pad. Solder is used to couple the second additional metal pad to the die interconnect to couple the die to the substrate. When the solder is heated to form a solder joint, the solder flows along the reduced cross-sectional area of ​​the second additional metal pad.

Various implementations related to the use of nanosheet transistors formed on a substrate are disclosed. A nanosheet transistor includes an active region with a width that defines an active device width for the transistor. Hybrid cell structures are disclosed that include varying cell heights (e.g., tall and short cells) aligned with fixed width power grid routes. The fixed width of the power grid routes provides spacings for variations of signal route spacing between the power grid routes depending on the size of the underlying cell. These structures provide flexibility for tall to short cell ratios on a partition level in logic blocks.