186 results about "Signal routing" patented technology

The invention discloses a power grid multi-range intelligent sensing method and system based on MEMS integration, and relates to the technical field of intelligent sensing, and the method comprises the steps: connecting an MEMS sensing unit to three parallel measurement channels, and connecting the MEMS sensing unit to a controllable signal routing module in parallel; after gating, the signals are sent to a successive approximation analog-to-digital converter for digitalization through nonlinear gain amplification and anti-aliasing filtering; determining a measuring range based on a sampling sequence and a sliding window ratio, and automatically switching channels through a threshold value and a hysteresis mechanism; performing baseline correction on the switching data and performing weighted fusion according to sensitivity and bandwidth; and after the laboratory performs segmented calibration and consistency verification on the three channels, calibration parameters are written and stored, and are transmitted to an upper system through an isolation power supply according to a preset protocol. Automatic range switching is achieved through a sliding window and a hysteresis mechanism, baseline drift correction and weighting fusion according to the proportion of sensitivity and bandwidth are adopted after channel switching, and measurement continuity and precision consistency are ensured.

The invention provides a system and a method for generating CAN (Controller Area Network) mailbox configuration and data routing configuration based on a communication matrix table. The method comprises the following steps of: reading a predefined finished automobile CAN communication network signal routing information table; analyzing the whole vehicle CAN communication network signal routing information table to obtain CAN communication configuration parameters of each CAN channel; the number of receiving mailboxes and the number of sending mailboxes of each CAN channel are distributed according to the maximum number of receiving mailboxes and the maximum number of sending mailboxes supported by the whole vehicle CAN communication network hardware for each CAN channel and CAN communication configuration parameters of each CAN channel; and when the number of the messages to be processed of a certain CAN channel exceeds the allocated mailbox number, classifying the messages, and multiplexing the same mailbox by the messages belonging to the same class. According to the method, CAN mailbox resources are used to the greatest extent, and the reliability of data routing is ensured; when the whole vehicle communication network signal routing table is frequently changed, the reliability of the routing function is ensured, and meanwhile, the development efficiency is improved.

A magnetless cryogenic circulator is developed that has three identical resonators in three branches. Each branch connects two ports and each resonator has a capacitor connected across a tunable inductor. A set of tunable inductors modulated with modulation signals that have a relative phase of 0°, 120° and 240° provided through a circuit. A microstrip delay line for providing the modulation signal to the three resonators, wherein the resonators are modulated in time such that the degeneracy of the two inherent counter-rotating modes is lifted, achieving a non-reciprocal signal routing. All capacitors and inductors are monolithically integrated and fabricated using a multi-layer Nb-based process with Nb / AlOx / Nb JJs.

The invention relates to the technical field of communication, and particularly discloses a front-end communication circuit and a communication method, and the front-end communication circuit comprises a communication chip, a first external change-over switch and a second external change-over switch. The communication chip is provided with a first transceiver interface, a second transceiver interface and a third transceiver interface. The first external change-over switch is configured to selectively route a middle-high frequency band signal to the first transceiving interface or allow the signal to be input through the second transceiving interface or the third transceiving interface; meanwhile, the second external change-over switch is used for switching the MIMO radio frequency signal to the second transceiver interface or the third transceiver interface. All the selected signals are finally input into the communication chip through corresponding interfaces to be processed. According to the scheme, flexible frequency band combination and carrier aggregation configuration can be supported so as to meet the differentiation requirements of global 5G frequency bands. In addition, through dynamic configuration of an external switch and an interface, a single hardware design can be compatible with module schemes of multiple domestic semiconductor manufacturers, and repeated development investment is avoided.

This disclosure relates to systems and methods for improving routing of an audio output signal from an electronic device to an audio output device. Such a system can include at least one inertial measurement unit (IMU) arranged in the audio output device; and at least one processor configured to: receive data from the at least one IMU, determine a current status of the audio output device from the received data as either worn or unworn, route an audio output signal from the electronic device to the audio output device if the current status of the audio output device is worn, and route the audio output signal to an audio output of the electronic device if the current status of the audio output device is unworn.

The invention discloses a reconfigurable parallel reading architecture and a parallel reading method of an image sensor. The objective of the invention is to solve the technical contradiction that the reading frame rate must be sacrificed when noise reduction or HDR is realized by using time serial processing in the prior art. The signal routing MUX is configured to be switched between at least one high-speed mode and one parallel mode. In the high-speed mode, signals of the first pixel unit and the second pixel unit are controlled to be routed to the first column reading circuit and the second column reading circuit respectively. In a parallel mode, a first pixel unit signal is controlled to be routed concurrently to the first and second column readout circuits. In a parallel mode, noise reduction may be achieved by configuring the two column readout circuits to the same gain and applying different Offsets, or by configuring the two column readout circuits to different gains to achieve HDR. According to the method, time serial processing is replaced by space parallel processing, and high speed, noise reduction and HDR functions are efficiently and flexibly realized on the premise that the frame rate is not sacrificed.

The disclosure relates to a substrate package that effectively supports signal routing for high data rate applications. An apparatus includes a substrate having a first side and a second side, where the first side is opposite the second side. The apparatus also includes a die positioned on the second side of the substrate and electrically coupled to the substrate. The apparatus includes a signal routing component positioned on a first side of the substrate. The signal routing component is configured to route a signal between the die and the external component through the substrate to the device. The apparatus includes a circuit board positioned on the second side of the substrate. The circuit board is electrically coupled to the substrate.

An antenna and receiver design is described herein that allows a spacecraft to safely and accurately perform an autonomous flight safety system, an ascent, an entry, a re-entry, a landing, and / or an orbit determination. For example, a spacecraft can be equipped with 180-degree dual-opposed antennas and two receivers. A signal captured by a first antenna can be routed to a secondary radio frequency (RF) of the first receiver and to a combiner. A signal captured by a second antenna can be routed to a secondary RF of the second receiver and to the combiner. The mixer can perform the phase combination operation on the signals captured by the first receiver and the second receiver to produce a phase combined signal, and can route the phase combined signal to the primary RF of the first receiver and to the primary RF of the second receiver.

A chip (100) comprising: an interconnection layer (110) and a plurality of dies disposed on the interconnection layer (110), the plurality of dies comprising a first die (1) and a second die (2), the first die (1) and the second die (2) being directly interconnected by routing lines in an edge region, wherein the edge region indicates a region outside a frame in the interconnection layer (110), the frame indicating a peripheral boundary of the plurality of dies in the interconnection layer (110). Since the edge region in the interconnection layer (110) is free of signal routing lines and is not disturbed by other data signals, the direct interconnection between the first die (1) and the second die (2) by routing lines in the edge region can reduce the delay of the data signals transmitted between the two dies and improve the data transmission efficiency.

A circuit board apparatus employing a stacked circuit board and with inductor (s) for routing power from a power management integrated circuit (IC) (PMIC) to a secondary circuit board, and related methods of manufacture. The inductor (s) is coupled in a first vertical direction between the first circuit board and the second circuit board as part of a power routing path between the PMIC on the first circuit board and the second electronic component (s) of the second circuit board. In this manner, the PMIC may be shared between the first circuit board and the second circuit board to manage power signals provided to the first electronic component (s) and the second electronic component (s) of the first circuit board. The inductor (s) may also be strategically positioned to provide a shorter power signal routing path to reduce or avoid power performance issues with a reduced impedance between the PMIC and the second electronic component (s).

A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts with a first average pitch, a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts with a second average pitch, and a signal routing structure between the first and second semiconductor devices and including a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a pattern of parallel conductive lines between the first and second pluralities of conductive structures. The pattern of parallel conductive lines has a third average pitch less than the first and second average pitches, and pairs of conductive structures from the first and second pluralities are electrically coupled by different ones of the parallel conductive lines.

Package substrate with a core having metallization layers to facilitate signal routing within the core, and related fabrication methods and integrated circuit (IC) packages. The core includes multiple core metallization layers that can be formed separately and coupled to each other to provide signal routing within the core. Metal interconnects in the multiple core metallization layers are coupled to each other through coupling of the core metallization layers to each other in the core to provide signal routing paths through the core. Including separate core metallization layers in the core provides flexibility in patterning location of the metal interconnects therein for routing flexibility within the core. This is opposed to only including singular body, vertical interconnects extending through the entire height of the core. Metal interconnects can also be patterned to extend laterally within a respective core metallization layer to provide lateral signal routing paths within a core metallization layer.

The invention discloses an integrated circuit and a routing node thereof, which are applied to the technical field of circuits, and comprise a routing module, a network interface and a system-level function module, the routing module comprises a routing unit which is connected with each input signal end and each output signal end of the routing node and is used for carrying out signal routing; n direct connection switches; the N direct connection switches are in one-to-one correspondence with the N non-local input signal ends of the routing node, and the first ends of the N direct connection switches are respectively connected with the non-local input signal ends corresponding to the N direct connection switches; the second end of any direct connection switch is connected to the output signal end of the routing node according to a preset connection relation; and the direct connection control unit is used for controlling the N direct connection switches to be turned off when the routing node is in the routing mode, and controlling the N direct connection switches to be turned on when the routing node is in the shielding mode. By applying the scheme of the invention, the transmission delay can be effectively reduced in the shielding mode, and the application flexibility of the integrated circuit is improved.

Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

An integrated circuit package and related manufacturing method are disclosed, comprising an additional metal pad with a reduced area for metal interconnects to reduce the die-to-substrate gap. The IC package includes a die interconnect with a first metal pad coupled to a metallization layer of the substrate to provide support and signal routing paths. To reduce the gap between the die and the substrate, and thus the height of the IC package, a second additional metal pad having a smaller cross-sectional area than the first metal pad is coupled to the first metal pad. Solder is used to couple the second additional metal pad to the die interconnect to couple the die to the substrate. When the solder is heated to form a solder joint, the solder flows along the reduced cross-sectional area of ​​the second additional metal pad.

Various implementations related to the use of nanosheet transistors formed on a substrate are disclosed. A nanosheet transistor includes an active region with a width that defines an active device width for the transistor. Hybrid cell structures are disclosed that include varying cell heights (e.g., tall and short cells) aligned with fixed width power grid routes. The fixed width of the power grid routes provides spacings for variations of signal route spacing between the power grid routes depending on the size of the underlying cell. These structures provide flexibility for tall to short cell ratios on a partition level in logic blocks.

The invention relates to the technical field of wireless communication services, and discloses an electric power emergency repair disaster-resistant RIS beam dynamic optimization method. The method is used for solving the problem that in a traditional method, RIS auxiliary communication lacks an elastic recovery mechanism in a disaster environment. The method comprises the following steps: firstly, acquiring RIS auxiliary communication parameters to form operation data; identifying an interrupt event based on a comparison of the data to a threshold, determining a location, type, and range, generating an event description; assessing disaster factors by using description classification, extracting influence parameters, associating with a power line repair scene, and establishing an interruption model; generating a beam adjustment scheme according to the model, selecting phase shift configuration, planning a reconstruction path and integrating emergency priorities to form an instruction sequence; executing sequence reconfiguration of a phase shift matrix, adjusting the beam direction and amplitude, and coordinating signal routing; after reconfiguration, parameters are circularly collected and updated, interruption is returned for re-identification, and a closed-loop monitoring mechanism is formed; according to the invention, the power communication toughness under disasters is improved, and the emergency repair service continuity is ensured.

The invention provides a chip system and a task processing method, and the chip system comprises a task scheduling module which is used for cutting a calculation task into a plurality of calculation sub-tasks, and generating a task cutting signal corresponding to the calculation task; the synchronization module comprises a routing unit and a plurality of task monitoring units, and the routing unit is used for receiving the task cutting signal and routing the task cutting signal to a target task monitoring unit in the task monitoring units according to the number of idle monitoring channels contained in the task monitoring units; at least one calculation module in the plurality of calculation modules is used for receiving the plurality of calculation subtasks from the task scheduling module and executing the plurality of calculation subtasks, and the at least one calculation module is further used for generating task completion signals corresponding to the calculation tasks in the process of executing the plurality of calculation subtasks and sending the task completion signals to the task scheduling module. And the task completion signal is routed to the target task monitoring unit through the routing unit, so that the target task monitoring unit monitors the execution states of the plurality of calculation sub-tasks according to the task cutting signal and the task completion signal. According to the invention, the routing unit is introduced into the synchronization module, so that load balancing among a plurality of task monitoring units is facilitated.

This disclosure belongs to the field of semiconductor technology and addresses the problem of complex signal interconnections between memory chips and logic chips in three-dimensional chip stacking structures. It provides a memory chip, a logic chip, a chip stacking structure, and a memory. The memory chip includes 2A channel signal regions arranged sequentially along a first direction. Each channel signal region includes a first data signal region and a second data signal region arranged along the first direction. The first data signal region in the i-th channel signal region is symmetrical to the first data signal region in the (2A-i+1)-th channel signal region about a second axis, and the second data signal region in the i-th channel signal region is symmetrical to the second data signal region in the (2A-i+1)-th channel signal region about the second axis. Thus, after forming a three-dimensional chip stacking structure, the positions of the first and second data signal regions of the memory chip and the logic chip are aligned along a third direction, reducing the complexity of signal routing.

A signal restructure unit for radio frequency (RF) antenna systems includes four ports and a signal routing circuit. The signal routing circuit receives RF signals at input ports and provides phase-controlled outputs to antenna ports. When receiving sum signals, the unit provides in-phase restructured signals for common-mode antenna operation. When receiving difference signals, the unit provides anti-phase restructured signals for differential-mode antenna operation. The signal routing circuit may be implemented as a rat-race coupler with transmission line segments or as discrete circuit elements including inductors and capacitors. An RF communication system incorporates the signal restructure unit with digital processing circuits, transceivers, and antennas to achieve MIMO operation from a single antenna structure. The system provides improved isolation while reducing the antenna size. The restructure unit enables reconfigurable MIMO operation with enhanced performance for wireless communication applications.

The invention discloses a programmable electrical interconnection neural information detection regulation and control microsystem and method, and belongs to the technical field of neuroscience and biomedical engineering. The system comprises a partitioned in-vitro neural chip, an electrical stimulation module, a multi-channel neural signal acquisition module, an electrical interconnection control module and an upper computer module. The partitioned in-vitro nerve chip is manufactured based on an MEMS (Micro Electro Mechanical System) process and supports partitioned culture of in-vitro nerve cells; the electrical stimulation module can generate multi-channel nanoampere-to-milliampere bidirectional constant-current pulses to realize accurate nerve regulation and control; the multi-channel neural signal acquisition module is provided with a low-noise amplifier array and is used for acquiring and converting multi-channel neural signals in real time; the electric interconnection control module realizes dynamic signal routing between partitions through the switch array; the upper computer module provides parameter configuration, signal processing and visual interaction functions. The system has the advantages of high integration level, high precision, programmability, real-time regulation and control and the like, and is suitable for in-vitro brain-computer interface and neural network function research.

A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts with a first average pitch, a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts with a second average pitch, and a signal routing structure between the first and second semiconductor devices and including a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a pattern of parallel conductive lines between the first and second pluralities of conductive structures. The pattern of parallel conductive lines has a third average pitch less than the first and second average pitches, and pairs of conductive structures from the first and second pluralities are electrically coupled by different ones of the parallel conductive lines.

The invention discloses a debugging system and method for RISC-V and FPGA system-on-chip. The system comprises a control module, a multiplexer, a debugging module and a JTAG interface, and the debugging module comprises an RISC-V DAP submodule and an FPGA TAP submodule; the control module is used for acquiring a debugging mode and sending a corresponding debugging link configuration instruction to the multiplexer; the multiplexer is used for configuring signal routing paths of the two submodules so as to form a debugging link; the RISC-V DAP submodule is used for debugging the debugging command and generating a debugging result when the debugging link routes the debugging command to the submodule to carry out RISC-V debugging; and the FPGA TAP submodule is used for debugging the debugging command and generating a debugging result when the debugging link routes the debugging command to the submodule to debug the FPGA. Therefore, by configuring different signal routing paths, construction of different signal debugging links is realized, support for multiple debugging modes is realized, and the debugging flexibility is improved.

Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

Embodiments herein relate to systems, devices, techniques, or processes for forming a bridge PCB within one or more metal layers of a main PCB. The bridge PCB, which can be fabricated using mSAP techniques, can be formed between the first and second metal layers of the main PCB and can be used for high-speed signal routing between two dies, such as a system-on-chip die and a memory die, located on the main PCB and coupled by the bridge PCB. Further embodiments may be described and / or claimed.

Semiconductor devices having redistribution structures and related systems and methods are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be located between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be changed based on a location of the interconnect structure.

The invention relates to the technical field of vehicle electronic and electrical architecture, in particular to a routing configuration method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring signal routing mapping information and message routing mapping information based on a preset communication matrix; constructing a target mapping relation between a preset communication matrix element and a preset protocol stack configuration element based on the signal reason mapping information and the message route mapping information; and based on the target mapping relationship, generating configuration information of a signal route in a preset communication layer, and / or generating configuration information of a message route in a preset message layer. Therefore, the routing relationship in the preset communication matrix is automatically scanned, and the mapping relationship between the routing relationship scanned in the communication matrix and the configuration elements defined in the communication protocol stack of the configuration tool is constructed, so that the problems of long time consumption, easiness in making mistakes, difficulty in maintenance and the like existing in a traditional manual configuration mode are solved; the routing configuration efficiency is effectively improved; and the configuration accuracy is remarkably improved.

A die is described. The die includes a first seal ring on a periphery of the die, which encloses a core of the die. The die also includes one or more bridge interconnect structures across the first seal ring to route a signal from a test pad outside of the first seal ring to a circuit in the core.

The application discloses a general IOMUX architecture and a configuration control method, and belongs to the technical field of input / output multiplexers.The architecture comprises a port management module, a signal routing module, a configuration control module, a protocol adaptation module and a state monitoring module; the configuration control module adopts a composite configuration mechanism combining static and dynamic modes, receives external configuration instructions, parses the external configuration instructions into configuration parameters of each module, sends the configuration parameters to each module, and stores and dynamically updates the configuration parameters; the protocol adaptation module adopts a two-stage adaptation structure of protocol analysis and timing adjustment to adapt the output signals of the internal functional modules of chips of different communication protocols, so that the protocol requirements of external equipment are met.The application can flexibly adapt to the differentiated requirements of different chip types through modular architecture design; when applied to a new chip, a developer only needs to adjust the configuration parameters, and does not need to modify the internal core logic of each module.