28 results about "Crossbar switch" patented technology

A device includes digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The analog crossbars are operable to dynamically adjust equalization settings based on real-time feedback from DSPs, physical media-dependent (PMD) devices, or environmental sensors. Equalization adjustments optimize signal quality by compensating for traffic conditions, environmental changes, or signal degradation. The crossbars support predictive equalization using machine learning algorithms to preemptively adjust signal properties, ensuring performance across dynamic network environments. Diagnostics and logging capabilities monitor and refine equalization performance, while auxiliary in-band channels provide low-power pathways to reduce energy consumption. These features enable efficient, high-speed data transmission with enhanced reliability and adaptability in modern networking systems.

A device includes a plurality of digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The DSPs and crossbars dynamically adjust power consumption based on traffic load and / or a signal quality, leveraging traffic prediction models to optimize resource allocation. The system supports features such as powering down unused lanes, asymmetrically deactivating transmission or receiving lanes, and preemptively scaling resources during predicted traffic increases. Dynamic voltage and frequency scaling (DVFS) optimizes power usage based on link utilization and traffic priority, minimizing latency impacts during transitions. The switch controller integrates traffic prioritization algorithms, including weighted round-robin (WRR), to allocate power and bandwidth efficiently to high-priority traffic flows. Redundant crossbars handle overflow traffic or failover scenarios, transitioning between standby and active states dynamically.

Embodiments of the present disclosure relate to an unaligned memory access in a neural processor circuit. The neural processor circuit includes a crossbar circuit and a neural engine circuit coupled to the crossbar circuit. During each operating cycle of the neural processor circuit, the crossbar circuit receives a portion of input data, and re-aligns or bypasses the portion of input data. The neural engine circuit receives at least a portion of the re-aligned or bypassed portion of the input data, and performs a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.

The application relates to the technical field of hash operation, and discloses a hash operation method for guaranteeing terminal security, which comprises the following steps: arranging a two-dimensional cross switch matrix composed of controlled switch tubes in a hash operation processing unit to construct a full-connection wiring grid; collecting an initial disturbance seed and an operation intermediate state; mapping the initial disturbance seed and the operation intermediate state into wiring constraints by using a path searching logic to generate a transient wiring topology in the full-connection wiring grid; establishing a unique physical path of a current period in the two-dimensional cross switch matrix; and realizing hash compression processing through the unique physical path. The application realizes operation logic and circuit path decoupling through a transiently changed physical path, makes side channel signals present spatial random distribution, blocks an attacker from establishing statistical association through a fixed power consumption model, and guarantees terminal data security.

The present application relates to the technical field of data cleaning, and more particularly to a stream data cleaning accelerator based on FPGA, which comprises a coarse-grained reconfigurable array cleaning pipeline arranged in a programmable logic region of an FPGA chip and comprising a plurality of processing units; each processing unit is internally provided with an arithmetic logic operation core, a local register stack, a crossbar router and an instruction buffer; a configuration controller is used to issue function configuration instructions to each processing unit in the coarse-grained reconfigurable array cleaning pipeline; a quantitative perception stream neighbor interpolation engine; an interpolation value generation module is used to generate interpolation values according to a precise neighbor set; and a data interface is used to receive original data streams to be cleaned and output cleaned data records. The problems of insufficient throughput of traditional data cleaning schemes and excessively high computational complexity of K-neighbor interpolation methods are effectively solved.

The present description concerns a circuit configured to perform a multiplication between first and second values each comprising up to a number N of chunks of n bits, comprising: a number NMUL of multiplier sub-circuits configured to generate partial products corresponding to a multiplication between one chunk of the first value and one chunk of the second value; an adder part configured to generate an intermediate sum, corresponding to the addition of partial products of same significance, and excess bit values; an input crossbar circuit configured to select at least one chunk of the first value and at least one chunk of the second value and to provide them to one of the multiplier sub-circuits; a control unit configured to indicate which chunks to supply to which multiplier sub-circuit; and a parallel adder configured to generate a value corresponding to the product.

A device includes a plurality of digital signal processors (DSPs), analog crossbars in communication with the DSPs, and a switch controller. The switch controller facilitates control signals using in-band signaling within payload traffic or out-of-band signaling over a dedicated management interface. The system supports dynamic traffic prioritization based on real-time metrics, such as latency and traffic load, ensuring efficient resource allocation and seamless operation during congestion or reconfiguration. Redundant crossbars and failover mechanisms enhance fault tolerance, while granular backpressure selectively throttles traffic flows to prevent bottlenecks. Integrated diagnostic tools monitor performance and optimize traffic flow, enabling high-speed and reliable communication.

Systems and methods for seamless network communication reconfiguration, comprising a device that includes physical media dependent (PMD) devices, incorporating a digital signal processor (DSP) configured to handle both in-band and out-of-band communication traffic, a plurality of primary analog crossbars connected to the DSPs for routing operational data, and a set of redundant analog crossbars configured to establish auxiliary communication channels. The system includes a controller operable to dynamically activate the auxiliary communication channels during reconfiguration events, enabling a make-before-break protocol by transitioning traffic from primary channels to auxiliary channels. The redundant crossbars support out-of-band signaling to coordinate transitions and maintain system integrity. The auxiliary channels remain in a low-power state during steady operation, ensuring resource efficiency, while the controller monitors signal integrity and initiates reconfiguration upon detecting a fault or network event, maintaining uninterrupted traffic flow.

The application provides a switched capacitor circuit and a control method thereof. The switched capacitor circuit comprises an input terminal, an output terminal, a first phase circuit, a second phase circuit, and a charge pump formed by an inter-phase coupling circuit. The first phase circuit and the second phase circuit each comprise two-stage flying capacitors and a plurality of switching tubes, which are respectively connected to the input terminal, the output terminal, and a reference ground through the switching tubes. The inter-phase coupling circuit comprises two cross switching tubes, which cross-connect the plate of the first-stage flying capacitor of one phase and the plate of the second-stage flying capacitor of another phase. By controlling the conduction state of each switching tube, at least two different voltage conversion ratios are output. The embodiment of the application realizes the voltage conversion output of multiple ratios by the cross-coupled two-phase two-stage charge pump structure with a small number of switching tubes, reduces the voltage stress of the flying capacitor, simplifies the control logic, and reduces the cost of the charging scheme.

A wireless device operates in a first mode by configuring a cross-switch to establish a first signal path from a Frequency Range 3 (FR3) antenna element to a transceiver through a shared interconnect. The wireless device operates in a second mode by configuring the cross-switch to establish a second signal path from a Frequency Range 2 (FR2) module to the transceiver through the shared interconnect. The FR2 module outputs FR2 intermediate frequency (IF) signals. The wireless device transmits and receives signals through the shared interconnect in a non-concurrent manner between the first mode and the second mode.

The application discloses a medical terminal trusted authentication method based on a physically unclonable function and relates to the technical field of terminal trusted authentication. The method comprises the following steps: a medical terminal receives a reference challenge vector and synchronously collects a physiological electrical signal and a body temperature plaintext; a dynamic internal mask is extracted from the least significant bit of a continuous sampling window to generate thermal shot noise and a degradation flag is output; a cross switch network is driven by the dynamic internal mask to perform same-weight bit shuffling, a transient challenge vector is formed, an SRAM-PUF is injected to obtain a noisy initial response, and the noisy initial response, the body temperature plaintext and the degradation flag are reported; then, a verification server performs thermal compensation on a digital twin baseline according to the body temperature plaintext to generate a predicted response and a contraction coefficient; finally, the tolerance threshold is tightened according to the contraction coefficient, blind search comparison is completed in a limited reverse de-shuffling space, and when the degradation flag is valid, the method is switched to a static mask isolation area to perform physical fuse verification.

Techniques are provided for noise and bound management for DNN training on an RPU crossbar array using a worst-case based scaling factor. A method for noise and bound management includes obtaining an input vector value x of an analog crossbar array of an RPU device, where a weight matrix is mapped to the analog crossbar array of the RPU device, and scaling the input vector value x based on a worst case to provide a scaled input vector value x' to use as an input to the analog crossbar array of the RPU device, where the worst case includes a sum of an assumed maximum weight of the weight matrix multiplied by an absolute value from the input vector value x.

A system and method for hardware-interlocked identity succession utilize a hardware-rooted integrity sentinel and an analog audit engine to enforce state integrity in a 2 nm-class semiconductor. Voltage anomalies are detected via continuous-time monitoring using a differential propagation delay interferometer and an asynchronous glitch latch, and enforcement is applied by an analog impedance modulation network physically interposed on a processor signature-enable line. A vertical-stack inductive gradient sensor integrated within a BSPDN stack detects backside tamper via mutual inductance changes. An analog memristive crossbar audit engine performs stochastic challenge-response scoring, and a thermal-security via lattice stabilizes the audit engine while also providing a parallel discharge path for termination. Identity transfer is controlled by a hardware-interlocked state machine with a deadman timer that triggers zeroization absent a physical acknowledgment signal.

This invention belongs to the field of PCIe switching chips and relates to a PCIe packet aggregation and switching method and apparatus. The apparatus includes a PCIe ingress port, an ingress aggregation module, a crossbar switch, an egress deaggregation module, and a PCIe egress port. The ingress aggregation module is used to filter and match multiple received TLPs according to preset aggregation conditions to determine whether they meet the aggregation requirements. The crossbar switch is used to receive CTLPs or independent TLPs sent by the ingress aggregation module and forward them to the corresponding egress deaggregation module according to the destination port of the packet. The egress deaggregation module is used to receive packets forwarded by the crossbar switch and determine whether they are CTLPs or independent TLPs. This invention significantly improves bandwidth utilization, significantly reduces transmission latency, has excellent compatibility, low implementation cost, high reliability, and strong universality.

This disclosure provides a shared memory interconnect device, arbitration method, and arbitration circuit, relating to the field of integrated circuit interconnect technology. The implementation scheme is as follows: a hierarchical interconnect network includes an outer routing network and an inner switching network. The outer routing network includes a multi-level switching network composed of multiple butterfly switching units, used to route data stream packets from input ports to multiple subgroups of the inner switching network. The inner switching network includes multiple crossbar switching modules for performing local non-blocking switching. An arbitration module maintains the weights of each input port and determines the arbitration result based on the weights between conflicting ports. When arbitration fails, the weight of the corresponding port is incremented by a preset increment. When arbitration succeeds, the weight of the corresponding port is restored to its initial value. The arbitration result of each port is determined by cascading the arbitration status between conflicting ports, which can significantly reduce hardware area overhead while ensuring local bandwidth and low latency.

This invention discloses a configurable routing distribution method for SSD controller command processing, belonging to the field of solid-state drive technology. The method includes: setting up a BXM module in the SSD controller; the BXM module includes an interface module, a two-layer routing table, a FIFO queue, processing nodes, and a crossbar switch; receiving commands through the host interface and generating data packets containing headers and payloads; the BXM module querying the two-layer routing table based on the operation reference field in the data packet header to determine the target engine and operation instructions; routing the data packets to the target engine for processing via the crossbar switch; repeating the routing and processing steps until all operation processes are completed and the final engine terminates processing, and the data packets are no longer forwarded. This invention uses the BXM module for routing, replacing traditional CPU-centralized processing, significantly reducing command processing latency and improving system energy efficiency.

A device may include a plurality of digital signal processors (DSPs) and a plurality of analog crossbars connected to the DSPs. A microcontroller unit may be operable to facilitate network isolation.

The application relates to a high-integration-gate resistive memory and a preparation method thereof, and belongs to the technical field of microelectronic devices. The gate resistive memory comprises a MOSFET transistor and a ferroelectric tunnel junction. The MOSFET transistor and the ferroelectric tunnel junction both comprise a first common electrode, a second common electrode, a common semiconductor layer, a first graphene layer and a second graphene layer. The high-integration-gate resistive memory and the preparation method thereof combine the MOSFET transistor and the ferroelectric tunnel junction, have the ability to inhibit the bypass current of the cross-switch matrix array, and have the characteristics of high switching speed, non-volatility, low power consumption, high expandability and compatibility with the CMOS process. In addition, the high-integration-gate resistive memory and the preparation method thereof omit the source metal electrode of the MOSFET transistor, directly use the semiconductor source end extension part of the MOSFET transistor as one end of the ferroelectric tunnel junction, can fully realize the 1T1R storage function, and greatly improve the integration of the device.

An electronic device and an operating method thereof are provided. The electronic device can include a crossbar array including a plurality of first memory cells, a plurality of second memory cells, a plurality of row lines, a plurality of first column lines, and a second column line, and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage. Each of the plurality of analog-to-digital converters determines an allowed maximum value of an analog signal voltage based on the reference voltage.

Technology for a device includes a plurality of digital signal processors (DSPs) and a plurality of analog crossbars in communication with the DSPs. The DSPs dynamically adjust queues to optimize data flow based on traffic conditions, latency, and resource availability. Queues may include input queues, output queues, virtual output queues, or hybrid configurations, supporting techniques such as priority scheduling and time-division multiplexing (TDM). The DSPs facilitate flow control through granular backpressure signaling, managing congestion between DSPs and endpoints. Synchronization of queues during crossbar reconfiguration ensures seamless traffic flow and prevents data loss. Advanced mechanisms, such as dynamic queue depth adjustment and adaptive prioritization, enable efficient resource sharing while maintaining high throughput. The device leverages these features to provide scalable, energy-efficient networking solutions for complex environments, such as data centers and telecommunication system

The application discloses a signal transmission method and device, a storage medium and a product, and relates to the technical field of communication. When a signal is transmitted from a sending end to a receiving end, link quality information of a first transmission channel and a second transmission channel is detected. Based on the link quality information, a first link quality score in a first transmission mode and a second link quality score in a second transmission mode are respectively calculated. Based on the first link quality score and the second link quality score, a target transmission mode is determined, with the target being to preferentially allocate a first signal to a transmission mode with a higher link quality score. A high-speed cross-over switch matrix is controlled to transmit the first signal and the second signal according to the target transmission mode. By dynamically detecting the quality difference between the two channels and quantifying the scores, the first signal is adaptively switched to a better channel. The defects of the prior art fixed mapping, which cannot utilize the quality difference between the channels, are overcome, and the transmission performance and transmission efficiency of high-speed data signals in long-distance transmission are significantly improved.

A device may include a processor operable to process one or more of layer 2(L2) or layer 3 (L3) protocols in which the processor includes handling of one or more of frame headers, frame boundaries, media access control (MAC) addresses, or internet protocol (IP) addresses. The device may have a MAC address and an IP address associated with the device. The device may be operable to receive and process data packets addressed to the MAC or the IP address of the device. The device may be operable to interface with layer 1(L1) devices, including layer 1 systems and physical transceivers (PHYs).

A stacked memory device comprises a stack of dies including a base die comprising interface logic and a set of memory dies including memory banks. The interface logic includes a host-side interface to a host device that communicates packetized serial commands and data, an interconnect, and a set of memory controllers corresponding to respective memory channels. The host-side interface may include one or more independent serial links including at least one command link, at least one response link, and at least one data link. The memory controllers operate in parallel to receive the packetized commands and perform memory operations with respect to the memory banks. The interconnect may comprise a full crossbar switch that enables switching between any of the serial links of the host-side interface and any of the memory channels controlled by the respective memory controllers.

A device includes a plurality of digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The analog crossbars dynamically switch between multiple inputs and outputs and adjust configurations based on real-time feedback from the DSPs. The crossbars use amplification to enhance signal strength at input and output stages, ensuring signal integrity across long transmission paths or during multicasting and broadcasting operations. Real-time adaptive equalization optimizes performance in response to environmental changes or signal degradation. The crossbars facilitate system management traffic through out-of-band signaling and support failover with redundant paths to maintain communication during failures. Synchronization with DSPs or a switch controller is achieved through shared clock signals or IEEE 1588. These features enable efficient, high-speed data transmission while maintaining robust performance and reliability in dynamic network environments.

This disclosure relates to LC distributed matching for balancing the RF performance of cross switches. For example, a method of manufacturing an RF switch is provided, comprising: adding a first mutual inductance portion of a first transmission line to a first self-inductance portion; and adding a second mutual inductance portion of a second transmission line to a second self-inductance portion, wherein the values ​​of the first and second mutual inductance portions and the values ​​of the first and second self-inductance portions balance the impedance difference between the first and second transmission lines.

Technology for a device used for time division multiplexing is disclosed. The device may include a plurality of digital signal processors (DSPs). The device may include a plurality of analog crossbars operable to be connected to the plurality of DSPs. The plurality of analog crossbars may be operable to: receive, at one or more input ports of the plurality of analog crossbars, input data from the plurality of DSPs; and send, from an output port of the plurality of analog crossbars, time-division multiplexed (TDM) output data.

The application discloses a heterogeneous computing system and method of a computer, and relates to the technical field of supercomputers, wherein the heterogeneous computing system of the computer comprises: a register unit, which is used for determining a computing core and a target configuration register corresponding to the computing core based on a physical address of to-be-computed data corresponding to a heterogeneous computing task of a processor device, and allocating the to-be-computed data to the target configuration register; and a data read-write unit, which is used for allocating the to-be-computed data to a corresponding memory layer in a plurality of memory layers through a first cross switch based on the target configuration register, so as to drive a computing unit to execute a computing task according to the to-be-computed data corresponding to the plurality of memory layers. The problems of large data transmission delay and low memory utilization of a heterogeneous acceleration system in the prior art are solved, the technical effects of fully utilizing memory resources in a heterogeneous platform, improving the performance of data transmission between different computing units, and reducing the delay of data movement are achieved.

Technology for a device is disclosed. The device may include a plurality of digital signal processors (DSPs). The device may include a plurality of analog crossbars operable to be connected to the plurality of DSPs. The device may include a set of redundant analog crossbars operable to be connected to the plurality of DSPs. The set of redundant analog crossbars may be operable to provide one or more of additional input lanes or additional output lanes when failover occurs.