140 results about "Crossbar switch" patented technology

The invention discloses a multi-level interconnection network based on real-time flow monitoring and dynamic priority adjustment. A multi-dimensional traffic sensing model is constructed through traffic intensity, queue depth, congestion signals and static priority dynamic indexes. A dynamic urgency value is generated by adopting a configurable weighting strategy, and a three-mode closed-loop optimization mechanism is designed. A layered interconnection structure is adopted, crossbar switches are used in computing clusters, and the computing clusters are connected through a low-diameter routing network. In a cluster gateway, a dynamic arbitration unit monitors the flow intensity in real time, calculates the urgency degree in combination with a queue state and a global congestion signal, and dynamically selects a fixed priority and a weighted polling or polling arbitration strategy. The problem that the resource utilization rate of a traditional static arbitration mechanism is reduced due to task switching is effectively solved, the risk of fairness imbalance in a mixed key data flow scene is effectively solved, and the communication adaptation capacity of a reconfigurable architecture to diversified computing loads is improved.

A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

The invention relates to the technical field of network communication, in particular to an intelligent network card data forwarding method and system based on an FPGA, and the method comprises the steps: after the FPGA receives a data stream, firstly extracting a time interval standard deviation of N data packets as a time feature, executing parallel hash operation on a source IP address and a destination IP address, and mapping the source IP address and the destination IP address into three-dimensional coordinates; splicing the time features and the space coordinates into a two-dimensional matrix; a time vector T and a space vector S are separated from the two-dimensional matrix, the time feature similarity is calculated through cosine similarity, the space similarity is calculated through an Euclidean distance normalization algorithm, and affinity is obtained after weighted fusion; the condition that the affinity exceeds a first preset threshold value is used as a triggering condition for micro-flow slice splitting, and a data label is added to the slice; the FPGA intelligent network card implements heterogeneous channel binding based on slice affinity, and the global crossbar switch realizes non-blocking channel switching according to priority. And the slice splitting is triggered according to the affinity threshold, so that the high-speed transmission efficiency is improved.

The invention discloses a crossbar switch control method based on cache information exchange, which relates to the technical field of integrated circuits and high-speed interconnection, and comprises an outlet flow control waterline register, an outlet congestion waterline register and a dequeue strategy optimization control register of an inlet receiving module in initialization configuration center control; the cache occupation amount of each outlet is monitored in real time, when the outlet cache is in an early warning state, an inlet dequeue strategy is controlled, and outlet data messages in a non-early warning state are scheduled preferentially; the cache occupation and release information is interacted in real time, and the early warning state is updated through the change of an occupation amount register; and dynamically optimizing an entrance dequeue sequence based on an exit cache early warning state, and performing decentralized flow cooperative control. The problem of performance loss of a traditional Crossbar switching chip caused by outlet bottleneck is effectively solved, and a high-performance and high-reliability switching chip technical scheme is provided for the fields of data center lossless interconnection, 5G core network packet switching and the like.

A sliced router decomposes a router into a plurality of slices. Each slice has a subset of the input and output ports of the router. One or more of the slices may communicate with a network access point. Adjacent slices communicate with each other. In some example embodiments, there are dedicated physical channels between each slice and each adjacent slice for traffic coming in on or going out on ports of other slices. Within a slice, traffic may be arbitrated onto upstream or downstream channels going to the same output port. Each slice contains one or more crossbars, allowing data received on any input port to be routed to any output port of the slice. The crossbar of each slice is substantially smaller than the crossbar that would be used by a unified router.

An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.

The invention provides a 1S1R storage unit and a preparation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. In the preparation process of the method, the preparation device comprising the first electrode layer, the gate layer and the buffer layer is subjected to annealing process treatment, so that the gate layer and the buffer layer are crystallized, after the gate layer is crystallized, the Forming voltage can be reduced, the threshold transformation characteristic yield of the device is improved, a protruding nanocrystalline interface is formed on the surface due to the crystallization of the buffer layer, and the yield of the device is improved. And meanwhile, local field intensity is also increased by a nanocrystalline interface, so that conductive filaments of the resistive layer are robust, the positions of the formed conductive filaments of the resistive layer have a certain rule, the randomness of the generation positions of the conductive filaments is reduced, and the uniformity of electrical properties is improved. The 1S1R unit structure is not only suitable for a 1S1R array of a Crossbar structure, but also suitable for a 1S1R array of a vertical structure after being properly modified, and has a wide application prospect.

The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) in crossbar circuits. The processing device may perform a programming process to program a resistive random access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

The invention relates to the technical field of communication network operation and maintenance management, and discloses a communication network reliability assessment method based on big data analysis, which comprises the following steps of: 1, connecting a communication network, a bit error tester, a NetFlow analyzer and a spectrum analyzer through a network to obtain detection data of communication equipment, classifying to form a cross data set, a routing data set and a gateway data set; 2, evaluating the communication state of each crossbar switch according to the crossbar data set, and generating an exchange score; 3, evaluating the communication state of each router according to the routing data set, and generating a forwarding score; step 4, evaluating the communication state of each gateway according to the gateway data set, generating a packaging score, and realizing high multi-dimensional evaluation precision; and step 5, comprehensively evaluating the reliability of the communication network according to the exchange score, the forwarding score and the packaging score, and outputting corresponding evaluation results and optimization suggestions, thereby realizing automatic decision support and preventive maintenance, and being high in intelligent management communication stability.

An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.

The application provides a configurable cross switch circuit and a convolution operation circuit based on the same, the configurable cross switch circuit comprising a read cross switch array in front of an operation unit array and a write cross switch array in front of the operation unit array; input feature maps are introduced into an input memory stack, input into the operation unit array through the read cross switch array, and output feature maps calculated by the operation unit array are written into an output memory stack through the write cross switch; in each cycle, at most only one switch is closed for the same column read switch and the same row write switch. The two-dimensional convolution operation circuit based on the application only needs to introduce the input feature map data into the on-chip memory once, and the two-dimensional convolution operation can be completed, without the need of repeatedly introducing the input feature map data into the memory or transmitting the input feature map data between the memories, so that the performance of the two-dimensional convolution calculation is improved and the energy consumption is reduced.

The invention discloses a shared hardware interface for optimizing crossbar switches, and particularly discloses an apparatus comprising crossbar switch circuitry that routes one or more packets between one or more ingress nodes and one or more egress nodes. The plurality of ingress nodes share a shared hardware interface. The shared hardware interface includes a pool of hardware interfaces, and the plurality of ingress nodes share the pool of hardware interfaces.

The invention provides an artificial intelligence chip and an operation method thereof. The artificial intelligence chip comprises an on-chip network and a core cluster. The core cluster includes a plurality of artificial intelligence cores, a crossbar circuit, and a producer data buffer circuit. The artificial intelligence cores jointly execute the program core. The crossbar circuit transmits a data write request to the network-on-chip to the producer data buffer circuit, wherein the data write request is to be sent to the network-on-chip by an artificial intelligence core as a producer. The producer data buffer circuit temporarily stores calculation data carried by the data write request to be used as an artificial intelligence core of a consumer. The crossbar circuit transmits a data read request to the network-on-chip as an artificial intelligence core of a consumer to the producer data buffer circuit. And the producer data buffer circuit transmits calculation data corresponding to the data reading request back to the artificial intelligence core serving as the consumer.

A chip architecture and system design for accelerating neural network computation is disclosed. The chip includes a plurality of cores interconnected via a ring-shaped network-on-chip (NoC), each core comprising a 2D mesh of processing elements (PEs) with hierarchical software-and hardware-based schedulers. Each PE includes specialized compute engines, local memory, and dynamic precision conversion logic. The architecture supports flexible instruction dispatch, scalable memory access, and runtime scheduling optimization. The chip can be deployed in chiplet-based configurations, PCIe cards with paired chips, or modular OAM cards with single-chip packaging. Multi-card systems utilize crossbar switch fabrics and direct inter-card links to enable efficient, low-latency communication and high-bandwidth scalability.

The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

An integrated circuit device includes interconnect circuitry. The interconnect circuit includes an interleaving switch circuit, a network switch circuit, and a crossbar switch circuit. The interleaved switch circuits are coupled to a requester device. The first interleaved switch circuit includes a first port. The first interleaving switch circuit receives a first memory command and outputs the first memory command via a first communication path connected to the first port based on a memory address of the first memory command. The network switching circuits are connected to the interleaving switching circuits. A first network switch circuit is connected to the first communication paths and routes first memory commands along the first communication paths based on memory addresses. A first crossbar circuit of the crossbar circuits receives a first memory command from the first communication paths and outputs the first memory command to a first memory device of the memory devices associated with the memory.

The invention relates to the field of electronic communication, and provides a dual-redundancy system switching method, system and device based on an FPGA and a storage medium. The method comprises the following steps: verifying transmission data of a main channel in real time to obtain health state information of the main channel; writing the channel state data of the main channel into a shared memory, and synchronously updating the channel state data of the standby channel through a state mirror image engine to obtain state mirror image data; generating a channel switching trigger signal according to the health state information of the main channel, inputting the channel switching trigger signal into a switching controller, and controlling routing selection of a crossbar switch by the switching controller to obtain a channel switching instruction; and switching the data transmission path from the main channel to the standby channel according to the channel switching instruction, and loading the transmission serial number and the FIFO pointer state to the standby channel from the state mirror image data to obtain the recovered data transmission service. According to the invention, seamless switching of the dual-redundancy system is realized, and high availability of the system is guaranteed.

Described herein are techniques to enable tracking circuits for crossbar circuits. One embodiment provides an apparatus including a crossbar array comprising: a plurality of bit lines intersecting with a plurality of word lines; and a plurality of cross-point devices, wherein each of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines; a read-out circuit selectively connected to at least one of the bit lines, wherein the read-out circuit is to generate an output representative of the memristor conductance; a tracking circuit comprising a first replica cell that emulates at least one of the cross-point devices, wherein the tracking circuit is to produce a reference voltage; and a converter configured to convert the output of the read-out circuit into a digital output or a pulse-width-modulated signal, wherein the reference voltage is provided to the converter as an input.

Systems and methods for modulating conductance of a plurality of unit cells are described. The controller may determine a plurality of conductance values for a plurality of unit cells arranged in the crossbar arrangement. The plurality of unit cells may include non-volatile memory devices. The plurality of conductance values may be less than a maximum conductance value of the plurality of unit cells. The controller may determine a read gate voltage for driving the plurality of access transistors to read from the plurality of unit cells. The controller may map the plurality of weights to a plurality of conductance values and a read gate voltage.

A device includes digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The analog crossbars are operable to dynamically adjust equalization settings based on real-time feedback from DSPs, physical media-dependent (PMD) devices, or environmental sensors. Equalization adjustments optimize signal quality by compensating for traffic conditions, environmental changes, or signal degradation. The crossbars support predictive equalization using machine learning algorithms to preemptively adjust signal properties, ensuring performance across dynamic network environments. Diagnostics and logging capabilities monitor and refine equalization performance, while auxiliary in-band channels provide low-power pathways to reduce energy consumption. These features enable efficient, high-speed data transmission with enhanced reliability and adaptability in modern networking systems.

This invention discloses a parallel situational gravity calculation chip and method based on in-memory computing, belonging to the field of artificial intelligence chips and analog in-memory computing technology. The chip includes: an event polarity input unit, which converts externally input event information loads (six-dimensional polarity vectors) into analog voltage signals; a situational reference storage array, employing a memristor cross-switch array, with each row storing a six-dimensional binary encoded vector of a reference situational type (such as the 64 hexagrams); a parallel gravity calculation unit, which performs large-scale parallel multiply-accumulate operations simultaneously in the analog domain, following the gravity calculation rule of "like lines cooperate, dissimilar lines repel," generating a multi-dimensional gravity intensity distribution; and a gravity readout and post-processing unit, which converts the gravity distribution into situational awareness results and outputs them. This invention adopts an in-memory computing architecture, eliminating the "memory wall" bottleneck of the traditional von Neumann architecture, achieving nanosecond-level fully parallel gravity calculation and ultra-low power consumption operation. It can be deployed as an independent situational awareness processor at sensor terminals, IoT terminals, and wearable devices.

An optoelectrical package may include at least one electrical switch application-specific integrated circuit (ASIC) and at least one optical engine. The electrical ASIC may be disposed at a central portion of a communication interface. The electrical ASIC may incorporate a crossbar functionality. The optical engine may be arranged relative to the communication interface. The optical engine may be electrically connected to the at least one electrical ASIC. The optical engine may be disposed adjacent to the at least one electrical ASIC. The optical engine may include a fiber connector for one or more fibers, a photonic integrated circuit, and an electronic integrated circuit. The optical engine may be configured to convert an optical signal obtained from the fiber connector to an electrical signal for use by the electrical ASIC and vice versa.

The invention relates to the technical field of on-chip communication, in particular to a multicast AXI crossbar switch design method and device adaptive to an ML accelerator, a host initiates AXI transmission, slaves respond to the AXI transmission, in a multicast task, a write request of the host is distributed to a plurality of slaves, each host interface is connected to an AXID Demux module for write request splitting, and the write request is transmitted to the host interface through the AXI Demux module. Each slave interface is connected to an AXIMux module so as to be connected with different AXI hosts; the whole crossbar switch is configured with an address mapping table Address Map, a complete address space is divided into a plurality of address intervals, and each address space is mapped to one slave; when a host initiates a write request, a target address is compared with an address mapping rule in an address mapping table, so that the request is matched to a corresponding slave, an AXI related bus signal is transmitted to the corresponding slave in an original mode, and only AW, W and B channels of the AXI are involved for multicast transactions. Compared with the prior art, the method has the advantages that the performance can be ensured, the transmission efficiency is remarkably improved, the multicast function is supported, and the power consumption delay overhead is controlled within an acceptable range.

A device includes a plurality of digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The DSPs and crossbars dynamically adjust power consumption based on traffic load and / or a signal quality, leveraging traffic prediction models to optimize resource allocation. The system supports features such as powering down unused lanes, asymmetrically deactivating transmission or receiving lanes, and preemptively scaling resources during predicted traffic increases. Dynamic voltage and frequency scaling (DVFS) optimizes power usage based on link utilization and traffic priority, minimizing latency impacts during transitions. The switch controller integrates traffic prioritization algorithms, including weighted round-robin (WRR), to allocate power and bandwidth efficiently to high-priority traffic flows. Redundant crossbars handle overflow traffic or failover scenarios, transitioning between standby and active states dynamically.

Embodiments of the present disclosure relate to an unaligned memory access in a neural processor circuit. The neural processor circuit includes a crossbar circuit and a neural engine circuit coupled to the crossbar circuit. During each operating cycle of the neural processor circuit, the crossbar circuit receives a portion of input data, and re-aligns or bypasses the portion of input data. The neural engine circuit receives at least a portion of the re-aligned or bypassed portion of the input data, and performs a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.

The present disclosure relates to an inter- core interconnect system and a graphics card apparatus including the same. The inter- core interconnect system has at least two cores; and a crossbar matrix bus for connecting the at least two cores, wherein each of the at least two cores includes an on-chip inter- core interconnect interface for inter- core interconnect, the on-chip inter- core interconnect interface having an interface conversion module, wherein the on-chip inter- core interconnect interface converts first data and a first address into a first packet having a first custom packet format using the interface conversion module and transmits the first data and the first address in the first packet onto the crossbar matrix bus, and / or the on-chip inter- core interconnect interface receives a second packet having a second custom packet format from the crossbar matrix bus and converts the second packet into second data and a second address using the interface conversion module.

A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.

The application relates to the technical field of hash operation, and discloses a hash operation method for guaranteeing terminal security, which comprises the following steps: arranging a two-dimensional cross switch matrix composed of controlled switch tubes in a hash operation processing unit to construct a full-connection wiring grid; collecting an initial disturbance seed and an operation intermediate state; mapping the initial disturbance seed and the operation intermediate state into wiring constraints by using a path searching logic to generate a transient wiring topology in the full-connection wiring grid; establishing a unique physical path of a current period in the two-dimensional cross switch matrix; and realizing hash compression processing through the unique physical path. The application realizes operation logic and circuit path decoupling through a transiently changed physical path, makes side channel signals present spatial random distribution, blocks an attacker from establishing statistical association through a fixed power consumption model, and guarantees terminal data security.