224 results about "Crossbar switch" patented technology

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

An electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors. An electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically 5 interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101). A first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a 10 respective output for each column of memristors.

The invention discloses a dynamic bypass fault-tolerant router in a network-on-chip. The dynamic bypass fault-tolerant router comprises input and output ports, an input buffer area, a crossbar switch, a routing calculation unit, a self-checking circuit and a bypass channel. Key features comprise a fault information unit, a bypass selector, a single flit buffer area and an arbitration unit. The router detects the self-fault through the self-checking circuit, and the fault information unit stores the information. And if the router fails, the bypass selector transmits the data packet through the bypass channel and bypasses the failed router. If the router is healthy, the router exchanges fault information with an adjacent router, the fault information is used for routing decision of a data packet after integration, and meanwhile, the router can select a routing path with smaller congestion in an effective direction according to the flow distribution condition in a network. According to the method, the area overhead is relatively low, the routing hop count of the data packet is remarkably reduced, the transmission delay of the data packet is reduced while the high reliability is maintained, and the network throughput is improved.

The invention discloses a multi-level interconnection network based on real-time flow monitoring and dynamic priority adjustment. A multi-dimensional traffic sensing model is constructed through traffic intensity, queue depth, congestion signals and static priority dynamic indexes. A dynamic urgency value is generated by adopting a configurable weighting strategy, and a three-mode closed-loop optimization mechanism is designed. A layered interconnection structure is adopted, crossbar switches are used in computing clusters, and the computing clusters are connected through a low-diameter routing network. In a cluster gateway, a dynamic arbitration unit monitors the flow intensity in real time, calculates the urgency degree in combination with a queue state and a global congestion signal, and dynamically selects a fixed priority and a weighted polling or polling arbitration strategy. The problem that the resource utilization rate of a traditional static arbitration mechanism is reduced due to task switching is effectively solved, the risk of fairness imbalance in a mixed key data flow scene is effectively solved, and the communication adaptation capacity of a reconfigurable architecture to diversified computing loads is improved.

The invention provides a network-on-chip transmission information arbitration method and related equipment, and belongs to the technical field of computers, and the method comprises the following steps: determining a request to be sent by a target node in each input direction in a current round of arbitration period, and obtaining a target set; determining a weight value corresponding to each to-be-sent request in a target set according to a fault state of a node closest to a target node in a message transmission path of the target request, a space idle number of a flit size, a historical request number in the same transmission direction and a historical weight value; the historical weight value is a corresponding weight value when the target node sends each to-be-sent request in the last round of arbitration period; and sorting the to-be-sent requests in the target set according to a sequence of the weight values from high to low so as to respond to the sorted to-be-sent requests by using a crossbar switch on the target node. According to the method, the technical problem that the flow load of the network-on-chip is unbalanced in the related technology can be solved.

The embodiment of the invention provides a protocol converter and method for a network card and electronic equipment. The protocol converter comprises a protocol controller, a crossbar switch and a high-speed serial computer extension bus PCIe interface. The protocol controller is provided with a transmit-receive interface which is connected with the data node. The data node is not provided with a processor; the PCIe interface is connected with the RDMA network card and is used for transmitting data between the data node and the RDMA network card; the protocol controller further comprises a sending management unit and a receiving management unit, and the sending management unit is used for receiving data sent by the data node and sending the data to the PCIe interface through the crossbar switch in a message mechanism; and the receiving management unit is used for receiving data transmitted by the PCIe interface through the crossbar switch. By adopting the protocol converter, a data node without a processor can realize data transmission through the RDMA network card, and the data transmission rate of a common node is improved.

A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

The invention provides an intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method, and belongs to the technical field of integrated circuit design, the system is characterized in that an AXI interconnection matrix module is provided with a crossbar switch, a master port and a slave port, and the master port and the slave port are connected with the crossbar switch through an AXI bus; each router node in the 2D Mesh network module is provided with a local port and a peripheral port, and each router node is connected with an adjacent router node through the peripheral port; the intelligent clock gating module monitors the channel flow of the AXI interconnection matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls a clock signal; and the dynamic power management module adjusts the power consumption state according to the global power optimization signal and the local optimization signal. The overall power consumption of the system-on-chip is reduced, and the stability and efficiency of data transmission are enhanced.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

The invention discloses a network-on-chip fault-tolerant system based on a fault processing router and a dual fault-tolerant distributed route, and relates to the technical field of network-on-chip. The system comprises a fault processing router and a dual fault-tolerant distributed routing mechanism. The fault processing router comprises a port distribution module, a redirection FIFO module, an error correction module, a crossbar switch module, a crossbar switch bypass module and a detection master control module. The modules cooperate to realize fault isolation and path reconstruction. According to the dual fault-tolerant distributed routing mechanism, fault tolerance is realized through single fault isolation, composite fault collaboration and dynamic routing adjustment, and deadlock is avoided and network connectivity under fault topology is maximized by dynamically relaxing and forbidding a steering rule. The problems of single-point failure and composite fault accumulation caused by permanent faults of transistors of the network-on-chip are solved.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

The invention relates to the technical field of network communication, in particular to an intelligent network card data forwarding method and system based on an FPGA, and the method comprises the steps: after the FPGA receives a data stream, firstly extracting a time interval standard deviation of N data packets as a time feature, executing parallel hash operation on a source IP address and a destination IP address, and mapping the source IP address and the destination IP address into three-dimensional coordinates; splicing the time features and the space coordinates into a two-dimensional matrix; a time vector T and a space vector S are separated from the two-dimensional matrix, the time feature similarity is calculated through cosine similarity, the space similarity is calculated through an Euclidean distance normalization algorithm, and affinity is obtained after weighted fusion; the condition that the affinity exceeds a first preset threshold value is used as a triggering condition for micro-flow slice splitting, and a data label is added to the slice; the FPGA intelligent network card implements heterogeneous channel binding based on slice affinity, and the global crossbar switch realizes non-blocking channel switching according to priority. And the slice splitting is triggered according to the affinity threshold, so that the high-speed transmission efficiency is improved.

A matrix-vector multiplication device includes an input encoder that encodes an input vector into a binary complement format value and a binary true format value; a pulse generator that converts each encoded bit of the binary complement format value and each encoded bit of the binary true format value into a corresponding pulse signal; a crossbar array of weights, wherein each weight is encoded as a differential analog conductance of resistive memory devices, wherein the pulse generator simultaneously applies a pulse signal corresponding to a given encoded bit of the binary complement format value and a pulse signal corresponding to a given encoded bit of the binary true format value to corresponding resistive memory devices; an analog-to-digital converter that digitizes outputs of the crossbar array of weights to generate partial dot-product results; and a digital counter that computes a final dot-product result from the partial dot-product results.

The invention relates to the technical field of processor hardware design, and discloses an ultra-wide RISC-V long vector processor, which comprises a 64-bit scalar RISC-V core and a plurality of vector clusters, wherein each vector cluster comprises an instruction dispatcher and an instruction scheduler, the instruction dispatcher receives vector instructions sent from the scalar core and distributes the instructions to idle processing channels, and the instruction scheduler controls the execution sequence of the instructions in time; each channel is connected with the mask unit, the sliding unit and the vector read-write unit through the full-interconnection crossbar switch, and the full-interconnection crossbar switch and the mask unit carry out conditional execution on elements in a vector instruction based on the mask register. According to the method, the long vector can be quickly and efficiently calculated, the expandability problem of a full interconnection structure is solved by adopting a special layered pipeline interconnection structure, and then long vector support can be carried out on an extended vector processor architecture.

The invention discloses a crossbar switch control method based on cache information exchange, which relates to the technical field of integrated circuits and high-speed interconnection, and comprises an outlet flow control waterline register, an outlet congestion waterline register and a dequeue strategy optimization control register of an inlet receiving module in initialization configuration center control; the cache occupation amount of each outlet is monitored in real time, when the outlet cache is in an early warning state, an inlet dequeue strategy is controlled, and outlet data messages in a non-early warning state are scheduled preferentially; the cache occupation and release information is interacted in real time, and the early warning state is updated through the change of an occupation amount register; and dynamically optimizing an entrance dequeue sequence based on an exit cache early warning state, and performing decentralized flow cooperative control. The problem of performance loss of a traditional Crossbar switching chip caused by outlet bottleneck is effectively solved, and a high-performance and high-reliability switching chip technical scheme is provided for the fields of data center lossless interconnection, 5G core network packet switching and the like.

The invention discloses a request access method and system for avoiding access conflicts in a period. The system comprises a plurality of request modules, a front-end processing module, a crossbar switch and a plurality of cache blocks, the plurality of request modules are used for sending access requests; the front-end processing module is used for carrying out duplicate removal processing on requests from the plurality of request modules in a period; the crossbar switch is used for dividing an address space requested to be accessed into non-overlapped address intervals, and respectively outputting requests corresponding to different address intervals according to addresses to be accessed by the requests subjected to duplicate removal processing; each cache block corresponds to a different address interval and is used for responding to a request of the corresponding address interval. According to the method, when the same address or address interval is repeatedly accessed in one period, the number of cache blocks can be remarkably reduced, and access conflicts and request stagnation can be avoided.

The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

Combined charging / discharging circuit with an energy storage terminal (A+, A-), an energy source terminal (PE, NE), a resistor (R), a series switch (L), a cross-switch (Q), and a controller (C) which is drivingly connected to the series switch (L) and to the cross-switch (Q), which together are designed as a changeover switch, wherein the resistor (R) connects a first potential (A+) of the energy storage terminal to a connection point (P) at which the series switch (L) and the cross-switch (Q) are connected to one another, the series switch (L) in a pre-charging state connects the resistor (R) to a first potential (PE) of the energy source terminal (PE, NE), and the cross-switch (Q) in a discharging state connects the resistor (R) to a second potential (NE) of the energy source terminal (PE, NE), wherein the controller is configured to set the pre-charging state (L1, U1) or the discharging state (Q2, U2),wherein the longitudinal switch (L) and / or the transverse switch (Q) in a connection state connects the first potential (PE) of the energy source terminal (PE, NE) to the first potential (A+) of the energy storage terminal, bypassing the resistor (R), wherein the controller is configured to establish the connection state.

Beamforming communication systems with crossbar switches are provided herein. In certain embodiments, a beamforming communication system includes an antenna array partitioned into a plurality of sub-arrays, a plurality of front-end channels each operatively associated with one of the sub-arrays, a plurality of data conversion channels, and a crossbar switch electrically connected between the data conversion channels and the front-end channels. Including the crossbar switch allows for a flexible allocation of the data conversion channels to the front-end channels and subsequently to each individual antenna element in the array.

A sliced router decomposes a router into a plurality of slices. Each slice has a subset of the input and output ports of the router. One or more of the slices may communicate with a network access point. Adjacent slices communicate with each other. In some example embodiments, there are dedicated physical channels between each slice and each adjacent slice for traffic coming in on or going out on ports of other slices. Within a slice, traffic may be arbitrated onto upstream or downstream channels going to the same output port. Each slice contains one or more crossbars, allowing data received on any input port to be routed to any output port of the slice. The crossbar of each slice is substantially smaller than the crossbar that would be used by a unified router.

The present disclosure provides read-out circuits for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The crossbar circuit may further include an output sensor that generates a digital output representative of a sum of currents flowing through one or more bit lines of the crossbar circuit. The output sensor includes a first transistor serially connected to a second transistor and an analog-to-digital converter configured to output the digital output. The read-out circuit is an open loop circuit. The read-out circuit may be selectively connected to one of the plurality of bit lines to perform a read operation.

An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.

The invention provides a 1S1R storage unit and a preparation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. In the preparation process of the method, the preparation device comprising the first electrode layer, the gate layer and the buffer layer is subjected to annealing process treatment, so that the gate layer and the buffer layer are crystallized, after the gate layer is crystallized, the Forming voltage can be reduced, the threshold transformation characteristic yield of the device is improved, a protruding nanocrystalline interface is formed on the surface due to the crystallization of the buffer layer, and the yield of the device is improved. And meanwhile, local field intensity is also increased by a nanocrystalline interface, so that conductive filaments of the resistive layer are robust, the positions of the formed conductive filaments of the resistive layer have a certain rule, the randomness of the generation positions of the conductive filaments is reduced, and the uniformity of electrical properties is improved. The 1S1R unit structure is not only suitable for a 1S1R array of a Crossbar structure, but also suitable for a 1S1R array of a vertical structure after being properly modified, and has a wide application prospect.

Provided is an analog-to-digital converter and a neuromorphic computing device including the analog-to-digital converter. The analog-to-digital converter is connected to a crossbar switch array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and a processing circuit. The voltage generator includes at least one resistive memory element having the same resistive material as the resistive elements included in the crossbar switch array. The voltage generator is configured to generate a first voltage based on a reference voltage and the at least one resistive memory element, and divide the first voltage to generate at least one divided voltage. The processing circuit is configured to: compare a signal voltage generated from the crossbar switch array with the at least one divided voltage to generate at least one comparison signal; and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) in crossbar circuits. The processing device may perform a programming process to program a resistive random access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

Methods and apparatus for performing diversity matrix operations within a memory fabric and for converting a memory array into a matrix fabric for spatial diversity-related matrix transformations and performing matrix operations therein. Exemplary embodiments described herein perform MIMO-related matrix transformations (e.g., precoding, beamforming, or data recovery matrix operations) within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one variant, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a matrix-vector product. The MMU may additionally perform various other logical operations within the digital domain.

The invention relates to the technical field of communication network operation and maintenance management, and discloses a communication network reliability assessment method based on big data analysis, which comprises the following steps of: 1, connecting a communication network, a bit error tester, a NetFlow analyzer and a spectrum analyzer through a network to obtain detection data of communication equipment, classifying to form a cross data set, a routing data set and a gateway data set; 2, evaluating the communication state of each crossbar switch according to the crossbar data set, and generating an exchange score; 3, evaluating the communication state of each router according to the routing data set, and generating a forwarding score; step 4, evaluating the communication state of each gateway according to the gateway data set, generating a packaging score, and realizing high multi-dimensional evaluation precision; and step 5, comprehensively evaluating the reliability of the communication network according to the exchange score, the forwarding score and the packaging score, and outputting corresponding evaluation results and optimization suggestions, thereby realizing automatic decision support and preventive maintenance, and being high in intelligent management communication stability.

An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.