291 results about "Crossbar switch" patented technology

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

An electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors. An electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically 5 interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101). A first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a 10 respective output for each column of memristors.

The embodiment of the invention provides a routing node, a data packet sending method, a storage medium and electronic equipment, and the routing node comprises a first input unit which is used for receiving a first data packet; the routing path calculation unit is connected with the first input unit and is used for acquiring data information carried by the first data packet, performing routing path calculation on the first data packet according to the data information and determining a first output unit corresponding to the first data packet; the switch distributor is used for performing switch use right arbitration on the first input unit according to the first output unit; the crossbar switch matrix is used for transmitting the first data packet from the first input unit to the first output unit under the condition of receiving the arbitration information sent by the switch distributor; and the first output unit is used for sending the first data packet to the second input unit of the second routing node under the condition that the first data packet is received through the crossbar switch matrix.

Techniques for noise and bound management for DNN training on RPU crossbar arrays using a scaling factor based on a worst-case scenario are provided. In one aspect, a method for noise and bound management includes: obtaining input vector values x for an analog crossbar array of RPU devices, wherein a weight matrix is mapped to the analog crossbar array of RPU devices; and scaling the input vector values x based on a worst-case scenario to provide scaled input vector values x′ to use as input to the analog crossbar array of RPU devices, wherein the worst-case scenario includes an assumed maximal weight of the weight matrix multiplied by a sum of absolute values from the input vector values x.

The invention discloses a dynamic bypass fault-tolerant router in a network-on-chip. The dynamic bypass fault-tolerant router comprises input and output ports, an input buffer area, a crossbar switch, a routing calculation unit, a self-checking circuit and a bypass channel. Key features comprise a fault information unit, a bypass selector, a single flit buffer area and an arbitration unit. The router detects the self-fault through the self-checking circuit, and the fault information unit stores the information. And if the router fails, the bypass selector transmits the data packet through the bypass channel and bypasses the failed router. If the router is healthy, the router exchanges fault information with an adjacent router, the fault information is used for routing decision of a data packet after integration, and meanwhile, the router can select a routing path with smaller congestion in an effective direction according to the flow distribution condition in a network. According to the method, the area overhead is relatively low, the routing hop count of the data packet is remarkably reduced, the transmission delay of the data packet is reduced while the high reliability is maintained, and the network throughput is improved.

The invention discloses a multi-level interconnection network based on real-time flow monitoring and dynamic priority adjustment. A multi-dimensional traffic sensing model is constructed through traffic intensity, queue depth, congestion signals and static priority dynamic indexes. A dynamic urgency value is generated by adopting a configurable weighting strategy, and a three-mode closed-loop optimization mechanism is designed. A layered interconnection structure is adopted, crossbar switches are used in computing clusters, and the computing clusters are connected through a low-diameter routing network. In a cluster gateway, a dynamic arbitration unit monitors the flow intensity in real time, calculates the urgency degree in combination with a queue state and a global congestion signal, and dynamically selects a fixed priority and a weighted polling or polling arbitration strategy. The problem that the resource utilization rate of a traditional static arbitration mechanism is reduced due to task switching is effectively solved, the risk of fairness imbalance in a mixed key data flow scene is effectively solved, and the communication adaptation capacity of a reconfigurable architecture to diversified computing loads is improved.

The invention provides a network-on-chip transmission information arbitration method and related equipment, and belongs to the technical field of computers, and the method comprises the following steps: determining a request to be sent by a target node in each input direction in a current round of arbitration period, and obtaining a target set; determining a weight value corresponding to each to-be-sent request in a target set according to a fault state of a node closest to a target node in a message transmission path of the target request, a space idle number of a flit size, a historical request number in the same transmission direction and a historical weight value; the historical weight value is a corresponding weight value when the target node sends each to-be-sent request in the last round of arbitration period; and sorting the to-be-sent requests in the target set according to a sequence of the weight values from high to low so as to respond to the sorted to-be-sent requests by using a crossbar switch on the target node. According to the method, the technical problem that the flow load of the network-on-chip is unbalanced in the related technology can be solved.

The embodiment of the invention provides a protocol converter and method for a network card and electronic equipment. The protocol converter comprises a protocol controller, a crossbar switch and a high-speed serial computer extension bus PCIe interface. The protocol controller is provided with a transmit-receive interface which is connected with the data node. The data node is not provided with a processor; the PCIe interface is connected with the RDMA network card and is used for transmitting data between the data node and the RDMA network card; the protocol controller further comprises a sending management unit and a receiving management unit, and the sending management unit is used for receiving data sent by the data node and sending the data to the PCIe interface through the crossbar switch in a message mechanism; and the receiving management unit is used for receiving data transmitted by the PCIe interface through the crossbar switch. By adopting the protocol converter, a data node without a processor can realize data transmission through the RDMA network card, and the data transmission rate of a common node is improved.

Beamforming communication systems with crossbar switches are provided herein. In certain embodiments, a beamforming communication system includes an antenna array partitioned into a plurality of sub-arrays, a plurality of front-end channels each operatively associated with one of the sub-arrays, a plurality of data conversion channels, and a crossbar switch electrically connected between the data conversion channels and the front-end channels. Including the crossbar switch allows for a flexible allocation of the data conversion channels to the front-end channels and subsequently to each individual antenna element in the array.

A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

The invention provides an intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method, and belongs to the technical field of integrated circuit design, the system is characterized in that an AXI interconnection matrix module is provided with a crossbar switch, a master port and a slave port, and the master port and the slave port are connected with the crossbar switch through an AXI bus; each router node in the 2D Mesh network module is provided with a local port and a peripheral port, and each router node is connected with an adjacent router node through the peripheral port; the intelligent clock gating module monitors the channel flow of the AXI interconnection matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls a clock signal; and the dynamic power management module adjusts the power consumption state according to the global power optimization signal and the local optimization signal. The overall power consumption of the system-on-chip is reduced, and the stability and efficiency of data transmission are enhanced.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

The invention provides a PCIe (Peripheral Component Interconnect Express) switching structure and a switching chip. The PCIe switching structure comprises a PCIe controller, a plurality of Router routers, a Crossbar switch, a DMA (Direct Memory Access) engine and an NOC (Note Over Chip). The Crossbar exchanger is connected with a plurality of Router routes; the PCIe controller is connected with the Crossbar exchanger through a Router route; the Crossbar exchanger is connected with the PCIe controller; a DMA (Direct Memory Access) Function and / or a P2P (Peer-to-Peer) Function are / is arranged in the PCIe controller; and the DMA engine is connected with the Crossbar exchanger through a Router route. According to the scheme, in PCIe switching supporting multiple virtual switches, multiple DMA modules are not needed, the DMA can be used as a Function in a PCIe structure according to needs so as to be attached to any virtual switching upstream port, and data migration in any switching port or between any two switching ports is supported.

A quantum-inspired parallel annealing method that enables full parallelism and improves solution quality, resulting in significant speed and energy improvement when implemented in analog memristor crossbars. Tasks are experimentally solved, including unweighted and weighted Max-Cut and traveling salesman problem using an integrated memristor chip. The method claimed herewith effective exploits the natural parallelism, analog conductance states and all-to-all connection provided by memristor technology, and therefore demonstrates significant improvements in time- and energy-efficiency compared to previous simulated annealing and Ising machine implemented on other technologies, having a large potential for solving complex optimization problems with greater efficiency.

The invention discloses a network-on-chip fault-tolerant system based on a fault processing router and a dual fault-tolerant distributed route, and relates to the technical field of network-on-chip. The system comprises a fault processing router and a dual fault-tolerant distributed routing mechanism. The fault processing router comprises a port distribution module, a redirection FIFO module, an error correction module, a crossbar switch module, a crossbar switch bypass module and a detection master control module. The modules cooperate to realize fault isolation and path reconstruction. According to the dual fault-tolerant distributed routing mechanism, fault tolerance is realized through single fault isolation, composite fault collaboration and dynamic routing adjustment, and deadlock is avoided and network connectivity under fault topology is maximized by dynamically relaxing and forbidding a steering rule. The problems of single-point failure and composite fault accumulation caused by permanent faults of transistors of the network-on-chip are solved.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

The invention relates to the technical field of network communication, in particular to an intelligent network card data forwarding method and system based on an FPGA, and the method comprises the steps: after the FPGA receives a data stream, firstly extracting a time interval standard deviation of N data packets as a time feature, executing parallel hash operation on a source IP address and a destination IP address, and mapping the source IP address and the destination IP address into three-dimensional coordinates; splicing the time features and the space coordinates into a two-dimensional matrix; a time vector T and a space vector S are separated from the two-dimensional matrix, the time feature similarity is calculated through cosine similarity, the space similarity is calculated through an Euclidean distance normalization algorithm, and affinity is obtained after weighted fusion; the condition that the affinity exceeds a first preset threshold value is used as a triggering condition for micro-flow slice splitting, and a data label is added to the slice; the FPGA intelligent network card implements heterogeneous channel binding based on slice affinity, and the global crossbar switch realizes non-blocking channel switching according to priority. And the slice splitting is triggered according to the affinity threshold, so that the high-speed transmission efficiency is improved.

The invention provides a method and a device for realizing a wireless communication algorithm, and a computer readable medium. The device for realizing the wireless communication algorithm comprises an algorithm realization module; wherein the algorithm implementation module comprises a central processing unit, a crossbar switch and an operator unit; wherein the operator unit realizes a corresponding data processing algorithm through hardware; wherein the central processing unit is configured to read microcode configuration information corresponding to a wireless communication algorithm; wherein the microcode configuration information comprises hardware connection configuration information and hardware unit configuration information; controlling a crossbar switch to connect the operator units into a combined operator unit according to the hardware connection configuration information; operator units in the combined operator unit are configured according to the hardware unit configuration information, so that the combined operator unit can realize a corresponding data processing algorithm; and the combined operator unit is configured to obtain to-be-processed data according to the configuration of the combined operator unit and perform corresponding data processing to obtain output data.

A matrix-vector multiplication device includes an input encoder that encodes an input vector into a binary complement format value and a binary true format value; a pulse generator that converts each encoded bit of the binary complement format value and each encoded bit of the binary true format value into a corresponding pulse signal; a crossbar array of weights, wherein each weight is encoded as a differential analog conductance of resistive memory devices, wherein the pulse generator simultaneously applies a pulse signal corresponding to a given encoded bit of the binary complement format value and a pulse signal corresponding to a given encoded bit of the binary true format value to corresponding resistive memory devices; an analog-to-digital converter that digitizes outputs of the crossbar array of weights to generate partial dot-product results; and a digital counter that computes a final dot-product result from the partial dot-product results.

The invention relates to the technical field of processor hardware design, and discloses an ultra-wide RISC-V long vector processor, which comprises a 64-bit scalar RISC-V core and a plurality of vector clusters, wherein each vector cluster comprises an instruction dispatcher and an instruction scheduler, the instruction dispatcher receives vector instructions sent from the scalar core and distributes the instructions to idle processing channels, and the instruction scheduler controls the execution sequence of the instructions in time; each channel is connected with the mask unit, the sliding unit and the vector read-write unit through the full-interconnection crossbar switch, and the full-interconnection crossbar switch and the mask unit carry out conditional execution on elements in a vector instruction based on the mask register. According to the method, the long vector can be quickly and efficiently calculated, the expandability problem of a full interconnection structure is solved by adopting a special layered pipeline interconnection structure, and then long vector support can be carried out on an extended vector processor architecture.

The invention discloses a crossbar switch control method based on cache information exchange, which relates to the technical field of integrated circuits and high-speed interconnection, and comprises an outlet flow control waterline register, an outlet congestion waterline register and a dequeue strategy optimization control register of an inlet receiving module in initialization configuration center control; the cache occupation amount of each outlet is monitored in real time, when the outlet cache is in an early warning state, an inlet dequeue strategy is controlled, and outlet data messages in a non-early warning state are scheduled preferentially; the cache occupation and release information is interacted in real time, and the early warning state is updated through the change of an occupation amount register; and dynamically optimizing an entrance dequeue sequence based on an exit cache early warning state, and performing decentralized flow cooperative control. The problem of performance loss of a traditional Crossbar switching chip caused by outlet bottleneck is effectively solved, and a high-performance and high-reliability switching chip technical scheme is provided for the fields of data center lossless interconnection, 5G core network packet switching and the like.

The invention discloses a request access method and system for avoiding access conflicts in a period. The system comprises a plurality of request modules, a front-end processing module, a crossbar switch and a plurality of cache blocks, the plurality of request modules are used for sending access requests; the front-end processing module is used for carrying out duplicate removal processing on requests from the plurality of request modules in a period; the crossbar switch is used for dividing an address space requested to be accessed into non-overlapped address intervals, and respectively outputting requests corresponding to different address intervals according to addresses to be accessed by the requests subjected to duplicate removal processing; each cache block corresponds to a different address interval and is used for responding to a request of the corresponding address interval. According to the method, when the same address or address interval is repeatedly accessed in one period, the number of cache blocks can be remarkably reduced, and access conflicts and request stagnation can be avoided.

The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

A quantum derived parallel annealing method is disclosed that achieves full degree of parallelism and improves understanding quality, resulting in significant speed and energy improvements when implemented in analog memristor crossbars. Tasks are experimentally addressed, including unweighted and weighted maximum cutting and traveler issues using integrated memristor chips. The claimed method effectively utilizes the natural parallelism provided by the memristor technology, simulated conductance states and many-to-many connections, and thus exhibits significant aging and energy efficiency improvements compared to previous simulated annealing and Isinin machines implemented in other technologies, such as for example, as well as for use in the field of memristor technology, as well as in the field of memristor technology, as well as in the field of memristor technology, as well as in the field of memristor technology. The method has a huge potential for solving a complex optimization problem with higher efficiency.

Combined charging / discharging circuit with an energy storage terminal (A+, A-), an energy source terminal (PE, NE), a resistor (R), a series switch (L), a cross-switch (Q), and a controller (C) which is drivingly connected to the series switch (L) and to the cross-switch (Q), which together are designed as a changeover switch, wherein the resistor (R) connects a first potential (A+) of the energy storage terminal to a connection point (P) at which the series switch (L) and the cross-switch (Q) are connected to one another, the series switch (L) in a pre-charging state connects the resistor (R) to a first potential (PE) of the energy source terminal (PE, NE), and the cross-switch (Q) in a discharging state connects the resistor (R) to a second potential (NE) of the energy source terminal (PE, NE), wherein the controller is configured to set the pre-charging state (L1, U1) or the discharging state (Q2, U2),wherein the longitudinal switch (L) and / or the transverse switch (Q) in a connection state connects the first potential (PE) of the energy source terminal (PE, NE) to the first potential (A+) of the energy storage terminal, bypassing the resistor (R), wherein the controller is configured to establish the connection state.

The invention relates to a computing device supporting hardware reconstruction and resource isolation and a reconfigurable processor, and the computing device comprises a plurality of input ports, a plurality of output ports, a data head decoding module, an input crossbar switch, a data coding module, an output crossbar switch, a controller and a computing array. The computing array comprises a simple function parallel computing module and a full function parallel computing module of which resources are mutually isolated, and the simple function parallel computing module is used for executing basic operation; the full-function parallel computing module is used for executing complex computing; the number of the simple function parallel computing modules is greater than that of the full function parallel computing modules; and the simple function parallel computing module and the full function parallel computing module support the reconstruction of a hardware connection relation under the control of the controller. According to the method, on the premise of ensuring the reconfigurability, the calculation efficiency is improved, and the chip overhead is reduced.

A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.

The present disclosure provides a crossbar circuit for performing in-memory computing and methods for performing vector-matrix multiplication (VMM) using the crossbar circuit. The crossbar circuit may include crossbar subarrays, trans-impedance amplifiers (TIAs), and analog-to-digital converter (ADCs). The crossbar subarrays may be programmed sequentially to compensate for residual errors associated with the previously programmed crossbar subarrays. For example, a first crossbar subarray may be programmed based on target conductance values. A second crossbar subarray may then be programmed based on the programming error associated with the first crossbar subarray. After the programming of the crossbar subarrays, input signals representative of an input matrix may be applied to the programmed crossbar subarrays. The TIAs may generate output voltages representative of accumulated current on the bit lines of the programmed crossbar subarrays. The DACs may convert the output voltage of the TIAs into digital outputs representing an output of a VMM operation.

Beamforming communication systems with crossbar switches are provided herein. In certain embodiments, a beamforming communication system includes an antenna array partitioned into a plurality of sub-arrays, a plurality of front-end channels each operatively associated with one of the sub-arrays, a plurality of data conversion channels, and a crossbar switch electrically connected between the data conversion channels and the front-end channels. Including the crossbar switch allows for a flexible allocation of the data conversion channels to the front-end channels and subsequently to each individual antenna element in the array.