18 results about "Wait state" patented technology

This invention discloses a unified management and scheduling method, system, and storage medium for multiple workflow engines, belonging to the field of workflow orchestration and task scheduling technology. The method includes: receiving a start request for a target workflow, creating and recording a workflow instance, and determining the engine type; based on the engine type, selecting a target runtime adapter, driving the workflow instance to execute in the engine, and establishing a node execution record; when a target workflow node enters a waiting state, writing waiting and recovery information into an extended storage area; upon receiving a recovery advancement request, resuming the template workflow's progress, and verifying and auditing the recovery data; submitting the verified recovery data to the target runtime adapter, driving the target workflow node to complete the recovery advancement and triggering subsequent node scheduling, and outputting unified progress data. This invention can reduce the integration cost when multiple engines coexist, and improve cross-engine collaborative scheduling capabilities and audit traceability capabilities.

This disclosure relates to a thread scheduling method, apparatus, electronic device, and storage medium. The thread scheduling method includes: obtaining a first parameter, which characterizes the number of processor cycles in which processor wait events occurred during the execution of a target thread in a historical scheduling cycle; a processor wait event characterizes a running event that causes a processor core to be in a waiting state; determining a second parameter based on the first parameter, which characterizes whether the occurrence of processor wait events during the execution of the target thread in a historical scheduling cycle leads to inefficient operation of the processor core; and scheduling the target thread based on the second parameter. This method uses the number of processor cycles in a waiting state as a criterion for judging processor core performance, subdividing the thread execution process from the perspective of processor cycles. This allows for a more accurate understanding of the target thread's requirements for processor core performance, ensuring that the target thread is scheduled to the most suitable processor core and maximizing the utilization of processor resources.

The application provides a concurrent vulnerability verification method and device, electronic equipment and readable storage medium, applied to the computer kernel security field, including: obtaining a first interleaved sequence in the computer kernel; the first interleaved sequence includes: a plurality of memory operation instructions; the plurality of memory operation instructions executed according to a target condition are used to trigger a concurrent vulnerability; adding a breakpoint before each memory operation instruction in the first interleaved sequence to obtain a second interleaved sequence and execute; the breakpoint is used to make the memory operation instruction after the breakpoint enter a waiting state; based on the memory operation instruction entering the waiting state and the target condition, the trigger information of the concurrent vulnerability is output. The embodiment adjusts the execution order of the interleaved sequence using the breakpoint, so that the execution process meets the target condition, and solves the problems of expected interleaved sequence execution interference and low reproduction efficiency.

The application relates to the technical field of industrial automation control, and proposes a control method, device, equipment and medium of a high-voltage frequency converter. The method comprises the following steps: receiving a ready instruction sent by a first control end, collecting real-time state signals of multiple associated components in the high-voltage frequency converter in parallel according to the ready instruction; performing logical judgment on the real-time state signals of each associated component and preset respective corresponding ready conditions; determining to enter a ready waiting state only when the real-time state signals of all the associated components all satisfy the corresponding ready conditions; after determining to enter the ready waiting state, keeping each associated component working and collecting the running state of each associated component in real time, generating and outputting a ready waiting signal to a second control end; receiving a start instruction returned by the second control end according to the ready waiting signal, and performing corresponding start operation according to the start instruction. Through the technical scheme, the control of safe and rapid start is realized.

The purpose is to enhance the enjoyment of the game. [Solution] In a gaming machine, the game control microprocessor comprises a CPU, a program executed by the CPU, a ROM storing information referenced by the program, a RAM capable of storing information updated by the program, a general-purpose register, a data register, and a flag register. The CPU writes first information to the RAM at the start of a variation performance indicating the result of a lottery. When the power to the gaming machine is cut off during the execution of the variation performance and then power is turned on to the gaming machine, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor. When the variation performance resumes after the machine has entered a waiting state for customers, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor.

The present application relates to database technology, in particular to a parallel read-write method, product, medium and equipment of an automatic storage management system. The parallel read-write method comprises: each node of a cluster database generates a respective node historical snapshot and enters a waiting state; a pre-designated coordinator node monitors the state of each node and, in response to all nodes having entered the waiting state, notifies all nodes to enter a snapshot completion state; the coordinator node forms a global historical snapshot of the cluster database based on the node historical snapshots of all nodes, so that each node performs a logical decoding operation based on the global historical snapshot. The present application uses a bitmap array in the allocation unit to lock the data in the allocation unit space in units of data pages, thereby achieving fine-grained locking and avoiding lock contention conflicts caused by locking the entire allocation unit, and thus improving the parallel read-write efficiency of the automatic storage management system.

The present application relates to the technical field of radar data processing, and provides a PCI board INTx interrupt distribution method, system, device and medium, which comprises creating a set containing multiple exclusive identifiers, constructing a corresponding synchronization structure for each identifier, initializing the structure based on a kernel waiting queue to be in a waiting state and associating a thread. The thread calls an interface with the exclusive identifier, enters the waiting state after binding the corresponding structure. The PCI board INTx interrupt triggers a response function, notifies the associated structure and wakes up the thread, and the thread executes data processing after resuming. After the processing is completed, the thread binds the original structure again, and the structure returns to the waiting state to be on standby. Thus, high-precision interrupt signals are provided, and equal-interval interrupts are allocated to each thread, meeting the demand of radar data processing for multiple equal-interval high-precision interrupt services.

This disclosure provides a method, apparatus, electronic device, and readable storage medium for processing encoding and decoding tasks, relating to the field of video encoding and decoding technology. The method includes: receiving a stream of encoding and decoding tasks to be processed; recording the processing state of the target encoding and decoding core on the encoding and decoding task stream through a state machine thread, the processing state including the lifecycle state of the hardware unit and the encoding and decoding workflow state, the encoding and decoding workflow state including: single-frame encoding and decoding execution state, single-frame encoding and decoding completion state, and temporary idle waiting state, the temporary idle waiting state being the next processing state after the single-frame encoding and decoding completion state has completed the encoding and decoding operation on the current non-tail frame; generating corresponding exception events for target processing states where processing timeouts exist; and performing exception repair on the exception events through a recovery thread according to the repair method corresponding to the target processing state. Applying this method can improve the overall processing efficiency of encoding and decoding tasks.

The application provides a priority scheduling-based multi-core platform spin lock management system and a control method thereof. The spin lock is provided with a linked list corresponding to itself. According to the priority of a second core that initiates a use request for a resource, the corresponding task of the second core is added to different positions of the linked list, and the current state of the task is set to a waiting state. After a first core releases the spin lock, the second core with the highest order in the linked list is selected in sequence, and the current state of the running task of the second core is adjusted to a wake-up state. At this time, it is confirmed that the current second core has the spin lock corresponding to the resource, and then it is confirmed that the current second core obtains the use right of the resource. No matter how many CPU processing cores are managed in the operating system, the core with a high-priority task running demand can obtain the spin lock in priority, and then the running task thereon can use the corresponding resource in priority, thereby improving the real-time performance and certainty of the operating system scheduling.

This application provides a method, system, medium, and product for synchronous conversion of CTP asynchronous interfaces, relating to the field of computer data interface technology. The method includes: receiving a synchronous call request sent by a business system through an execution thread; generating a unique request identifier through an atomic increment operation; creating a business data collection list for the unique request identifier; and simultaneously initializing a shared state variable to indicate the status of the synchronous call result of the synchronous call request; associating the unique request identifier with the corresponding response processing function and storing it in a listener mapping table; and sending a query request to the target CTP platform; causing the execution thread to enter a waiting state for a preset duration and starting an independent thread to receive the query response data pushed by the target CTP platform; and in the independent thread, performing a synchronous conversion operation on the received query response data using a target callback function. This solves the problem of low reliability in the conversion of CTP asynchronous interfaces to synchronous interfaces in related technologies.

This application discloses a user-mode thread execution control method, device, and storage medium for pthread and libc-compatible interception, relating to the field of data processing technology. The method, when the scheduler selects an application thread in a ready-to-schedule state, controls the application thread to switch to an active state to execute business logic; when the application thread initiates a blocking call, it intercepts the blocking call and, if it determines that the blocking call cannot be completed immediately, creates a waiting event object corresponding to the blocking call; it determines the target waiting queue corresponding to the calling object of the blocking call and places the waiting event object into the target waiting queue; it controls the application thread to switch to a sleep waiting state to release the CPU for execution by the scheduling thread; and when the scheduling thread receives a ready event corresponding to the waiting event object by calling the kernel interface, it controls the application thread to switch to a ready-to-schedule state, thus reducing CPU resource consumption.

This application relates to a chip verification method, apparatus, computer device, computer-readable storage medium, and computer program product. The method includes: configuring a dynamic storage structure accessible via a handle in a global control unit of the verification environment; an excitation generator, while driving a transaction request to the module under test (DUT), writing the page table entry corresponding to the transaction into the dynamic storage structure; a reference model receiving the transaction request and performing a cache matching test; when a missing state is determined, sampling the internal state signal of the DUT and entering a blocking waiting state until timing synchronization with the DUT is completed; finally, the reference model obtaining the page table entry from the dynamic storage structure and calculating the expected result, comparing it with the DUT. This invention solves the stability and completeness problems of the model under complex random states through a blocking sampling mechanism of a cacheless reference model, improving the verification efficiency and coverage of the translation cache unit.

The application relates to a coroutine running method and device, computer equipment and a storage medium. The method comprises the following steps: when a first coroutine running in a target thread causes an exception in switching to a second coroutine due to occupying a resource bound by the target thread, the target thread and the first coroutine are set to a stop state; a new thread is created, and an execution lock of the target thread is allocated to the new thread; the second coroutine is run based on the new thread to which the execution lock has been allocated; when the second coroutine running ends and the target thread enters a waiting state from the stop state, the new thread is terminated, and the execution lock of the new thread is released to the target thread; and the first coroutine is continuously run through the target thread. The method can improve the running efficiency of the coroutine.

This application discloses a method, apparatus, device, and storage medium for handling main thread lag. The technical solution provided by this application adds time-consuming tasks in the main thread to a time-consuming task queue. When all time-consuming tasks in the queue are in a waiting state, a priority time-consuming task is determined from the queue based on the task mode of each task, and then added to the main thread for execution. This ensures that at most one priority time-consuming task is placed in the main thread from the queue, reducing the accumulation of time-consuming tasks in the main thread, reducing concentrated execution of time-consuming tasks by the main thread, and reducing application lag.

This invention provides a dynamic switching method for LIN scheduling tables based on an AUTOSAR architecture. The method includes: receiving multi-source signals and evaluating and logically judging the multi-source signals according to a preset rule set to determine a target scheduling table; sending a switching request carrying the identifier of the target scheduling table and transitioning the state to a synchronization waiting state; continuously monitoring the execution progress of the current scheduling table in the synchronization waiting state and waiting for the triggering of a preset synchronization signal; when the preset synchronization signal is detected, performing a scheduling table switching operation to switch the currently active scheduling table to the target scheduling table; and confirming the completion of the scheduling table switching operation. This invention improves the utilization efficiency of LIN bus resources, effectively reduces the overall power consumption of the system, and enhances the rapid response capability to high-priority events, ensuring the real-time performance and reliability of critical data transmission.

The application provides a low-power embedded system-level chip and a power consumption control method, relates to the technical field of chips and corresponding control methods, and comprises a main execution domain, a normal open managed domain, an execution folding engine, an execution token storage array, a conditional managed engine, a selective unfolding engine and a resource reattachment control network. When an application task runs to a preset folding boundary, the execution folding engine extracts a minimum active state set of the task, recovers a program counter, an event source identifier, a condition threshold, a deadline and a target resource identifier, generates an execution token and writes the execution token into the execution token storage array in the normal open managed domain. The application converts the existing form of the application task in the waiting stage from a processor complete thread context into an execution token object, restores a three-stage control chain through execution folding, conditional management and directional unfolding, reduces the main execution domain to maintain power consumption, reduces the number of invalid wake-up times, and shortens the response time from the waiting state to the effective execution state.

This application relates to an address registration method based on an RS485 ring bus, belonging to the technical field of communication. The method includes the following initial debugging process after the master-slave connection is completed: S1. Upon power-up, each slave's ABI and ABO terminals are in receiving mode. The first slave on the ring bus receives the registration communication command sent by the master's RS485 port 1. This command contains the master ID information and the sender's address code. S2. Master registration is initiated. After sending the command, RS485 port 1 enters a waiting state. S3. Slave registration begins. After receiving the command, the slave stores the master ID information and increments the sender's address code by 1 to obtain its own address code. S31. The ABI terminal is set as an output, and a response command containing its own ID and address code is sent. S32. The ABO terminal is set as an output, forwarding the registration communication command (the sender's address code is the slave's address), and the ABO terminal is set as a receive terminal. S33. If no response is received, the slave repeats S3 until the command forwarded by the last slave through its ABO terminal is received by the master's RS485 port 2. This method avoids conflicts or errors caused by manual address configuration.