75 results about "Wait state" patented technology

The invention provides an automatic fault-tolerant propulsion method and system for task execution abnormity and a storage medium, and relates to the technical field of distributed system fault-tolerant control, and the method comprises the steps: task dynamic arrangement: arranging tasks into a serial, parallel or dependent execution mode according to a preset dynamic rule, and realizing task trigger execution through an asynchronous thread pool; performing process monitoring, adding a monitoring annotation to an execution method of each task by using an AOP tangent, and capturing a task execution state in real time; performing abnormal grading processing, and executing a strategy according to a pre-configured three-level processing channel; spreading a dependency state, and automatically updating an associated task state based on a dependency relationship among the tasks: when an upstream task fails, pausing a downstream dependency task and marking the downstream dependency task as a waiting state, and continuing to execute a non-dependency task; and performing global state statistics, calculating a global state in real time through a task state algorithm, if all tasks are completed, marking the tasks as completed, if abnormal tasks exist, marking the tasks as abnormal, and triggering root cause analysis.

A system allows multiple users to interact with the system to perform data analysis. The system allows users to specify data analytics requests using high-level natural language requests. The system generates an execution plan based on natural language requests received from a particular user and executes the execution plan. The system detects a failure in executing the execution plan and determines whether to request help from another entity. The system may change the state of execution of the execution plan to a waiting state in which the system blocks execution until it receives an approval to proceed from an entity. The system receives a request to modify the execution plan from the entity and modifies the execution plan based on the request. The system iteratively performs the modification of the execution plan until an acceptable execution plan is generated.

The embodiment of the invention provides a data synchronization communication method and device, equipment and a storage medium, and the method comprises the steps: responding to an interface calling request, configuring a target shared memory of the interface calling request, and the target shared memory comprises target calling information; after the reference information of the target shared memory is sent to a second thread corresponding to the primary layer, entering a blocking waiting state, so that the second thread performs processing based on the reference information to obtain target response information and notifies the first thread to end the blocking waiting state; and after the blocking waiting state is ended, obtaining target response information from the target shared memory, and feeding back target result information. According to the scheme, lightweight and efficient synchronous interface calling can be realized, and the communication efficiency is improved.

This invention discloses a unified management and scheduling method, system, and storage medium for multiple workflow engines, belonging to the field of workflow orchestration and task scheduling technology. The method includes: receiving a start request for a target workflow, creating and recording a workflow instance, and determining the engine type; based on the engine type, selecting a target runtime adapter, driving the workflow instance to execute in the engine, and establishing a node execution record; when a target workflow node enters a waiting state, writing waiting and recovery information into an extended storage area; upon receiving a recovery advancement request, resuming the template workflow's progress, and verifying and auditing the recovery data; submitting the verified recovery data to the target runtime adapter, driving the target workflow node to complete the recovery advancement and triggering subsequent node scheduling, and outputting unified progress data. This invention can reduce the integration cost when multiple engines coexist, and improve cross-engine collaborative scheduling capabilities and audit traceability capabilities.

In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

The application discloses a kind of based on multiple buffer's obfuscated network packet assembly transmission method and device, the method, including, data packet assembly step and cache data sending step;Data packet assembly step: multiple buffer is set for data packet to be sent queue, extract a data packet from to-be-sent queue each time, whether the idle load space of each buffer can accommodate the data packet in turn according to preset order is judged, can accommodate then store and continue to extract next;When all buffer cannot accommodate, enter waiting state until the data of buffer is read and sent, and then re-execute storage;Cache data sending step: multiple buffer is locked at preset sending time, read first buffer data and fill to the size of set load after forwarding to obfuscated network;After forwarding is completed, execute buffer pointer switching, unlock buffer and wait for the next sending time to repeat sending, improve payload utilization by optimizing data packet assembly and sending logic.

The application discloses a general multi-master parallel on-chip bus supporting X86 architecture and belongs to the field of data transmission buses. The general on-chip bus supports parallel data transmission between multiple master processing devices and multiple slave devices, supports IO and memory space access, multiple priority arbitration strategies, multiple waiting states, an on-chip shared address multi-path data (SAMD) topology structure and three-state multiplexing of a bus data external interface, read and write data are multiplexed, and PPGA pin resources are saved. Through testing and simulation, a general IP core is formed, can be applied in different EDA development tools and development environments, has strong generalization, can effectively avoid repeated work, improve work efficiency, and further reduce research and development cost and research and development time.

A process of an operating system is detected as having undergone a live migration, where the live migration involves a change in a hardware feature of the computer system on which the process is executing. A first message is transmitted to a group of processors, the first message causing each processor in the group of processors to enter a wait state. While each of the group of processors is in the wait state, a portion of a set of program instructions of the operating system is modified.

The invention provides a thread running method, a multi-core processor, computing equipment and a computing equipment cluster, and belongs to the technical field of computers. In the method, operation modes of processor cores of the multi-core processor comprise a user mode and a user exclusive mode; when a first processor core executes a first task through a first user thread in a user mode, if the first user thread executes first mode switching in the first task, the first processor core enters a user exclusive mode; the processor core can run the user thread in the user exclusive mode and has the execution authority for the instruction used for controlling the state of the processor core in the operating system kernel, so that the first processor core can freely enter the waiting state in the user exclusive mode and continue to execute the first task after being awakened; the method does not need to switch back to the user mode, and does not need to switch the mode when the processor needs to enter the waiting state next time, thereby improving the efficiency of inter-core communication between user threads, and reducing the power consumption of the processor.

Embodiments of the present application provide a process instance processing method and device, equipment and a storage medium, belonging to the technical field of financial technology. The method comprises: putting a candidate process instance with a process priority into an instance waiting queue; extracting a candidate process node and a node execution order of a target process instance from the instance waiting queue according to the process priority; executing the target process instance according to the node execution order to obtain a target execution instance; obtaining a target process node in a waiting state from the target execution instance to obtain a target process node, and putting the target process node into a node waiting queue; extracting a current node category and a current execution operation of a current process node from the node waiting queue according to the node execution order; calling a microservice to execute the current execution operation according to the current node category to obtain a node execution result; and executing the target execution instance according to the node execution result and the node execution order. The embodiments of the present application can automatically control the microservice to complete the business, and improve the efficiency of business completion.

This disclosure relates to a thread scheduling method, apparatus, electronic device, and storage medium. The thread scheduling method includes: obtaining a first parameter, which characterizes the number of processor cycles in which processor wait events occurred during the execution of a target thread in a historical scheduling cycle; a processor wait event characterizes a running event that causes a processor core to be in a waiting state; determining a second parameter based on the first parameter, which characterizes whether the occurrence of processor wait events during the execution of the target thread in a historical scheduling cycle leads to inefficient operation of the processor core; and scheduling the target thread based on the second parameter. This method uses the number of processor cycles in a waiting state as a criterion for judging processor core performance, subdividing the thread execution process from the perspective of processor cycles. This allows for a more accurate understanding of the target thread's requirements for processor core performance, ensuring that the target thread is scheduled to the most suitable processor core and maximizing the utilization of processor resources.

The application provides a concurrent vulnerability verification method and device, electronic equipment and readable storage medium, applied to the computer kernel security field, including: obtaining a first interleaved sequence in the computer kernel; the first interleaved sequence includes: a plurality of memory operation instructions; the plurality of memory operation instructions executed according to a target condition are used to trigger a concurrent vulnerability; adding a breakpoint before each memory operation instruction in the first interleaved sequence to obtain a second interleaved sequence and execute; the breakpoint is used to make the memory operation instruction after the breakpoint enter a waiting state; based on the memory operation instruction entering the waiting state and the target condition, the trigger information of the concurrent vulnerability is output. The embodiment adjusts the execution order of the interleaved sequence using the breakpoint, so that the execution process meets the target condition, and solves the problems of expected interleaved sequence execution interference and low reproduction efficiency.

The application relates to the technical field of industrial automation control, and proposes a control method, device, equipment and medium of a high-voltage frequency converter. The method comprises the following steps: receiving a ready instruction sent by a first control end, collecting real-time state signals of multiple associated components in the high-voltage frequency converter in parallel according to the ready instruction; performing logical judgment on the real-time state signals of each associated component and preset respective corresponding ready conditions; determining to enter a ready waiting state only when the real-time state signals of all the associated components all satisfy the corresponding ready conditions; after determining to enter the ready waiting state, keeping each associated component working and collecting the running state of each associated component in real time, generating and outputting a ready waiting signal to a second control end; receiving a start instruction returned by the second control end according to the ready waiting signal, and performing corresponding start operation according to the start instruction. Through the technical scheme, the control of safe and rapid start is realized.

This invention discloses a data parallel processing method, apparatus, and electronic device based on model data, relating to the field of multi-threaded control technology, aimed at reducing power consumption during model-localized runtime. The method includes: after the first thread in the multi-threaded system completes its calculation, if the global busy-wait token is in a closed state, setting the global busy-wait token to an open state, simultaneously setting its own end token to an open state, and entering a cyclic busy-wait state; after the second thread in the multi-threaded system completes its calculation, if the global busy-wait token is in a open state, setting the second thread's own end token to an open state, stopping execution, and relinquishing the CPU. This invention is applicable to data processing of large localized models.

The purpose is to enhance the enjoyment of the game. [Solution] In a gaming machine, the game control microprocessor comprises a CPU, a program executed by the CPU, a ROM storing information referenced by the program, a RAM capable of storing information updated by the program, a general-purpose register, a data register, and a flag register. The CPU writes first information to the RAM at the start of a variation performance indicating the result of a lottery. When the power to the gaming machine is cut off during the execution of the variation performance and then power is turned on to the gaming machine, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor. When the variation performance resumes after the machine has entered a waiting state for customers, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor.

The invention discloses a task assignment method and system based on a task graph, and relates to the technical field of sparse linear equation set solver, and the method comprises the steps: calculating task processing time based on a time estimation model during task assignment; the number of completed tasks is initialized to be zero, the number of initial idle threads is initialized to be the number of total threads, and the tasks with the initial task state being in task waiting are put into a to-be-dispatched task sequence; executing a task assignment main cycle; when the initial idle thread number is greater than zero and the to-be-dispatched task sequence is not empty, distributing a thread number for the task; when the initial idle thread count is zero, determining the fastest thread based on the task processing time; when the to-be-dispatched task sequence is empty, traversing the task chain depending on the current task to obtain the dependent task of the current task, putting the dependent task into the to-be-dispatched task sequence, and executing the task dispatching main cycle, so that the problem that the task processing time cannot be accurately predicted and the thread resources cannot be uniformly distributed in the prior art can be solved.

The invention provides a data processing method and device, electronic equipment and a medium, and belongs to the technical field of cloud computing. The method comprises the following steps of: in any time slice allocated to a consumer driver, when the total byte number recorded by a memory counter is reduced to 0 or data in a cache region is read empty, taking out a producer driver from a blocking queue, adding the producer driver into a ready queue, and controlling the consumer driver to be in a waiting state without offering the allocated time slice; after the waiting duration of the consumer driver reaches a preset duration, allocating a time slice to the producer driver in the ready queue, and awakening the consumer driver through the producer driver; and controlling a producer driving program to write data into the cache region, and controlling a consumer driving program to read data from the cache region, thereby providing a data processing method.

This application relates to a method for rapidly accelerating an engine based on a dynamic thread pool in large-scale scenarios. The method includes: configuring basic parameters such as the number of core threads and the maximum number of threads, or generating parameters through a computational model for initialization; after task submission, first determining the availability of core threads, and if idle, creating threads to execute tasks based on load prediction to determine the expansion step size; when the core thread pool is full, checking the blocking queue status, storing tasks if not full, and triggering expansion if full; when the thread pool is full, executing a saturation strategy to block submissions until resources are idle; after task execution, threads enter a waiting state, and if a timeout occurs, they are released to sleep, with the remaining thread count not less than the core thread count. This method can accelerate the process of the engine calling the simulation model, ensuring the normal execution of training tasks.

The application relates to the chip technical field, in particular to a software and hardware joint debugging method based on an IPC, electronic equipment and a medium, the method comprises the following steps: S1, obtaining N software test case sets which need to be run on a to-be-tested chip design in parallel; S2, assigning a corresponding process group (B1 n , B2 n ) to each A n , assigning a corresponding interaction identifier P n to each process group based on an IPC protocol; S3, starting all B1 n in parallel, each B1 n starts to execute the corresponding A n , meanwhile, the chip RTL code performs a chip initialization operation, B1 n generates A n corresponding register configuration instructions based on the corresponding A n , and enters a waiting state; S4, after the to-be-tested chip design completes the chip initialization operation, B1 n and B2 n perform inter-process communication based on the corresponding P n , and A n is run on the to-be-tested chip design. The application reduces the cross-stage verification cost of the software test case and improves the chip verification efficiency.

The invention discloses a novel intelligent washing machine mode, and belongs to the technical field of intelligent household appliance control. The invention aims to solve the problems that the program of the traditional washing machine is fixed and the personalized and complex washing and care requirements of users cannot be met. The method comprises the following steps: firstly, establishing an atomic operation library containing independent actions such as water feeding, washing and dehydration; through a graphical visual construction interface, a user is allowed to freely select atomic instructions, configure specific parameters and recombine the atomic instructions into a self-defined program instruction queue according to actual requirements; and analyzing and executing the instructions in the queue one by one by utilizing a dynamic interpretation engine. And in the execution process, the system tracks the completion, execution and waiting states of the instruction in real time through a text list, and feeds back equipment operation data through a physical instrument. The black box limitation of a traditional washing program is broken through, washing process programming of WYSIWYG is achieved, and the user is endowed with the complete definition right and control right for the washing process.

The invention discloses a task cooperative processing method and device, a storage medium and a terminal, after a first task processor responds to an execution signal for a target task, whether a conflict task corresponding to the target task is executed by a second task processor is judged, and the target task and the conflict task need to use the same resource during execution; if the conflict task which is being executed exists, enabling the target task to enter a waiting state; if the conflict task which is being executed does not exist, executing the target task; and when the target task is in a waiting state, if a task end message after the conflict task is executed is received, responding to the execution signal again. In this way, the execution state of the conflicting task is checked before the task is executed, so that whether the target task can use the needed resources or not under the current condition is known, then the current task is executed or waited, the situation that the tasks need to use the same resource at the same time to cause conflicts is avoided, and the cooperation efficiency of multiple parallel tasks is improved.

The invention relates to a master-slave node data synchronization and state optimization method based on a CAN bus. The method comprises the following steps: initializing related configuration of the CAN bus; binding the configured slave node IDs; after the slave node ID binding is completed, the master node waits for a control system self-checking instruction, and after self-checking is executed, the instruction is forwarded to the slave node; the slave node performs self-inspection after receiving the forwarded self-inspection instruction, and feeds back a self-inspection result to the master node; the master node feeds back a self-checking result to the control system after receiving the self-checking result fed back by the slave node; and after completion, the servo system returns to a waiting state. According to the method, through time slice calculation, node ID setting and state optimization, it is ensured that the master node can efficiently receive slave node data, feed back the state of the whole servo system to the control system and accurately position slave node faults, data synchronization of the master node and the slave node is achieved, the real-time performance and reliability of the servo system are improved, and troubleshooting time is shortened.

This application provides a kernel reboot method, to reserve an internal memory for storing an entry address of a physical code and a code segment for the physical core. A kernel hotswap scenario is used as an example. When a computer system stops executing an old kernel, an interrupt is sent to the physical core, so that the physical core enters a busy waiting state. When the computer system starts a new kernel, the entry address of the physical core is modified. When finding that the entry address is modified, the physical core in the busy waiting state exits the busy waiting state, performs an initialization procedure of the physical core, and receives task scheduling of the new kernel.

The present application relates to database technology, in particular to a parallel read-write method, product, medium and equipment of an automatic storage management system. The parallel read-write method comprises: each node of a cluster database generates a respective node historical snapshot and enters a waiting state; a pre-designated coordinator node monitors the state of each node and, in response to all nodes having entered the waiting state, notifies all nodes to enter a snapshot completion state; the coordinator node forms a global historical snapshot of the cluster database based on the node historical snapshots of all nodes, so that each node performs a logical decoding operation based on the global historical snapshot. The present application uses a bitmap array in the allocation unit to lock the data in the allocation unit space in units of data pages, thereby achieving fine-grained locking and avoiding lock contention conflicts caused by locking the entire allocation unit, and thus improving the parallel read-write efficiency of the automatic storage management system.

The task processing method is applied to the operation and maintenance platform, the operation and maintenance platform comprises an event queue and a task executor, and the task processing method comprises the steps that the event queue receives at least one operation and maintenance task of an application, task events corresponding to the at least one operation and maintenance task are added into the event queue, and the task executor takes out a first task event from the event queue, calling a first execution unit in the execution unit resource pool, executing the first sub-task, issuing the operation of the first sub-task on the resource to the resource, releasing the first execution unit, receiving a first resource event sent by the resource by the event queue, and executing the first resource event by the task executor according to the state of the resource described by the first resource event. And determining the next task or the next subtask to be processed, and executing the next task or the next subtask. According to the method, events are taken as the center, states of operation and maintenance tasks, subtasks and resources are taken as events for processing, and tasks are processed from smaller granularity. Moreover, the execution unit is not blocked by the waiting state of the operation and maintenance task, and the resource utilization rate is improved.

This invention relates to the field of parallel system technology, and in particular to a control method, control device, and storage medium for a parallel system. The method includes: after entering a parallel state, acquiring its own random code and random delay, and entering a waiting state based on the random delay; if no first control command is received from other controllers during the waiting state, then acting as the master and sending the first control command to all other controllers; receiving a slave command including the slave's random code sent by a slave device; in response to the slave command, allocating a virtual parallel address to the slave device from an address list, and sending a response command including the virtual parallel address to the slave device; acquiring the total number of currently connected slave devices, setting a transmission period based on the total number, and sending a second control command to all slave devices according to the transmission period; and receiving a slave data command sent by each slave device in response to the second control command based on its own random delay. This invention eliminates the need for manual address adjustment, improving convenience and reducing costs.

The present application relates to the technical field of radar data processing, and provides a PCI board INTx interrupt distribution method, system, device and medium, which comprises creating a set containing multiple exclusive identifiers, constructing a corresponding synchronization structure for each identifier, initializing the structure based on a kernel waiting queue to be in a waiting state and associating a thread. The thread calls an interface with the exclusive identifier, enters the waiting state after binding the corresponding structure. The PCI board INTx interrupt triggers a response function, notifies the associated structure and wakes up the thread, and the thread executes data processing after resuming. After the processing is completed, the thread binds the original structure again, and the structure returns to the waiting state to be on standby. Thus, high-precision interrupt signals are provided, and equal-interval interrupts are allocated to each thread, meeting the demand of radar data processing for multiple equal-interval high-precision interrupt services.

This disclosure provides a method, apparatus, electronic device, and readable storage medium for processing encoding and decoding tasks, relating to the field of video encoding and decoding technology. The method includes: receiving a stream of encoding and decoding tasks to be processed; recording the processing state of the target encoding and decoding core on the encoding and decoding task stream through a state machine thread, the processing state including the lifecycle state of the hardware unit and the encoding and decoding workflow state, the encoding and decoding workflow state including: single-frame encoding and decoding execution state, single-frame encoding and decoding completion state, and temporary idle waiting state, the temporary idle waiting state being the next processing state after the single-frame encoding and decoding completion state has completed the encoding and decoding operation on the current non-tail frame; generating corresponding exception events for target processing states where processing timeouts exist; and performing exception repair on the exception events through a recovery thread according to the repair method corresponding to the target processing state. Applying this method can improve the overall processing efficiency of encoding and decoding tasks.

The invention provides a congestion control method and device, electronic equipment and a storage medium, and belongs to the technical field of networks. The method comprises the steps that in each preset period, the number of clock periods in a normal scheduling state and the number of clock periods in a congestion waiting state of switching equipment are determined, the preset period comprises a plurality of clock periods, and the preset period is a congestion signal detection period; determining a candidate congestion signal based on the number of the clock cycles in the normal scheduling state and the number of the clock cycles in the congestion waiting state, the candidate congestion signal indicating a congestion degree of the switching device in a preset period; and based on the candidate congestion signal, determining a target congestion signal to adjust a data transmission rate in a network link where the switching device is located, the target congestion signal indicating a congestion degree of the network link. According to the method, the congestion signal capable of accurately reflecting the congestion degree is provided, and low-overhead network congestion control is realized.

To provide a server device that can quickly deliver report files. [Solution] In the server device 200, the intermittent appending unit 250 intermittently appends log information about newly created or updated records in the database 210 to the report file for the store at predetermined time intervals. When a store terminal requests to download the report file, the supplemental appending unit 260 appends the log information since the last append by the intermittent appending unit 250 to the report file. When the supplemental appending unit 260 starts appending, the providing unit 270 makes the intermittent appending unit 250 wait for appending, and when the supplemental appending unit 260 completes appending, it provides the report file to the customer terminal. Then, when the providing unit 270 has finished providing the report file, the restarting unit 280 initializes the report file, releases the waiting state of the intermittent appending unit 250, and resumes appending.