63 results about "Dram chip" patented technology

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

The invention discloses an edge end large language model inference system. The system comprises a main computing chip, an LPDDR interconnection resource and a vertically stacked and packaged storage chip stack, the storage chip stack comprises an NAND flash memory chip and a DRAM (Dynamic Random Access Memory) chip, and the NAND flash memory chip and the DRAM chip are paired and share an LPDDR interconnection resource; the NAND flash memory chip comprises a flash memory chip bare chip and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip bare chip which are three-dimensionally interconnected based on hybrid bonding; a flash memory array is arranged on the flash memory chip bare chip; a logic block is arranged on the CMOS chip bare chip; the main calculation chip reads a parameter matrix of a model full connection layer from the NAND flash memory chip and reads other parameters from the DRAM chip for calculation in a pre-filling stage of large language model reasoning; and the NAND flash memory chip performs full connection layer calculation in a decoding stage. The system provided by the invention can improve the external transmission and internal reading bandwidth.

The invention belongs to the technical field of chip packaging, and particularly relates to a three-dimensional stacked DRAM (Dynamic Random Access Memory) packaging structure based on electro-coppering cylinders. The packaging structure specifically comprises a bottom-layer logic chip, a top-layer DRAM chip, a second-layer DRAM chip, a vertical copper column interconnection region, a bottom-layer packaging body, a top-layer packaging body, a second-layer packaging body, a planar interconnection region, a signal longitudinal transmission path, a C4 bump array and a micro bump array, the bottom-layer packaging body packages the bottom-layer logic chip, the vertical copper cylinder and the planar metal wire interconnection layer together in a plastic mode, and the top-layer packaging body and the second-layer packaging body are similar to the bottom-layer packaging body in function; according to the invention, the TSV is replaced by the off-chip copper cylinder manufactured by electroplating in the packaging stage, so that the longitudinal interconnection of the chip is realized, and the DRAM three-dimensional integration with lower cost and high reliability is further realized; and meanwhile, the design difficulty of a memory chip is reduced, the system storage capacity is improved, and the overall performance of the system is improved.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

The invention discloses an iRDIMM storage access method and system. The iRDIMM storage access method comprises the following steps: detecting storage conditions of a plurality of storage units; when it is detected that a weak storage unit exists in the multiple storage units according to the storage condition, the address of the weak storage unit is written into the mapped address of the address mapping table, and the address of the reserved storage unit is written into the mapping address of the address mapping table, so that when the address of the weak storage unit is accessed, the address of the reserved storage unit is accessed according to the address of the weak storage unit and the address query table; accessing a reserved storage unit address; wherein the address query table comprises a weak storage unit index table and a weak storage unit mapping table, and the weak storage unit index table is used for querying weak storage unit addresses; the address mapping table is used for storing the corresponding relation between the weak storage unit address and the mapping address; a storage area indicated by the reserved storage unit address is located in a reserved space of the DRAM chip. The memory reliability is improved, and errors generated at the application end can be reduced.

The present invention belongs to the field of semiconductor technology, and specifically relates to a chip design method and a chip system. The chip design method includes: integrating a local DRAM controller, a global DRAM controller, and a shared DRAM controller on a processor core, and integrating several processor cores on a logic chip. The DRAM chips are stacked vertically on the logic chip, each global DRAM controller is connected to the shared DRAM storage space, and the shared DRAM controllers are respectively connected to their corresponding private DRAM storage spaces. The present invention directly connects to the shared DRAM storage space through the global DRAM controller, reduces the intermediate links, shortens the data path, and improves the data exchange speed. The shared DRAM controller is directly connected to the private DRAM storage space of each processor core, thereby realizing memory sharing data interaction between the processor cores.

The invention discloses a DDR5 dynamic ODT regulation and control method, device and equipment based on multi-working-condition perception and a medium, and relates to the field of computer memories, and the method comprises the steps: obtaining a power supply ripple value and a DRAM chip temperature value of a system; querying a preset ripple-temperature-ODT value corresponding table by taking the power supply ripple value and the DRAM chip temperature value as a joint index to obtain a corresponding target ODT value; and writing the target ODT value into an ODT control register of the DDR5 chip through a mode register setting command. Multi-working-condition sensing is achieved by synchronously monitoring power supply ripples and chip temperature, the optimal ODT value is directly obtained based on a joint index query preset optimization mapping table, and finally configuration is written through a standard MRS command. Comprehensive state monitoring, pre-stored expert knowledge and a standard hardware interface are combined, microsecond-level fast decision making and reliable regulation and control are achieved, on the premise that an existing DDR5 standard is completely compatible, signal integrity is effectively guaranteed, system power consumption is optimized, and the overall performance and energy efficiency of a memory subsystem are improved.

The invention relates to the technical field of artificial intelligence, and discloses a hybrid bonding-based large model reasoning data read-write method and system, a controller and a storage medium, and the method comprises the following steps: constructing hybrid bonding connection between a PIM chip and a DRAM chip and between the PIM chip and a FLASH chip; when the large model is used for reasoning, the weight of the large model is stored in the FLASH chip through the data bus, and the cue word of the large model is stored in the DRAM chip through the data bus; in the pre-filling stage, the PIM chip is used for respectively reading the weight and the cue word, and the calculated first key value is cached and written into the DRAM chip; and in a decoding stage, respectively reading the weight and the first key value cache by utilizing the PIM chip, and writing the second key value cache of the Token generated by the large model into the DRAM chip. According to the method, the processing engine in the PIM chip is utilized, data only need to be read from the FLASH and the DRAM which are closest in physical distance, delay is reduced, model weight data and key value cache data do not need to be read through a bus route, data carrying is reduced, and power consumption is reduced.

A memory and routing module includes a substrate and a connection component. The connection component is attached to the substrate and includes multiple pins that connect the module to a corresponding connection component on a motherboard. The substrate is connected to a dynamic random-access memory, DRAM, chip, and a routing chip. The routing chip includes a memory controller, multiple connections, and routing logic. The multiple connections include a first group between the memory controller and the DRAM chip and a second group of connections with the pins of the connection component. The routing logic routes data between the second group of connections and the first group of connections.

This invention relates to the field of semiconductor memory repair technology, specifically a QR code encoding method and system for DRAM chip repair mapping. It includes: determining the total number of blocks and the allowable number of damaged blocks; setting encoding rules containing block status information and verification information; testing the chip under test to identify the location of damaged blocks; generating repair data according to the encoding rules and calculating the check byte using extended Hamming code; converting the encoded information into a QR code and laser-printing it on the chip surface; scanning and reading the code on the production line for verification and error correction, automatically correcting single-bit errors, prompting rescanning for double-bit errors, and writing the data to the storage area; and reading the repair data from the storage area during application, performing verification and error correction again, and executing block mapping. This invention ensures reliable transmission of repair data through a two-stage error correction protection mechanism, significantly improving chip utilization.

The invention provides a chip storage area testing method and device, equipment and a computer storage medium. The chip storage area test method comprises the following steps: acquiring an address of a target area for storing a target test program in a to-be-tested DRAM (Dynamic Random Access Memory) chip; loading the initial test program to an SRAM chip in a test system SOC, and calling the initial test program to test the target area according to the address; and under the condition that the test of the target area is passed, testing areas except the target area in the to-be-tested DRAM chip according to the target test program and the target area. By means of the chip storage area testing method, the detection blind area of the DRAM chip to be tested is eliminated, and reliable testing of the full physical memory space, namely the whole storage area, of the DRAM chip to be tested is achieved.

A self-managed DRAM module configured to reduce energy consumption. A module is described that includes a plurality of DDR channels, each DDR channel having a set of DRAM chips; and a management engine configured to read and write data blocks to DDR channels, wherein a write operation of a data block in a DDR channel is implemented according to a process that includes: compressing the data block to generate a compressed data block; encoding the compressed data block to obtain a punctured ECC codeword; determining a reduced number of DRAM chips in the DDR channel required to store the punctured ECC codeword; storing metadata indicative of the reduced number; and writing the punctured ECC codeword to the reduced number of DRAM chips in the DDR channel.

An example operation includes one or more of receiving a request for access to data stored within a chip stack that comprises a plurality of dynamic random-access memory (DRAM) chips which are communicably coupled to a substrate, and a NOT AND (NAND) flash memory chip which is communicably coupled to the plurality of DRAM chips, and accessing the data within the chip stack based on the plurality of DRAM chips and the NAND flash memory chip within the chip stack.

This invention discloses a UMCP product packaging structure that reduces product thickness, enabling the product to meet the requirements for thinness and lightness. It includes: a DRAM chipset; a Nand Flash chipset; an FC main control chip; a first substrate; a second substrate, which serves as a carrier substrate; and a first molding compound. The bottom BUMP of the FC active chip is soldered to the central region of the upper surface of the first substrate. The bottom layer of the DRAM chipset is mounted to the upper surface of the FC main control chip. Each layer of DRAM chips in the DRAM chipset is connected to the corresponding upper surface of the first substrate via a first wire bonding assembly. The bottom first solder ball of the first substrate is soldered to one side of the upper surface of the second substrate. The bottom layer of the Nand Flash chipset is mounted to the other side of the upper surface of the second substrate. Each layer of the Nand Flash chipset is connected to the corresponding upper surface of the second substrate via a second wire bonding assembly. The first molding compound encapsulates the DRAM chipset, Nand Flash chipset, FC main control chip, and first substrate on the upper surface of the second substrate.

The invention provides a packaging structure and a manufacturing method thereof, and relates to the field of semiconductors, and the packaging structure comprises a first substrate which is provided with a first SoC chip and a first DRAM chip; the cooling fin is attached to the surfaces of the first SoC chip and the first DRAM chip; the second substrate is arranged above the first substrate, a second SoC chip and a second DRAM chip are arranged on the second substrate, and a capacitor is arranged on the back surface of the second substrate; the front surfaces of the first substrate and the second substrate are oppositely arranged, and the second SoC chip and the second DRAM chip are attached to the surface of the radiating fin; four flexible silicon connecting layers are arranged between the first substrate and the second substrate, the two ends of each flexible silicon connecting layer are welded to the first substrate and the second substrate, and the four flexible silicon connecting layers are distributed in an orthogonal mode. The problem that the packaging size is too large due to the fact that the SoC chips and the DRAM chips are horizontally arranged is effectively solved, and meanwhile the heat conduction efficiency of the system is optimized.

This invention discloses an aging test method for dynamic random access memory (DRAM), relating to the field of memory testing technology. The method includes: S1: Model Establishment: Aging tests are performed on a reference chip sample, and the test results are monitored and acquired. Simultaneously, based on the test results and a statistical analysis model, a correlation model between real-time monitoring parameters and the long-term lifespan of the chip is constructed; S2: Closed-Loop Testing: Based on the correlation model, a damage control threshold is determined. Simultaneously, based on the damage control threshold, selected electrical parameters for the aging test of the DRAM chip under test are monitored, and the test parameters are adjusted; S3: Test Judgment: Functional tests are performed on each DRAM chip under test to determine the chip test results. This method avoids the problem of hidden damage to virgin chips caused by excessive stress in traditional aging tests, ensuring the long-term lifespan and stability of the chips in actual use.

The invention discloses a subgraph GNN acceleration system and an electronic chip. The subgraph GNN acceleration system comprises a DRAM chip used for storage and a logic chip used for calculation, and the DRAM chip and the logic chip are packaged together through a 3D hybrid bonding technology to form a near memory architecture; the DRAM chip comprises a plurality of storage blocks, the logic chip comprises a plurality of logic blocks, the plurality of storage blocks are configured into multiple rows and multiple columns on the DRAM chip, the plurality of logic blocks are configured into multiple rows and multiple columns on the logic chip, the row number and the column number of the storage blocks configured on the DRAM chip are consistent with the row number and the column number of the logic blocks configured on the logic chip, and the storage blocks and the logic blocks are in one-to-one correspondence. Forming a plurality of logic-storage blocks; in a sub-graph processing stage in the sub-graph GNN, workloads are allocated to respective logic-storage blocks at sub-graph granularity. According to the invention, parallel processing of the sub-graphs can be realized.

A self-managed DRAM module and method. The module includes a plurality of DRAM chips; and a controller chip configured to store a data block received from a host according to a process that includes: compressing the data block to generate a compressed data block; performing error detection code (EDC) encoding on the compressed block and adding an EDC redundancy to the compressed block; partitioning the compressed block with the EDC redundancy into a set of m data chunks; performing error correction code (ECC) encoding on each of the m data chunks to generate m codewords; and writing the m codewords to the DRAM chips.

A self-managed DRAM module and method. The module includes a plurality of DRAM chips; and a controller chip configured to compress a data chunk received from a host according to a process that includes: compressing the data chunk to generate a plurality of compression results, wherein each compression result includes a different block size; identifying an optimal compression result, wherein the optimal compression result has a lowest block size among the plurality of compression results that achieves a threshold compression; and storing the optimal compression result in the plurality of DRAM chips.

The invention relates to the technical field of dynamic random access memories, and particularly provides a hierarchical screening method and system based on a DRAM chip, and the method comprises the steps: monitoring the energy absorption fluctuation of each storage unit, and recording a dynamic response curve; after the dynamic response curve is subjected to Fourier transform processing, deriving a quantitative data set of the energy characteristic spectrum; performing similarity calculation on energy distribution modes in the energy characteristic spectrum, and generating a similarity matrix by calculating Euclidean distance and angle deviation between characteristic vectors; outputting a feature clustering group; a variable load condition is applied to each feature clustering group, and an actual working environment is simulated; monitoring a stability index of the storage unit; after a verification result is subjected to weighted scoring, final graded output is generated; the memory cells are divided into a plurality of performance levels. The system comprises a data set derivation module, a clustering group output module and a weighted scoring module. According to the method, the accuracy and the applicability of DRAM chip quality evaluation are remarkably improved.

An apparatus including a stack of a plurality of substrates, wherein the stack includes a plurality of channels extending therethrough. The plurality of channels are configured to allow air to flow therethrough; a plurality of dynamic random-access memory (DRAM) chips. Respective ones of the plurality of DRAM chips are attached to one of the plurality of substrates and located within one of the plurality of channels. The apparatus also includes a plurality of processor chips located on an outer surface of the stack, and a plurality of wires electrically connecting the plurality of DRAM chips to the plurality of processor chips.

The invention belongs to the technical field of artificial intelligence accelerators, and discloses a double-ring sparse attention acceleration system and method based on a 3D stacked hybrid computing architecture, and the system comprises a DRAM chip and a logic chip which are vertically integrated through a hybrid bonding technology, the DRAM chip is provided with a plurality of vertical cores, and the vertical cores are arranged in parallel; each vertical core comprises a DRAM (Dynamic Random Access Memory) block and a logic block aligned with the DRAM; a matrix processing engine, an auxiliary function engine, a memory controller, a dual-port SRAM buffer area, an NoC router and a global controller are integrated in the logic block; the matrix processing engine includes a plurality of dual mode DCIM macros supporting a broadcast mode and a pulsation mode. Through sparse pruning of the algorithm level and 3D stacking design of the architecture level, deep collaborative optimization of the algorithm and hardware is realized, the advantages of the hardware architecture are fully played, and the performance is remarkably improved.

This utility model provides a composite substrate suitable for high-performance computing, relating to the semiconductor field, comprising: a first substrate having a through-groove along its thickness direction; a second substrate disposed in the through-groove, with a buffer zone between the first and second substrates, the first and second substrates being electrically connected through the buffer zone; an ASIC chip disposed above the second substrate, the ASIC chip being electrically connected to both the first and second substrates; and a DRAM chip disposed above the second substrate, the DRAM chip being electrically connected to both the first and second substrates. The first substrate is an organic substrate, and the second substrate is a glass substrate. This application utilizes the smooth surface of the glass substrate, which enables narrower linewidths and spacings, to combine the glass substrate and the organic substrate, thereby reducing the size of the composite substrate suitable for high-performance computing while maintaining the same interconnect speed.

This invention discloses a solid-state drive (SSD) firmware architecture system, comprising: multiple driver modules, each driver module corresponding to a type of storage chip, and the multiple driver modules are sequentially stored in non-volatile memory and share the same preset runtime memory address segment during runtime; a hardware identification module, used to obtain the type information of the storage chip currently installed in the SSD during the firmware startup phase; and a loading management module, connecting the hardware identification module and the non-volatile memory, loading the target driver module from the non-volatile memory into the preset runtime memory address segment for use by the firmware main program. Thus, by adopting firmware normalization, only a unified firmware image needs to be maintained, and different NAND / DRAM chip combinations can be adapted by loading different overlay driver modules, greatly reducing the number of firmware versions and lowering management complexity.

The invention discloses a test system and method for a DRAM (Dynamic Random Access Memory) chip, and the system comprises an FPGA (Field Programmable Gate Array) and LVDS (Low Voltage Differential Signaling) combined module which is used for transmitting a signal to a to-be-tested DRAM chip, receiving a signal returned by the DRAM chip, and controlling the DRAM chip to enter different working states; the voltage detection ADC circuit is used for acquiring voltage change signals of the DRAM chip to be tested in different working states; and the upper computer is used for controlling the FPGA and LVDS combined module, receiving and processing signal data from the FPGA and LVDS combined module and the voltage detection ADC circuit, and carrying out power consumption analysis and display on a test result. And an ATE test scheme is replaced to realize chip power consumption measurement. Meanwhile, compared with an original defective product testing scheme, the method can replace ATE to analyze the testing process, the defect that an original SLT scheme cannot analyze and debug the voltage and current conditions of the specific address of the DRAM is overcome, and low-cost convenient verification is conducted on the physique of the defective product.

The present disclosure provides a dynamic random access memory (DRAM) device. The dynamic random access memory device comprises a plurality of slave dynamic random access memory chips and a master dynamic random access memory chip. Each of the plurality of slave dynamic random access memory chips includes a slave fuse circuit and a slave reference voltage generator. The subordinate fuse circuit provides a subordinate setting signal according to a subordinate fuse setting operation of the subordinate fuse circuit. The subordinate reference voltage generator provides a subordinate reference voltage according to a subordinate setting signal. The master dynamic random access memory chip controls operation of the plurality of slave dynamic random access memory chips.

The present disclosure provides a dynamic random access memory (DRAM) device, in particular, a dynamic random access memory (DRAM) device, in particular, a DRAM (dynamic random access memory) device, in particular, a DRAM (dynamic random access memory) device. The DRAM device comprises a slave DRAM chip and a master DRAM chip. The slave DRAM chip comprises a slave control circuit and a slave power supply circuit. The subordinate control circuit generates a subordinate control signal according to the subordinate category signal and the setting signal. The slave power supply circuit stops generating at least one of a plurality of slave voltages in response to a first value of the slave control signal, and generates the plurality of slave voltages in response to a second value of the slave control signal. The main DRAM chip comprises a main control circuit. The main control circuit generates a main control signal according to the main category signal and the setting signal, and controls the main DRAM chip to generate a plurality of main voltages according to the main control signal. The slave class signal is different from the master class signal.

The invention belongs to the technical field of semiconductors, and particularly relates to a chip design method and a chip system. The chip design method comprises the following steps of: integrating a local DRAM (Dynamic Random Access Memory) controller, a global DRAM controller and a shared DRAM controller on a processor core, and integrating a plurality of processor cores on a logic chip. The DRAM chips are vertically stacked on the logic chip, all the global DRAM controllers are connected with the shared DRAM storage space, and the shared DRAM controllers are connected with the corresponding private DRAM storage spaces respectively. The global DRAM controller is directly connected to the shared DRAM storage space, intermediate links are reduced, the data path is shortened, the data exchange speed is increased, the shared DRAM controller is directly connected with the private DRAM storage space of each processor core, and memory shared data interaction between the processor cores is achieved.

The invention relates to the technical field of chip packaging, in particular to a multi-memory chip packaging structure and a packaging method. Comprising an Soc chip and a Dram chip, the Soc chip is provided with a bonding pad and a first conductive structure, the Soc chip is connected with an SRAM chip through the bonding pad, the Soc chip is connected with a rewiring layer through the first conductive structure, the surface of the DRAM chip is connected with the rewiring layer through an electric connection structure, one side of the rewiring layer is connected with solder balls through a UBM layer, and the other side of the rewiring layer is provided with a plastic package layer. Compared with the prior art, the large-size SRAM Chip is externally arranged on the SoC, and SoC / SRAM / Dram multi-chip fan-out integration is carried out; and through a large-size SRAM or a plurality of SRAMs, the calculation speed of the high-speed cache is improved.

A dynamic random-access memory (DRAM) device is provided. The DRAM device includes slave DRAM chips and a master DRAM chip. Each of the slave DRAM chips includes a slave reference voltage pad, a slave voltage sensor, a slave voltage pump and a slave fuse circuit. The slave voltage sensor senses a voltage value of a reference voltage on the slave reference voltage pad and provides a slave oscillating signal according to the voltage value of a reference voltage on the slave reference voltage pad. The slave voltage pump provides the reference voltage according to the slave oscillating signal. The slave fuse circuit provides a slave set signal according to a slave fuse setting operation of the slave fuse circuit and disables the slave voltage sensor according to the slave set signal. The master DRAM chip controls operations of the slave DRAM chips.