28 results about "Dram chip" patented technology

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

The invention discloses a DDR5 dynamic ODT regulation and control method, device and equipment based on multi-working-condition perception and a medium, and relates to the field of computer memories, and the method comprises the steps: obtaining a power supply ripple value and a DRAM chip temperature value of a system; querying a preset ripple-temperature-ODT value corresponding table by taking the power supply ripple value and the DRAM chip temperature value as a joint index to obtain a corresponding target ODT value; and writing the target ODT value into an ODT control register of the DDR5 chip through a mode register setting command. Multi-working-condition sensing is achieved by synchronously monitoring power supply ripples and chip temperature, the optimal ODT value is directly obtained based on a joint index query preset optimization mapping table, and finally configuration is written through a standard MRS command. Comprehensive state monitoring, pre-stored expert knowledge and a standard hardware interface are combined, microsecond-level fast decision making and reliable regulation and control are achieved, on the premise that an existing DDR5 standard is completely compatible, signal integrity is effectively guaranteed, system power consumption is optimized, and the overall performance and energy efficiency of a memory subsystem are improved.

The invention relates to the technical field of artificial intelligence, and discloses a hybrid bonding-based large model reasoning data read-write method and system, a controller and a storage medium, and the method comprises the following steps: constructing hybrid bonding connection between a PIM chip and a DRAM chip and between the PIM chip and a FLASH chip; when the large model is used for reasoning, the weight of the large model is stored in the FLASH chip through the data bus, and the cue word of the large model is stored in the DRAM chip through the data bus; in the pre-filling stage, the PIM chip is used for respectively reading the weight and the cue word, and the calculated first key value is cached and written into the DRAM chip; and in a decoding stage, respectively reading the weight and the first key value cache by utilizing the PIM chip, and writing the second key value cache of the Token generated by the large model into the DRAM chip. According to the method, the processing engine in the PIM chip is utilized, data only need to be read from the FLASH and the DRAM which are closest in physical distance, delay is reduced, model weight data and key value cache data do not need to be read through a bus route, data carrying is reduced, and power consumption is reduced.

This invention relates to the field of semiconductor memory repair technology, specifically a QR code encoding method and system for DRAM chip repair mapping. It includes: determining the total number of blocks and the allowable number of damaged blocks; setting encoding rules containing block status information and verification information; testing the chip under test to identify the location of damaged blocks; generating repair data according to the encoding rules and calculating the check byte using extended Hamming code; converting the encoded information into a QR code and laser-printing it on the chip surface; scanning and reading the code on the production line for verification and error correction, automatically correcting single-bit errors, prompting rescanning for double-bit errors, and writing the data to the storage area; and reading the repair data from the storage area during application, performing verification and error correction again, and executing block mapping. This invention ensures reliable transmission of repair data through a two-stage error correction protection mechanism, significantly improving chip utilization.

A self-managed DRAM module configured to reduce energy consumption. A module is described that includes a plurality of DDR channels, each DDR channel having a set of DRAM chips; and a management engine configured to read and write data blocks to DDR channels, wherein a write operation of a data block in a DDR channel is implemented according to a process that includes: compressing the data block to generate a compressed data block; encoding the compressed data block to obtain a punctured ECC codeword; determining a reduced number of DRAM chips in the DDR channel required to store the punctured ECC codeword; storing metadata indicative of the reduced number; and writing the punctured ECC codeword to the reduced number of DRAM chips in the DDR channel.

An example operation includes one or more of receiving a request for access to data stored within a chip stack that comprises a plurality of dynamic random-access memory (DRAM) chips which are communicably coupled to a substrate, and a NOT AND (NAND) flash memory chip which is communicably coupled to the plurality of DRAM chips, and accessing the data within the chip stack based on the plurality of DRAM chips and the NAND flash memory chip within the chip stack.

This invention discloses an aging test method for dynamic random access memory (DRAM), relating to the field of memory testing technology. The method includes: S1: Model Establishment: Aging tests are performed on a reference chip sample, and the test results are monitored and acquired. Simultaneously, based on the test results and a statistical analysis model, a correlation model between real-time monitoring parameters and the long-term lifespan of the chip is constructed; S2: Closed-Loop Testing: Based on the correlation model, a damage control threshold is determined. Simultaneously, based on the damage control threshold, selected electrical parameters for the aging test of the DRAM chip under test are monitored, and the test parameters are adjusted; S3: Test Judgment: Functional tests are performed on each DRAM chip under test to determine the chip test results. This method avoids the problem of hidden damage to virgin chips caused by excessive stress in traditional aging tests, ensuring the long-term lifespan and stability of the chips in actual use.

The invention discloses a subgraph GNN acceleration system and an electronic chip. The subgraph GNN acceleration system comprises a DRAM chip used for storage and a logic chip used for calculation, and the DRAM chip and the logic chip are packaged together through a 3D hybrid bonding technology to form a near memory architecture; the DRAM chip comprises a plurality of storage blocks, the logic chip comprises a plurality of logic blocks, the plurality of storage blocks are configured into multiple rows and multiple columns on the DRAM chip, the plurality of logic blocks are configured into multiple rows and multiple columns on the logic chip, the row number and the column number of the storage blocks configured on the DRAM chip are consistent with the row number and the column number of the logic blocks configured on the logic chip, and the storage blocks and the logic blocks are in one-to-one correspondence. Forming a plurality of logic-storage blocks; in a sub-graph processing stage in the sub-graph GNN, workloads are allocated to respective logic-storage blocks at sub-graph granularity. According to the invention, parallel processing of the sub-graphs can be realized.

A self-managed DRAM module and method. The module includes a plurality of DRAM chips; and a controller chip configured to store a data block received from a host according to a process that includes: compressing the data block to generate a compressed data block; performing error detection code (EDC) encoding on the compressed block and adding an EDC redundancy to the compressed block; partitioning the compressed block with the EDC redundancy into a set of m data chunks; performing error correction code (ECC) encoding on each of the m data chunks to generate m codewords; and writing the m codewords to the DRAM chips.

A self-managed DRAM module and method. The module includes a plurality of DRAM chips; and a controller chip configured to compress a data chunk received from a host according to a process that includes: compressing the data chunk to generate a plurality of compression results, wherein each compression result includes a different block size; identifying an optimal compression result, wherein the optimal compression result has a lowest block size among the plurality of compression results that achieves a threshold compression; and storing the optimal compression result in the plurality of DRAM chips.

The invention relates to the technical field of dynamic random access memories, and particularly provides a hierarchical screening method and system based on a DRAM chip, and the method comprises the steps: monitoring the energy absorption fluctuation of each storage unit, and recording a dynamic response curve; after the dynamic response curve is subjected to Fourier transform processing, deriving a quantitative data set of the energy characteristic spectrum; performing similarity calculation on energy distribution modes in the energy characteristic spectrum, and generating a similarity matrix by calculating Euclidean distance and angle deviation between characteristic vectors; outputting a feature clustering group; a variable load condition is applied to each feature clustering group, and an actual working environment is simulated; monitoring a stability index of the storage unit; after a verification result is subjected to weighted scoring, final graded output is generated; the memory cells are divided into a plurality of performance levels. The system comprises a data set derivation module, a clustering group output module and a weighted scoring module. According to the method, the accuracy and the applicability of DRAM chip quality evaluation are remarkably improved.

An apparatus including a stack of a plurality of substrates, wherein the stack includes a plurality of channels extending therethrough. The plurality of channels are configured to allow air to flow therethrough; a plurality of dynamic random-access memory (DRAM) chips. Respective ones of the plurality of DRAM chips are attached to one of the plurality of substrates and located within one of the plurality of channels. The apparatus also includes a plurality of processor chips located on an outer surface of the stack, and a plurality of wires electrically connecting the plurality of DRAM chips to the plurality of processor chips.

The invention belongs to the technical field of artificial intelligence accelerators, and discloses a double-ring sparse attention acceleration system and method based on a 3D stacked hybrid computing architecture, and the system comprises a DRAM chip and a logic chip which are vertically integrated through a hybrid bonding technology, the DRAM chip is provided with a plurality of vertical cores, and the vertical cores are arranged in parallel; each vertical core comprises a DRAM (Dynamic Random Access Memory) block and a logic block aligned with the DRAM; a matrix processing engine, an auxiliary function engine, a memory controller, a dual-port SRAM buffer area, an NoC router and a global controller are integrated in the logic block; the matrix processing engine includes a plurality of dual mode DCIM macros supporting a broadcast mode and a pulsation mode. Through sparse pruning of the algorithm level and 3D stacking design of the architecture level, deep collaborative optimization of the algorithm and hardware is realized, the advantages of the hardware architecture are fully played, and the performance is remarkably improved.

This utility model provides a composite substrate suitable for high-performance computing, relating to the semiconductor field, comprising: a first substrate having a through-groove along its thickness direction; a second substrate disposed in the through-groove, with a buffer zone between the first and second substrates, the first and second substrates being electrically connected through the buffer zone; an ASIC chip disposed above the second substrate, the ASIC chip being electrically connected to both the first and second substrates; and a DRAM chip disposed above the second substrate, the DRAM chip being electrically connected to both the first and second substrates. The first substrate is an organic substrate, and the second substrate is a glass substrate. This application utilizes the smooth surface of the glass substrate, which enables narrower linewidths and spacings, to combine the glass substrate and the organic substrate, thereby reducing the size of the composite substrate suitable for high-performance computing while maintaining the same interconnect speed.

This invention discloses a solid-state drive (SSD) firmware architecture system, comprising: multiple driver modules, each driver module corresponding to a type of storage chip, and the multiple driver modules are sequentially stored in non-volatile memory and share the same preset runtime memory address segment during runtime; a hardware identification module, used to obtain the type information of the storage chip currently installed in the SSD during the firmware startup phase; and a loading management module, connecting the hardware identification module and the non-volatile memory, loading the target driver module from the non-volatile memory into the preset runtime memory address segment for use by the firmware main program. Thus, by adopting firmware normalization, only a unified firmware image needs to be maintained, and different NAND / DRAM chip combinations can be adapted by loading different overlay driver modules, greatly reducing the number of firmware versions and lowering management complexity.

The present disclosure provides a dynamic random access memory (DRAM) device, in particular, a dynamic random access memory (DRAM) device, in particular, a DRAM (dynamic random access memory) device, in particular, a DRAM (dynamic random access memory) device. The DRAM device comprises a slave DRAM chip and a master DRAM chip. The slave DRAM chip comprises a slave control circuit and a slave power supply circuit. The subordinate control circuit generates a subordinate control signal according to the subordinate category signal and the setting signal. The slave power supply circuit stops generating at least one of a plurality of slave voltages in response to a first value of the slave control signal, and generates the plurality of slave voltages in response to a second value of the slave control signal. The main DRAM chip comprises a main control circuit. The main control circuit generates a main control signal according to the main category signal and the setting signal, and controls the main DRAM chip to generate a plurality of main voltages according to the main control signal. The slave class signal is different from the master class signal.

A dynamic random-access memory (DRAM) device is provided. The DRAM device includes slave DRAM chips and a master DRAM chip. Each of the slave DRAM chips includes a slave reference voltage pad, a slave voltage sensor, a slave voltage pump and a slave fuse circuit. The slave voltage sensor senses a voltage value of a reference voltage on the slave reference voltage pad and provides a slave oscillating signal according to the voltage value of a reference voltage on the slave reference voltage pad. The slave voltage pump provides the reference voltage according to the slave oscillating signal. The slave fuse circuit provides a slave set signal according to a slave fuse setting operation of the slave fuse circuit and disables the slave voltage sensor according to the slave set signal. The master DRAM chip controls operations of the slave DRAM chips.

A bridge chip die, a memory device and an electronic system are provided. The provided bridging chip crystal grain is used for connecting at least one DRAM chip crystal grain; wherein the bridging chip crystal grain is used for being integrated with the at least one DRAM chip crystal grain through 3D packaging; the bridging chip crystal grain comprises one or more UCIe interfaces, a plurality of DRAM (Dynamic Random Access Memory) controllers, a Cache controller and an SRAM (Static Random Access Memory); each of the plurality of DRAM controllers is used for accessing a corresponding DRAM block; each of the plurality of DRAM controllers comprises a 3D DRAM interface; when the main plane of the bridging chip crystal grain is attached to the main plane of the first DRAM chip crystal grain in the at least one DRAM chip crystal grain, the 3D DRAM interface of each DRAM controller is correspondingly connected with the DRAM interface of each DRAM block of the first DRAM chip crystal grain; and the Cache controller and the SRAM are used as the Cache of the at least one DRAM chip crystal grain.

A dynamic random-access memory (DRAM) device is provided. The DRAM device includes a plurality of slave DRAM chips and a master DRAM chip. Each of the plurality of slave DRAM chips includes a slave fuse circuit and a slave reference voltage generator. The slave fuse circuit provides a slave set signal according to a slave fuse setting operation of the slave fuse circuit. The slave reference voltage generator provides a slave reference voltage according to the slave set signal. The master DRAM chip controls operations of the plurality of slave DRAM chips.

This application provides a unified memory architecture suitable for distributed 3D-DRAM, relating to the field of artificial intelligence technology, including: a storage layer, a buffer layer, and a logic layer; the storage layer is formed by three-dimensional stacking of multiple DRAM chips for storing data; the DRAM chips are interconnected with the buffer layer via through-silicon via (TSV) technology; the buffer layer, located between the storage layer and the logic layer, is used to preprocess data from the storage layer and perform data stream scheduling; the logic layer integrates multiple computing cores for parallel processing of the data streams scheduled by the buffer layer; the computing cores are interconnected with the buffer layer via TSV technology and correspond one-to-one with the DRAM chips. This application achieves unified and efficient access to local and remote memory in a distributed 3D-DRAM architecture, thereby reducing programming complexity and improving overall computing performance.

The application provides a storage computing chip and a manufacturing method thereof, which vertically stacks a logic chip with a computing processor, a buffer chip and a DRAM chip (or a DRAM chip stack) by a through silicon via, and the chips can directly communicate through the through silicon via, so that the chip area is saved, the integration degree is high, the wafer processing difficulty is reduced, the logic chip can access a low-speed DRAM chip in a large amount of parallel mode through the buffer chip, high bandwidth and large capacity cache are provided, and a physical layer interface is not needed between the buffer chip and the logic chip to complete the inter-chip communication, so that the hardware resource cost is greatly reduced.

A memory system including a first chip having a processor, and a second chip having a DRAM sector that includes: a plurality of DRAM arrays; an output circuit configured to store a plurality of data values read from the DRAM arrays; a first set of through silicon vias (TSVs) connecting the processor to the DRAM sector, wherein the first processor transmits a plurality of weight data values to the DRAM sector on the first set of TSVs; a plurality of comparator arrays coupled to receive the plurality of weight data values and the plurality of data values read from the DRAM arrays, and in response, generate a plurality of comparison output values; and a second set of TSVs connecting the processor to the DRAM sector, wherein the plurality of comparison output values are transmitted from DRAM sector to the processor on the second set of TSVs.

The invention discloses a collaborative parallelization error correction method and equipment for a DRAM (Dynamic Random Access Memory), and belongs to the field of computer storage, and the method comprises the following steps: at a DRAM chip end, carrying out error detection on a code word consisting of a data block D and a check bit thereof by utilizing an in-memory error correction code, if an error is detected in the D, generating a pseudo-random number at the DRAM chip end and injecting the pseudo-random number into a sub-block where the error is located, and if the error is detected in the D, carrying out error correction on the sub-block; obtaining a data block D ', and sending the D' to a memory controller; in a memory controller, a plurality of data blocks from a DRAM chip are combined into RS erasure code words, and pseudo-random numbers in the RS erasure code words are identified as known errors through pseudo-random number comparison; performing error correction on the RS erasure code word based on known error information; in the memory controller, a new pseudo-random number is generated every time the pseudo-random numbers are successfully compared, and the pseudo-random number generated at the ith time is the same as the pseudo-random number generated at the ith time in the DRAM chip. According to the invention, DRAM error correction with low overhead, high reliability and low delay can be realized.

The present application relates to a semiconductor packaging structure and a preparation method therefor. The semiconductor packaging structure comprises: a DRAM wafer, the DRAM wafer comprising a plurality of DRAM chips and a plurality of first through-silicon vias penetrating the DRAM wafer; a BEOL layer, which is located on one side of the DRAM wafer; a DTC layer, which is located on the side surface of the BEOL layer facing away from the DRAM wafer, the DTC layer comprising a plurality of DTC chips, and each DTC chip being provided with a plurality of second through-silicon vias; and a processor layer, which is located on the side surface of the DTC layer facing away from the BEOL layer, the processor layer comprising a plurality of processor chips, wherein the DRAM wafer and the DTC layer are connected together by means of hybrid bonding, and the DTC layer and the processor layer are connected together by means of hybrid bonding. The semiconductor packaging structure provided in the present application can improve the integration density of a system, improve the stability and strength of an SoW packaging structure, reduce the transmission distance and transmission power consumption for stored data, mitigate crosstalk and return loss by means of a DTC, and reduce power network impedance, thereby further improving the signal integrity of a DRAM and the overall power integrity of the system.

The invention relates to the technical field of semiconductor memory repair, in particular to a two-dimensional code encoding method and system for DRAM particle repair mapping. Comprising the following steps: determining a total block number and an allowable damaged block number, and setting a coding rule containing block state information and verification information; the to-be-tested particles are tested, and the positions of damaged blocks are identified; generating repair data according to a coding rule, and calculating a check byte by adopting an extended Hamming code; coding information is converted into two-dimensional codes and the two-dimensional codes are printed on the surfaces of the particles through laser; performing code scanning and reading on a production line, performing verification and error correction, automatically correcting a single-bit error, prompting a double-bit error to re-scan the code, and writing the code into a storage area; and reading the repair data from the storage area during application, performing verification and error correction again, and executing block mapping. Through a double-stage error correction protection mechanism, reliable transmission of repair data is ensured, and the particle utilization rate is remarkably improved.

This invention provides a temperature control method and a 3D stacked DRAM chip, belonging to the interdisciplinary field of computer storage and heat dissipation control. The method includes: acquiring the real-time temperature output by a temperature sensor; if the real-time temperature is greater than a first preset value, executing a first cooling scheme, the first cooling scheme including: sending a request to an external host to reduce downlink traffic, so as to reduce the access load on the DRAM chip according to the downlink traffic adjusted by the external host. This invention can reduce the access load on the DRAM chip based on the downlink traffic adjusted by the external host, reducing the rate of heat generation of the stacked DRAM chips, thereby improving the heat dissipation effect of the original heat dissipation processes of the 3D stacked DRAM chip, such as system-level solutions like air cooling and liquid cooling, and package-level structural solutions like vertical heat conduction channels.

A dynamic random-access memory (DRAM) device is provided. The DRAM device includes a slave DRAM chip and a master DRAM chip. The slave DRAM chip includes a slave control circuit and a slave power circuit. The slave control circuit generates a slave control signal according to a slave category signal and a setting signal. The slave power circuit stops generating at least one of slave voltages in response to a first value of the slave control signal and generates the slave voltages in response to a second value of the slave control signal. The master DRAM chip includes a master control circuit. The master control circuit generates a master control signal according to a master category signal and the setting signal, and controls the master DRAM chip to generate master voltages according to the master control signal. The slave category signal is different from the master category signal.

The utility model provides a kind of multilayer stack package structure, it is related to the field of semiconductor packaging, comprising: vertically stacked first unit and second unit, the first unit and second unit are respectively installed with SoC chip and DRAM chip by substrate, SoC chip and DRAM chip on the first unit and the second unit respectively with the fin surface contact on the first unit to realize heat dissipation, still welded with flexible silicon connecting layer on the second unit, the both ends of flexible silicon connecting layer are welded with the substrate of first unit and play mechanical support and circuit connection path, as a kind of form of 2D / 2.5D package, replace HBM chip with DRAM chip, utilize multiple DRAM chips to reach corresponding bandwidth with HBM, utilize vertically stacked mode to solve the problem of large package size caused by horizontal connection of multiple SoC chips and DRAM chips, utilize fin to relieve the heat dissipation problem of chip in the first unit and the second unit.