19 results about "Serial presence detect" patented technology

Embodiments of the present disclosure provide a method and apparatus for reporting asset information, a non-transitory computer readable storage medium, and an electronic device. The method for reporting asset information includes: reading, in a case where a target device supports memory expansion, Serial Presence Detect (SPD) information of a designated memory bank mounted to the target device from a configuration space register of a Memory Expander Controller (MXC) of the target device by means of a Basic Input Output System (BIOS), wherein the target device is a device that supports a Computer Express Link (CXL) protocol, which is an open interconnection standard; and reporting, in a case where target SPD information has been read, the target SPD information to a Central Processing Unit (CPU) of the target device as system asset information by means of the BIOS.

The invention discloses a memory device management method and device, and relates to the field of computers.The method comprises the steps that field data of N bytes are extracted from serial existence detection data of a server memory device, and the bytes comprise key fields such as manufacturer numbers, production place information, production years, production weeks and serial numbers; and the target sequence identifier is generated according to the preset rule combination, and the identifier completely reflects physical factory information such as a manufacturer, a production place, time and a unique serial number of the memory device, so that the purpose of unifying memory sequence identifier display is achieved, and the technical effect that complete memory information can be accurately checked in real time without physically disassembling a server is achieved. The operation and maintenance efficiency of the server is improved, the hardware management cost is reduced, and the reliability and applicability of the system are enhanced.

A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

The present application provides a memory device supporting multiple serial presence detection settings. The device includes a sequence presence detection module disposed on a substrate and electrically connected to a plurality of memory units. The sequence presence detection module is electrically connected to a storage element, including a first memory setting data and a second memory setting data respectively support a first processor and a second processor, which are different computational processing circuits. When the sequence presence detection module is electrically connected to a respective processor of the first processor and the second processor, the sequence presence detection module correspondingly reads a respective memory setting of the first memory setting data and the second memory setting data to support the respective processor.

The embodiment of the application provides a HSA pin resistance value selection method, device and computer readable storage medium, and relates to the chip technical field.The method internally arranges a nonvolatile memory in a serial presence detect hub, and utilizes the nonvolatile memory to persistently save a HID (HID is an abbreviation of High Definition) which can normally work at low temperature, normal temperature and high temperature, that is, an optimal HID.In use of the serial presence detect hub, a user can directly acquire the optimal HID in the nonvolatile memory of the serial presence detect hub, and access preset resistance values corresponding to the optimal HID to the HSA pin of the serial presence detect hub, so that the test time of the user is saved, and the use experience of the user is improved.

This application discloses a memory testing method and electronic device, relating to the field of memory testing technology. The method includes: dynamically configuring the testing environment based on the serial presence detection parameters of the memory under test, ensuring precise matching of testing criteria with memory specifications, significantly improving the accuracy and relevance of the test; simultaneously, by comparing power supply parameters and serial presence detection parameters in real time, dynamic adjustment of the protection threshold is achieved, which avoids accidental interruptions, ensures test continuity, and can respond promptly to real anomalies, effectively improving testing efficiency and reducing the risk of memory damage.

The invention discloses a memory testing method and electronic equipment, and relates to the technical field of memory testing, and the memory testing method comprises the steps that a testing environment is dynamically configured according to serial existence detection parameters of a to-be-tested memory, so that a testing criterion is accurately matched with a memory specification, and the testing accuracy and pertinence are remarkably improved; meanwhile, dynamic adjustment of the protection threshold is achieved by comparing the power supply parameters with the serial existence detection parameters in real time, mistaken interruption is avoided, the test continuity is guaranteed, response can be made in time when real abnormity occurs, the test efficiency is effectively improved, and the memory damage risk is reduced.

The invention provides an automatic burning system and method for serial existence detection information, and the system comprises a port scanning module which is used for automatically detecting available serial communication ports on a host, and determining a serial communication port to be burnt from the available serial communication ports; the address identification module is used for automatically identifying and connecting an EEPROM (Electrically Erasable Programmable Read-Only Memory) address of a serial communication port to be burnt; the data reading module is used for reading original serial existence detection data from the EEPROM chip according to the EEPROM address; the data modification module is used for acquiring two-dimensional code information on the memory bank, analyzing and extracting serial existence detection parameters, and updating original serial existence detection data in the EEPROM chip according to the serial existence detection parameters; and the data writing module is used for writing the updated serial existence detection data into the EEPROM chip. Therefore, the burning operation process is simplified, and the burning efficiency and accuracy are improved.

An active information display dynamic memory module is disclosed. The active information display dynamic memory module involves a microcontroller unit; a serial presence detect hub, electrically connected to the microcontroller unit; and a display panel, electrically connected to the microcontroller unit. Thereby, for DRAM modules under the JEDEC specification, new functional circuits on the circuit layout on the circuit carrier board is designed through designing customized microcontroller units. Through firmware design, the microcontroller unit is electrically connected to the serial presence detect hub and the display panel and controlled to actively display the specification and information of memory modules of different models.

A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.

The present application provides an automated programming system and method for serial presence detect information. The system includes: a port scanning module for automatically detecting available serial communication ports on a host and determining the serial communication port to be programmed from the available serial communication ports; an address identification module for automatically identifying and connecting to the EEPROM address of the serial communication port to be programmed; a data reading module for reading original serial presence detect data from an EEPROM chip according to the EEPROM address; a data modification module for obtaining the two-dimensional code information on a memory module, parsing and extracting serial presence detect parameters, and updating the original serial presence detect data in the EEPROM chip according to the serial presence detect parameters; and a data writing module for writing the updated serial presence detect data into the EEPROM chip. Thereby simplifying the programming operation process and improving the programming efficiency and accuracy.

The present disclosure provides a memory module, a manufacturing method thereof, and a monitoring method thereof. The memory module includes: a substrate, the substrate including a first region and a second region, the first region and the second region having no intersection; an identification module disposed in the first region, the identification module storing identification information of the memory module, the identification information of the memory module including serial presence detection information of the memory module; and a memory chip disposed in the second region. In the present disclosure, by disposing the identification module and the memory chip in the first and second regions, respectively, which have no intersection, the identification module can be prevented from occupying core circuit space, allowing the identification module and the memory chip to maintain their respective functions without interference; information management of the memory module is achieved by storing the identification information of the memory module in the identification module disposed in the first region.

A system includes a memory module and an SPD writer. The memory module includes a first memory device having a first capacity, and a serial presence detect (SPD) device configured to store data of the memory module. The SPD writer is configured to change the data according to a capacity of the memory module. The SPD writer includes a test pad configured to measure a first voltage signal generated by a controller. After the first memory device is replaced by a second memory device having a second capacity different from the first capacity, the test pad measures the first voltage signal.

A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and / or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command / address signals.

The invention provides a memory module and a manufacturing method and a monitoring method thereof, the memory module comprises a substrate, the substrate comprises a first area and a second area, and the first area and the second area have no intersection; the identification module is arranged in the first area, the identification module stores identification information of the memory module, and the identification information of the memory module comprises serial existence detection information of the memory module; and the memory chip is arranged in the second area. In the invention, the identification module and the memory chip are respectively arranged in the first area and the second area which are not intersected, so that the identification module can be prevented from occupying the space of a core circuit, and the identification module and the memory chip keep respective functions without being interfered; the information management of the memory module is realized through the identification information of the memory module stored by the identification module arranged in the first area.

The application discloses a memory SPD information recovery method and device and a computing device, and relates to the technical field of computers.The method comprises the following steps: acquiring serial presence detect (SPD) information of each memory, each memory having identification information for representing the specifications of the memory, and the identification information and the SPD information of the memory of the same specifications being the same; when a fault memory with erroneous SPD information exists, recording first identification information of the fault memory, and determining target identification information from second identification information corresponding to the memory with non-erroneous SPD information, the target identification information being the same as the first identification information of the fault memory; and re-determining target SPD information corresponding to the target identification information as the SPD information of the fault memory. In this way, after the information of the fault memory with the SPD information variation is recovered, the fault memory can still be normally used because the hardware of the memory itself is not faulty, and the normal start of the system is no longer affected, so that the fault tolerance performance of the system is improved.

A method and apparatus for adjusting a memory capacity, an electronic device, and a storage medium are provided by embodiments of the present application. The method includes: reading serial presence detect (SPD) data of a target memory from a basic input output system (BIOS) image of a BIOS, wherein the SPD data is reserved and the target memory is a physical memory without an SPD controller; and adjusting a memory capacity of the target memory based on the SPD data of the target memory. In the embodiments of the present application, dynamic adjustment on the memory capacity without SPD controllers may be achieved and dynamic adjustment on the memory capacity of an overall server without manually disassembling the memory modules of the server may be met, actual business needs of customers are met, the service life of memories is prolonged, and operation and maintenance costs are reduced.

A serial presence detect (SPD) device includes a region of nonvolatile memory for SPD data and an additional region for other (e.g., vendor) use. The additional region may be subdivided into write protect regions that can be individually and independently write protected. To configure the write protection, a password key scheme is used to enter a mode whereby the write protection attributes may be configured. Another password key scheme is used to exit the write protection configuration mode.