51 results about "Serial presence detect" patented technology

An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.

A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.

An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

A server comprises a BMC (Baseboard Management Controller), a BIOS (Basic Input Output System), a temperature sensor, and an SPD (Serial Presence Detect) chip. The BMC comprises a setting module, a judging module, and a detection module, wherein the setting module is used for setting a bus mark bit as a first numerical value when the server is started up; the judging module is used for judging whether the bus mark bit is the first numerical value or not when the temperature of an internal storage is required to be detected; and the detection module is used for visiting the temperature sensor by utilizing an I2C bus when the bus mark bit is the first numerical value. The BIOS comprises a modification module, a delay module, an initialization module and a reset module, wherein the modification module is used for setting the bus mark bit as a second numerical value when the inner storage is required to be initialized; the delay module is used for delaying schedule time; the initialization module is used for visiting the SPD chip by utilizing the I2C bus to acquire the configuration information on the internal storage to initialize the internal storage when the schedule time is over; and the reset module is used for resetting the bus mark bit as the first numerical value after the initialization of the internal storage is completed. The invention further provides a method for avoiding the bus collision by utilizing the server, which can avoid bus collision caused by that the I2C bus is simultaneously used by the BMC and the BIOS.

A system and method to provide memory test patterns for the calibration of a delay locked loop (DLL) using a pseudo random bit sequence (PRBS) stored in a serial presence detect (SPD) circuit memory. The test bits stored in the SPD memory are transferred to a memory controller register (MCR) and implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write / read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.

A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability.

The invention relates to a computer system of heterogeneous hybrid memory architecture. The computer system comprises a memory unit, a non-volatile memory unit and a basic input and output system BIOS unit, wherein the memory unit comprises a first serial presence detect SPD chip and accesses the computer system through a dual inline memory module DIMM interface, and the first SPD chip comprises memory capacity information of the memory unit; the non-volatile memory unit comprises a second SPD chip and accesses the computer system through a DIMM interface, and the second SPD chip comprises memory capacity and memory type information of the non-volatile memory unit; the BIOS unit is used for acquiring capacity information of the second SPD chip at a power on self-test POST stage and then forming a system memory report by the capacity information of the second SPD chip and the memory capacity information of the memory unit. The invention further relates to a control method for the computer system and a memory detection system in the computer system. According to the computer system, the control method and the memory detection system, the whole computer system obtains a certain degree of balance on reading and writing speed and costs.

Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

The invention relates to an intelligent lightning stroke monitoring device comprising a singlechip microcomputer control unit module, an SPD (Serial Presence Detect) remote signaling monitoring unit module, a temperature detecting unit module, a lightning stroke detecting unit module and an RS485 communication unit module. According to the intelligent lightning stroke monitoring device, the singlechip microcomputer control unit module is used for controlling the SPD remote signaling monitoring unit module, the temperature detecting unit module, the lightning detecting unit module and the RS485 communication unit module; the temperature detecting unit module is initialized by the singlechip microcomputer control unit module and then can automatically work to detect the temperature of the surrounding environment, when the corresponding temperature property is detected, signals transmits data to the singlechip microcomputer control unit module in high-level digital signal codes and low-level digital signal codes, and the singlechip microcomputer control unit module judges the currently detected temperature according to the group of codes. The intelligent lightning stroke monitoring device disclosed by the invention realizes the real-time monitoring function.

A memory module includes a counter configured to count a number of commands received from a host to generate a counted number and provide the counted value to the host, a memory device configured to receive an operating frequency and an operating voltage from that host that are determined based on the counted number, and a serial presence detect (SPD) configured to store the operating frequency and operating voltage.

Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

A memory module system may include a serial presence detect (SPD) memory and a memory controller. The SPD memory may store first SPD data and second SPD data of a memory module. The SPD memory may be partitioned into at least two regions that may operate as multiple SPD ROMs. The memory controller may boot the memory module system based on a comparison between the first SPD data and the second SPD data when an initialization signal is input to the memory module system. The memory module system may be booted stably and may prevent system breakdowns.