207 results about "Low Pin Count" patented technology

A low pin count (LPC) input/output (I/O) bridge device and method for a portable computer having a plurality of legacy ports and a docking connector. The LPC I/O bridge device includes an LPC controller coupled to the legacy ports and docking connector. The LPC controller is adapted to detect whether the portable computer is coupled to a docking station via the docking connector and route data transmissions to the legacy ports, docking connector, or both, based on information received from an LPC interface. Serialization logic coupled to the LPC controller serializes data transmissions routed to the docking connector.

A method and apparatus are described for fabricating a low-pin-count chip package (701) including a die pad (706) for receiving an integrated circuit device and a plurality of connection leads (702) having recessed lead ends (704) at the outer peripheral region of each contact lead. After forming the package body (202) over the integrated circuit device, unplated portions (104) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends (302) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated (402) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

A low-pin-count non-volatile memory (NVM) embedded an integrated circuit can be accessed without any additional pins. The NVM has one or more memory cells and at least one of the NVM cells can have at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector can be coupled to a second supply voltage line and has a selecting signal. The integrated circuit can include at least one test mode detection circuit to activate a test mode upon detecting an abnormal (or out of normal) operation condition(s). Once a test mode is activated, at least one I/O or supply voltage of the integrated circuit can be used as the I/O or supply voltage of the NVM to select at least one NVM cell for read, program into nonvolatile, or volatile state. At least one NVM cell can be read during ramping of at least one supply voltage line.

A method of electrical testing electronic devices DUT, comprising: connecting at least an electronic device DUT to an automatic testing apparatus suitable for performing the testing of digital circuits or memories or of digital circuits and memories; sending electrical testing command signals to the electronic device DUT by means of the ATE apparatus; performing electrical testing of the electronic device DUT by means of at least one advanced supervised self testing system “Advanced Low Pin Count BIST” ALB which is built in the electronic device DUT, the ALB system being digitally interfaced with the ATE through a dedicated digital communication channel; and sending reply messages, if any, which comprise measures, failure information and reply data to the command signals from the electronic device DUT toward the ATE apparatus by means of the digital communication channel.

Provided is an external secondary computing device configured to monitor or control a rack-mounted computing device independently of whether the rack-mounted computing device is operating or is turned off via a low-pin-count motherboard bus independently of a baseboard management controller.

The invention discloses a high-reliability computing platform, which comprises a mainboard (1), a reliable BIOS (3) and a reliable password module (2) connected through a bus. A computer is electrified, and then the reliable password module (2) is electrified at first; the mainboard (1) is kept at a reset state by controlling a power, a clock and reset signal line, meanwhile a safety control module (4) starts a BIOS integrity measuring mechanism to ensure the reliability of the BIOS and then releases the power, the clock and the reset signal; the mainboard (1) directly accesses the BIOS chip through an LPC bus and loads the reliable BIOS (3) for normal start; the reliable BIOS (3) sequentially loads a hard disk boot sector integrity measuring unit (9) and an operating system core component integrity measuring unit (10) therein to finish the software integrity measurement; and after the measurement is successful, the operating system is normally loaded and operated. The invention ensures the safety and reliability during the computer starting process.

A system for automatically retargeting test vectors for application on tester systems having different performance capabilities is provided. The system includes a user selectable mode selector that can be adjustable between different performance modes, e.g. high, medium, and low. In high performance mode, the system allows test vectors to be applied using a high performance test system, e.g. a tester having high pin count. In low performance mode, the same test vectors can be applied but using a low performance test system, e.g. a tester having low pin count. By allowing the same test vectors to be used in a high performance or a low performance test environment, a testing facility can make maximum use of its available testing equipment for efficiently testing a device.

The embodiment of the invention provides a signal conversion device and method as well as communication equipment. The signal conversion device comprises an LPC (Low Pin Count) bus interface unit, a register configuration unit and a UART (Universal Asynchronous Receiver Transmitter) unit, wherein the LPC bus interface unit is used for performing protocol analysis on signals from an LPC bus and outputting local signals through a local bus, and the local signals comprise a control signal, an address signal and a data signal; the register configuration unit is used for configuring registers of the UART unit according to the local signals; the registers of the UART unit are allocated in a memory address space and an I/O address space; and the UART unit is used for converting data from the LPCbus into serial data according to the local signals and the values of configured registers of the UART unit and then outputting the serial data through a UART interface or outputting the serial data received by the UART interface to the LPC bus through the local signals. The embodiment of the invention can simplify the configuration process of the registers of the USRT unit.

The invention discloses a real-time server fault diagnosis method. The method is interconnected by BMC and BIOS through LPC bus, BMC and CPU are interconnected through PECI bus, BIOS and memory and PCIE devices are interconnected through SMBus and PCIE bus; BMC is interconnected through LPC bus Read the fault status of CPU, memory and PCIE devices in real time; when the BMC detects a device fault, it will trigger an interrupt in real time, and the interrupt processing process reads some specific fault status registers of the CPU through the PECI bus, and records them in the BMC storage space. The invention realizes the purpose of real-time diagnosis of server faults at the fault site, improves the hit rate of fault diagnosis, reduces the time for fault location, and effectively reduces the impact on customer services.

The present invention provides a BMC based method and system for remote diagnosis of a server startup failure. The BMC based method for remote diagnosis of a server startup failur comprises: creating a BMC detection module on a BMC by adding code, wherein the BMC detection module acquires BIOS POST Code information in real time in an interrupting manner by using an LPC bus; and the BMC detection module displaying the acquired BIOS POST Code information on a BMC remote management webpage. According to the technical scheme provided by the invention, an initialization process of each hardware device in a power-on and start-up process of a server baseboard is monitored remotely in real time, and a problem that occurs during start-up of a system can be rapidly located without the need to use a debug card, thus increasing server maintenance efficiency. Moreover, an administrator may locate the failures without going to a computer room, thereby reducing server maintenance costs and improving server maintenance efficiency.

A computer system may receive one or more credentials of a user (e.g., username, password, etc.) from an integrated circuit (IC) device carried by the user. The computer system may include an IC device interface to receive the user credential(s) from the IC device. The IC device interface may be coupled to a CPU of the computer system through a low pin count (LPC) bus. The user credential(s) may be used to grant access to software and/or to grant access to information. Access may be granted to information stored on the computer system. In some embodiments, the computer system may be coupled to a network and transmit the user credential(s) from the IC device and a request for access of information to a service provider coupled to the network. The service provider may grant or deny the request for access of information based on user credential(s).

A low pin count IC includes a wireless power receive coil, a rectifying circuit, an output circuit, circuit modules, a power management unit (PMU), a die, and a package substrate. The wireless power receive coil generates an AC voltage from a wireless power electromagnetic signal and the rectifying circuit generates a rectified voltage from the AC voltage. The output circuit generates a DC voltage from the rectified voltage. The PMU manages distribution of the DC voltage to the circuit modules. The die supports the circuit modules and the PMU, wherein the die includes return pads for coupling to circuit return nodes and a PMU return node. The package substrate supports the die and includes return pins for coupling to the return pads, wherein at least one of the die and the package substrate support the wireless power receive coil, the rectifying circuit, and the output circuit.

A memory controller with an interface for providing a connection to a plurality of memory devices at least one of said plurality of memory devices supporting burst mode data transfers comprises data interface circuitry for connecting to a plurality of separate data buses for communicating data signals between said memory controller and a respective one of said memory devices, each of said data buses providing a dedicated data signal path to a different one of said memory devices, address interface circuitry for connecting to a common address bus for communicating address signals to each of said memory devices on a shared address signal path, address signals which are directed to different ones of said memory devices being time division multiplexed together on said common address bus, and device selecting circuitry for generating one or more device selecting signals synchronised with said time division multiplexing of said common address bus to select that memory device to which address signals currently asserted on said common address bus are directed. In this way, an increased bandwidth memory controller can be provided which is efficient for both short, narrow and long and wide burst lengths and which has interface circuitry with a relatively low pin count.

A method and apparatus for low pin count firmware hub recovery on a circuit board having a firmware hub includes coupling a firmware hub recovery module having a firmware program onto the circuit board, establishing communication between a central processing unit (CPU) and the firmware hub recovery module, and reprogramming the firmware hub by the firmware program.

The invention discloses a server serial port output method and a server serial port output device. The device comprises a BMC (Baseboard Management Controller), an either-or switching chip, a serial port output switching press button and a DB9 serial port connector, wherein the input end of an LPC (Low Pin Count) decoding module of the BMC is connected with an LPC bus of a server chip group; the output end of the LPC decoding module outputs system serial port information; the output end of the LPC decoding module and the serial port output end of the BMC are respectively connected to two input ends of the either-or switching chip; the output end of the either-or switching chip is connected with the DB9 serial port connector; the serial port output switching press button is connected to the switching control end of the either-or switching chip; and the either-or switching chip is controlled to be switched between the two input ends through control signals. The server serial port output method and the server serial port output device have the advantages that the free switching between a system serial port and a BMC serial port for output can be realized only through the DB9 serial port connector; the requirements of development personnel on the system serial port and BMC serial port information are met; and the mainboard design is also simplified.

The invention discloses a system error information detection system and method for a server. The server comprises a BMC (Baseboard Management Controller) chip and a BIOS (Basic Input Output System) chip. The system error information detection method comprises the following steps of defining an error contrast relationship table between system error codes and system error information in the BMC chip; starting an LPC (Low Pin Count) bus between the BMC chip and the BIOS chip and setting a mainboard port which is used for obtaining server system starting information in the BIOS chip; obtaining system starting information of a server from a mainboard port and storing the system starting information in a system detection file through the LPC bus when the server is normally started; obtaining a system error code from the error contrast relationship table through the system detection file when the server breaks down; analyzing system error information which is corresponding to the system error code according to the error contrast relationship table in the BMC chip. The system error information detection system and method for the server can accurately, rapidly and simply obtain system fault reasons of the server to achieve system fault correction of the server as soon as possible.

The invention discloses a method and a device for expanding an LPC (linear predictive coding) peripheral on the basis of a GPIO (general purpose input/output) interface. The method includes primarily communicating the LPC peripheral with the GPIO interface of a CPU (central processing unit) on the basis of a two-way asynchronous request-acknowledge handshake protocol; forwarding received messages to the lower-level LPC peripheral by the aid of a secondary synchronous handshake protocol or interrupting operation on an internal register; reversely initiating interrupt requests to the GPIO interface of the CPU if serial interrupt requests or internal interrupt requests of the LPC peripheral are received. The device comprises a GPIO and LPC interface module, an LPC bus protocol control module and an LPC serial interrupt control module. The GPIO and LPC interface module is connected with the CPU. The method and the device have the advantages that the LPC peripheral can be expanded easily and flexibly, a system can be expanded conveniently, communication is irrelevant to particular clocks, special requirements on a clock of the GPIO interface can be omitted, communication data are reliable, hardware resources can be saved, and the method and the device are transparent for upper-layer users.