28476 results about "Bus" patented technology

A system for characterizing malicious activity in an intelligent utility grid system includes a system storage in which to store a database including a plurality of rules. A collector is operable to collect and store in the system storage information-technology (IT) data including IT-related activity from the intelligent grid system. A complex event processing (CEP) bus is operable to receive non-IT data including location-specific event data from a plurality of electronic sources, the CEP bus further operable to disregard the non-IT data failing to meet a predetermined level of relevance to one of a plurality of risk-related events. A processor is operable to apply the plurality of rules to the relevant non-IT data to: associate an undesired event with reference to the IT-related activity; and determine a probability that the undesired event is indicative of malicious activity. The processor further applies a risk characterization to the undesired event based on the probability and the IT-related activity.

An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.

Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

The invention discloses a battery managing system (BMS) testing platform comprising a testing platform main control computer, a high-precision cell voltage simulator, a high-precision large-current constant-current source, a high-precision thermotank, a battery managing system to be tested, a whole vehicle controller simulator and the like which are connected by CAN buses. The battery managing system is connected with a cell box air cooling device, a vehicle relay assembly and the like. The battery managing system testing platform can truly simulate the output state of a battery, comprising single cell voltage, total voltage, charging and discharging current, temperature and the like of the battery, can complete various communication and command functions, protection functions, battery heavy current applying process between the battery managing system and the whole vehicle, and the test and the verification on the functions of overhead protection and the like of the battery. The invention can carry out testing evaluation on the data collection precision of the battery managing system, the evaluation precision of the charge state of the battery and the like.

Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.

The invention provides a sensor probe which has: one or more microelectromechanical systems (MEMS) sensors configured to sense one or more parameters and a communication bus in electrical communication therewith. The one or more sensors and communication bus are disposed on a substrate. The sensor probe includes a digital storage module in which a unique probe identifier is stored and which is in electrical communication with the communication bus. The probe includes, a cable, a first end of which is in electrical communication with the communication bus and a second end of which is in electrical communication with a remote monitoring unit. The cable is configured to provide electrical power received from the remote monitoring unit to the one or more sensors, via the communication bus, and to communicate data received from the one or more sensors, via the communication bus, to the remote monitoring unit.

Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

An escape-code complexing method based on H.264 multi-path video includes applying fast conversion means of MPEG-2 to H.264 code and utilizing H.264 macro-block mode to select relativity to MPEG-2 motion compensation residual error as well as utilizing motion compensation residual error and MB mode as well as mapped H.264 macro-block mode obtained by MPEG-2 decoding to synthesize TS stream and to input multi-path MPEG-2 program stream to escape code complex server by SI interface through PCI bus and outputting escape-coded and complexed single H.264 video stream through PCI bus in ASI interface mode.

A multi-port adapter having a single MAC chip has reduced logic circuits for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end to a port multiplexer through an interface and at the other end to respective storage registers. The port multiplexer is coupled to the Physical Layer of each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFO's to write or read data for the selected port. At the end of the cycle, the state registers are set and stay set until selected again. The process repeats for each port in a cyclic manner. Once data is accumulated in the receive storage register, control logic reads the data of the host bus. Once space is available in the transmit storage register, the control logic writes data from the host system to the transmit storage register.

An anomaly detector for a Controller Area Network (CAN) bus performs state space classification on a per-message basis of messages on the CAN bus to label messages as normal or anomalous, and performs temporal pattern analysis as a function of time to label unexpected temporal patterns as anomalous. The anomaly detector issues an alert if an alert criterion is met that is based on the outputs of the state space classification and the temporal pattern analysis. The temporal pattern analysis may compare statistics of messages having analyzed arbitration IDs with statistics for messages having those analyzed arbitration IDs in a training dataset of CAN bus messages, and a temporal pattern is anomalous if there is a statistically significant deviation from the training dataset. The anomaly detector may be implemented on a vehicle Electronic Control Unit (ECU) communicating via a vehicle CAN bus. The anomaly detector does not rely on an database of messages and their periodicity from manufacturers (dbc files) and in that sense is truly a zero knowledge detector.

The invention relates to device diagnostics in industrial processes comprising field devices employing a field bus. A remote diagnostics device (1) is placed in connection with a process device (2), separate from the field devices and the field bus. The remote diagnostics device comprises diagnostics electronics which collects diagnostics data relating to the process device, and a transmitter part for wireless (17) transmission of the diagnostics data to a near-by field device. The field device comprises a receiver part (41) for wireless (17) reception of the diagnostics data from said remote diagnostics device (1). A field device control unit (430) analyses the received diagnostics data and transmits a diagnostics report over a field bus interface (44) and the field bus to a diagnostics computer.

In one embodiment, the system includes a host processor and a plurality of devices connected to the host processor via a USB interface. Each of the devices includes at least a processor and USB controller hardware. The host processor includes message handling logic and each of the devices also include message handling logic that is configured to cooperate with the device to prepend a communication protocol header to a message that one of the devices desires to send to the host or to another of the devices. The host processor and each of the devices are peers with respect to each other. A router located in the host processor analyzes the communication protocol header to determine whether the message is destined for the host processor or for one of the other devices.

The invention provides a set top box with a WIFI (Wireless Fidelity) module. The set top box comprises a set top box body, wherein an external USB (Universal Serial Bus) interface, a functional press key, a power supply indication lamp, a signal locking indication lamp and an SD (Secure Digital) card reader socket are arranged on a front panel of the set top box body, wherein heat dissipation holes are arranged in side plates of two ends of the set top box body; an output interface, a user interactive interface and a three-network fused interface are arranged on a rear terminal board of the set top box body; the set top box body is internally provided with a main control circuit; the main control circuit comprises a main chip, a WIFI module, a demodulator, a TS (Transport Stream) demultiplexing device, a multimedia decoder, a multimedia encoder, a flash memory, an inner memory and an input/output control circuit. According to the set top box disclosed by the invention, network transformation cost is saved and a plurality of networks are fused and accessed; meanwhile, a television program is played and Internet is accessed or three-screen interaction is realized; and after an intelligent terminal passes through WIFIAP (Wireless Fidelity Access Point) authentication in real time, the intelligent terminal can be subjected to intelligent interaction with the set top box; and the invention provides a more flexible and humanized operation manner for users.

A microcontroller includes an electrically erasable and programmable nonvolatile memory and a memory controller for controlling the nonvolatile memory. Upon writing a control program for the microcontroller and data into the nonvolatile memory pursuant to an externally provided NVM command or an internally issued program command, a CPU of the microcontroller does not intervene in controlling the nonvolatile memory. Particularly, in a programming mode set by the external program command, CPU, buses, and communication interfaces of the microcontroller are deactivated. Further, the memory controller receives a NVM command, an address and data from outside of the microcontroller for controlling an operation of the nonvolatile memory based on the NVM command and the address without intervention of the CPU.

What is described here is a system for centrally monitoring and/or controlling at least one unit for endoscopy and particularly for minimally invasive surgery, such as an insufflation means, a pump, a light source and/or a video camera, wherein the unit or units to be controlled are interconnected via interfaces.The inventive system is characterised by the combination of the following features:the units are connected via the interfaces on a self-configuring bus to a BUS master,the BUS master configures the bus automatically,the BUS master monitors the communication on the bus for correct execution.

The present invention concerns a battery monitoring system for monitoring a plurality of batteries serially connected to form a string. The battery monitoring system includes a number of probes connected to at least a portion of the string, a daisy chain bus having a select channel for serially interconnecting the probes, the bus having other, parallel channels for data communication and power, and a system server. The probes each have a sensing module and a communication module. The sensing module senses characteristics of at least a portion of the string, such as voltage or current. The communication module receives the sensed characteristics and converts them into digital form for broadcast to the system server over the bus. The communication module of the probes have a memory for storing an address assigned to the corresponding probe upon reception of an initialization signal sent by the system server via the bus.