496 results about "Link layer" patented technology

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

The invention belongs to the field of star flash mouse communication, and discloses a star flash mouse low-power-consumption communication system and method based on Polar code and SLE collaborative optimization, the system adopts a layered architecture design, collaborative optimization of energy efficiency and performance is realized through deep coupling of a physical layer and a link layer, and the performance of the system is improved. The core of the system is composed of three functional units including a Polar code coding module, an SLE control engine and a cross-layer optimization interface, and a complete closed-loop control system is formed. According to the invention, through deep cooperation of the Polar code and the SLE mechanism, the overall power consumption is reduced by 42.7% compared with the traditional scheme; according to the Polar code dynamic construction method based on track prediction, an ultra-low bit error rate of 10 <-5 > magnitude can still be kept in a 2.4 GHz complex interference environment, and in combination with signal-to-noise ratio self-adaptive coding parameter adjustment, it is ensured that transmission delay within 0.5 ms is always kept from a low-speed office scene to a high-speed electronic sports scene; in the aspect of engineering implementation, the method has the capability of quickly adapting to hardware platforms of different manufacturers, and a complete solution with high performance and low cost is provided for large-scale commercial use of the satellite flash technology in the consumer electronics field.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention discloses a PCIe (Peripheral Component Interconnect Express) switching chip for realizing calculation in transmission, a switch with the PCIe switching chip and a communication system with the PCIe switching chip, the switching chip comprises a physical layer, a data link layer, a transaction layer and a calculation module, and is used for responding to the condition that a specific prefix of a transaction layer data packet is analyzed by the transaction layer and carries a preset calculation instruction; if yes, the calculation module analyzes the calculation instruction analyzed by the transaction layer so as to extract a calculation parameter field in the calculation instruction; the calculation module generates and executes a task of calculating the data in transmission according to the calculation parameter field, and calculation does not need to be started after all the data to be calculated are in place; firstly, part of the currently received data to be calculated is calculated to obtain an intermediate calculation result; and aggregating the subsequent newly received data to be operated and the intermediate operation result. According to the invention, by inserting the programmable calculation path into the PCIe switch, an innovative mechanism of'transmission while calculation 'is realized, the system delay is reduced, and the bandwidth occupation is reduced.

The invention belongs to the field of PCIe (Peripheral Component Interconnect Express) chips, and relates to a CXL switching chip of a multi-core-grain architecture and a cross-core-grain routing switching method thereof, and a plurality of CXL switching core grains with uniform specifications are packaged and interconnected to form the CXL switching chip; each CXL switching core particle comprises a plurality of ports, each port can be configured to be in a CXL mode and a D2D mode, and the port of each CXL switching core particle at least comprises a physical layer, a CXL link layer, a CXL transaction layer, a D2D routing layer, a bypass and a multipath selection module; the CXL switching chip further comprises a multi-VC on-chip CXL switching network, and the multi-VC on-chip CXL switching network comprises at least one order-preserving switching VC and one out-of-order switching VC. According to the method, CXL switching chips of various specifications can be flexibly constructed, the design complexity and verification difficulty of the large-scale or multi-port CXL switching chips are effectively reduced, and the production yield of the chips is improved.

The invention discloses a method and a system for verifying the reliability of remotely acquired data of an electric meter box, particularly relates to the technical field of communication and data transmission, and aims to solve the problem that the reliability of the remotely acquired data of the electric meter box is verified without changing an existing netmeter and a communication protocol. The invention aims to solve the problem of how to execute cross-layer reviewable reliability verification and quantitative credibility evaluation on a single reading result remotely acquired by an electric meter box so as to identify and eliminate the abnormity that communication is successful but data is not credible in real time, and support source end positioning. By introducing fusion of a cross-layer evidence set and an active detection mechanism, the credibility of each copying and reading result can be comprehensively evaluated. Multi-level data of a physical layer, a link layer, an application layer and the like are verified, and data exception is identified through active detection. Through the mechanisms, the method can effectively eliminate reading results which succeed in communication but have errors in actual data, thereby ensuring that the collected data are more reliable and accurately reflect the actual state of the electric meter.

The invention provides an optimized kernel network and an implementation method thereof, and relates to the technical field of kernel networks, the kernel network comprises a fast data channel component XDP arranged on a data link layer; when the network card equipment receives a message data packet, the XDP analyzes and filters the received data packet, or encapsulates or de-encapsulates the received data packet, and modifies a field to forward the data packet; and the XDP matches and filters the received data packet with the rules in the BPF Maps, and discards the data packet when the data packet is illegal. The method comprises the steps that hardware initialization comprises the step of adding a zero copy processing flow when an NAPI polling point processing function is added; the application program configures an XDP socket; the xsk unit executes a BPF instruction, calls a network card driving unit to configure an XSK cache pool, and establishes a DMA mapping relationship between the device and the UMEM shared cache; and the network card drives zero-copy receiving and receiving of the data packet. According to the invention, the kernel network communication efficiency is improved.

This disclosure relates to method, device, and system for data transmission between network nodes of a network. The method may include receiving, by a processing node, a Link Layer Discovery Protocol (LLDP) frame from each network node of the plurality of network nodes. The method may further include extracting, by the processing node, information related to each interface and port available in the plurality of network nodes from the LLDP frame. The method may further include transmitting, by the processing node, the information in a single data packet to an Access Point (AP) node of the distributed network.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

According to the PCIe Switch system and the PCIe switch, a PCIe hardware IP is used as a bottom layer, and a basic PCIe interface function for physical layer and link layer management is provided; and identifying and configuring all connected devices to construct a device address routing mapping table through a Soft Switch IP mounted on the PCIe hardware IP, and determining a specific target of data transmission based on the constructed mapping table so as to route the data to a specific position of the corresponding device. According to the invention, flexible equipment enumeration can be carried out by selecting a pure hardware mode or a software and hardware combined mode according to actual requirements, so that the data can be correctly and efficiently transmitted to the target endpoint from the source equipment, and the complex problems of address resolution and routing management are solved. Compared with the prior art, the method can replace the existing PCIe Switch IP of a manufacturer, provides higher flexibility and expansibility, obtains better balance in the aspect of cost control, and is suitable for various applications needing large-scale PCIe equipment connection, virtualization and high-speed data exchange.

The invention discloses a satellite-ground convergence network switching method, which comprises the following steps of: operating double protocol stacks of a 5G protocol stack and a satellite communication protocol stack in parallel in a user terminal embedded environment, maintaining active connection of double link layers, and acquiring a parameter set in real time through a multi-dimensional link quality monitoring module; inputting the parameter set into an embedded prediction model, and predicting whether the current network quality is lower than a first quality threshold in a specific time window based on a historical link degradation mode and a real-time change trend; when the prediction triggering condition is satisfied, the encrypted context information group is pre-synchronized to the target network control entity through the security signaling channel of the current service network immediately; when it is monitored that the actual link quality is reduced to a second quality threshold value, the pre-synchronized context information group is directly activated to execute atomization switching operation, and it is ensured that the end-to-end switching time delay is controlled within a preset time delay range; according to the method, instantaneous seamless switching of the network is finally realized, and high-real-time service transmission reliability is ensured.

The invention discloses a digital aeronautical communication system design based on a cellular-free network architecture, which belongs to the technical field of aeronautical communication and comprises an aeronautical communication system and a communication service execution module. The aeronautical communication system comprises a network infrastructure and a communication link layer and is responsible for providing underlying physical connection and transmission environment support. The communication service execution module covers a network protocol and information interaction and task execution process; the network infrastructure adopts distributed AP topology planning, airport and route area APs are deployed in a differentiated manner, and parameters are dynamically adjusted in combination with a three-dimensional coverage optimization model; and software and hardware modules comprise ground APs and airborne terminals, so that the problems caused by high-speed movement are solved. The communication link layer carries out multi-dimensional channel modeling, and LDPC code coding and dynamic cluster generation are adopted. The working process comprises the steps of initialization, cluster construction, state monitoring and the like, stable communication in the whole flight process is achieved, and the aviation communication efficiency and safety are improved.

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

The invention discloses a video data transmission method and system based on an FPGA, and relates to data transmission. The method comprises the steps that a video data stream is acquired, and a time sequence signal of the video data stream is analyzed; writing the parallel data into an external memory to form a frame buffer area; packaging the read video data into a data packet meeting a USB3.2 transmission protocol; packaging the data packet based on a USB3.2 link layer protocol; and converting the USB3.2 protocol transmission frame into a differential signal, and transmitting video data in the USB3.2 protocol transmission frame according to the differential signal. In view of data loss caused by mismatching of a video input rate and a USB output rate in the prior art, by establishing an annular buffer structure and adopting a dynamic pointer management and waterline threshold monitoring mechanism, rate adaptive matching of a video data stream is realized, and continuous and stable transmission of video data is ensured.

The invention belongs to the field of computer networks, data compression and mobile internet and wireless communication, and discloses a TCP (Transmission Control Protocol) data packet compression and aggregation self-adaption method, which comprises the following steps of: 1, receiving a TCP data packet and separating a header from a payload; step 2, storing the effective load part; step 3, compressing the head and updating context data according to the serial number, the confirmation number, the mark and the window size field of the head; step 4, combining the compressed header with the effective load to obtain a compressed message; 5, extracting the compressed messages according to a set aggregation threshold value, aggregating the compressed messages, and sending the aggregated compressed messages to a data link layer; and step 6, storing the operation records, comparing the operation records with the previous N operation records, and changing a set aggregation threshold according to a comparison result. According to the invention, the message can be efficiently processed under the condition of a complex network, so that the overall network throughput and the message processing efficiency are improved.

The invention provides a wind turbine generator master control system software and hardware security and credibility mutual recognition measurement mechanism and method, and relates to the field of wind turbine generator control, and the method comprises the following steps: carrying out the hierarchical division of a wind turbine generator master control system, and carrying out the behavior measurement of all hierarchies according to the division result; the method comprises the following steps of: performing hierarchical bidirectional authentication on each hierarchy of a main control system of a wind turbine generator by combining a data link layer encryption technology on the basis of a cross-hierarchy credible mutual recognition mechanism; based on a cross-equipment-level credible mutual recognition mechanism, carrying out equipment-level identity bidirectional authentication between a main control system and a peripheral system of the wind turbine generator; and the change conditions of the behavior measurement result, the hierarchical authentication result and the equipment-level authentication result are tracked in real time, the credible state of the main control system of the wind turbine generator is evaluated, and a response strategy is dynamically executed according to the evaluation result. According to the method, the security problems of hardware tampering, software malicious injection, cross-device communication hijacking and the like can be solved, and meanwhile, the industrial control requirements of real-time performance and low resource occupation are met.

The invention discloses a satellite network encrypted traffic preprocessing method and system under multi-feature fusion, and the method comprises the steps: cooperatively processing original traffic data from two dimensions of a data packet level and a session level: at the data packet level, deleting an invalid TCP control segment and a TLS / DNS key exchange segment to eliminate redundancy, and removing a data link layer header to reduce interference; anonymization mask processing is carried out on an IP header to prevent overfitting, data normalization and standardization operations are executed to balance the feature scale, and meanwhile the data length is unified through truncation and zero filling strategies; in a session level, session splitting is carried out based on a quintuple sharing a source IP, a target IP, a port number and a protocol, statistical features such as the total number of data packets and session duration are extracted to capture time sequence association, and feature vectorization is realized by adopting Min-Max normalization. The double-layer fusion mechanism effectively combines data packet level microscopic fine-grained features with session level macroscopic context information to jointly improve the accuracy of encrypted traffic classification and the model generalization ability.

The invention relates to the technical field of integrated circuits and distributed computing, in particular to a chip computing network-oriented clock synchronization method, which is convenient for a receiving end to quickly identify and reduce analysis overhead by customizing a simplified synchronization frame format. A hardware synchronization module is deployed between a physical layer and a link layer to record a high-precision timestamp to eliminate an error caused by protocol stack processing, and a slave node calculates clock skew based on timestamp information interacted by a master node and a slave node and corrects the clock skew in real time to realize accurate synchronization. Master-slave roles are independently configured through each communication port, and automatic topology discovery is supported to adapt to a complex network structure. According to the method, an existing routing protocol and a physical link of the chip are reused, hardware overhead is reduced, synchronization precision is high, flexibility is high, the method can be widely applied to a computing network formed by an artificial intelligence acceleration chip graphics processor, a data processor and the like, and multi-chip cooperative computing efficiency and data consistency are effectively improved.

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

The invention provides an EtherCAT protocol fault injection test system and method. Comprising a management control module used for generating a fault injection configuration and control instruction; the simulation slave station module is used for establishing a register and interface model of a slave station controller, generating a virtual slave station topology according to a network configuration file and communicating with the master station; the multi-level fault injection engine is used for implementing injection in a link layer and an application layer according to fault injection configuration; a trigger control unit for determining a trigger condition according to a communication state transition, an initialization command, a specific mailbox transaction, a frame count, or a time window; the injection execution unit is used for presetting hanging points of message generation and analysis, storage mapping and synchronous management processing and object dictionary access and file transmission processing; and the test arrangement and judgment module is used for judging the receipt record and the state of the master station according to a preset rule and outputting a judgment result. According to the invention, multi-level accurate fault injection, automatic replayable testing and unified observation determination can be realized.

The embodiment of the invention provides a quantum security encryption equipment assembly for a novel electric power communication architecture, and belongs to the technical field of communication encryption. Comprising a power quantum encryption module which is designed to be in a plugging form and is directly deployed in a network communication link of a receiving party and a transmitting party in a novel power communication architecture so as to carry out encryption protection on data in a link layer of an OSI network model; and the anti-quantum zero-trust security suite is deployed between a sensing layer node or a tail end of the novel electric power communication architecture and a platform / application layer communication access end, in the data transmission process, data is encrypted through the electric power quantum encryption module firstly, and then identity authentication and access control are performed through the anti-quantum zero-trust security suite. According to the assembly, the security encryption of the power communication system can be realized under the condition that the original network structure is not changed.

The invention provides a bus link layer, an on-chip bus and a chip, and relates to the technical field of chip design and manufacture, and the bus link layer comprises an upstream virtual channel distributor which is used for determining an upstream virtual channel based on a credit value of each virtual channel; the upstream virtual channel memory is used for receiving the target data sent by the upstream module and storing the target data to a storage space corresponding to an upstream virtual channel; the downstream virtual channel distributor is used for determining a downstream virtual channel based on the credit value of each virtual channel; and the downstream virtual channel memory is used for storing the target data to a storage space corresponding to a downstream virtual channel and sending the target data to a downstream module. According to the device provided by the invention, the upstream module and the downstream module do not need to integrate and manage a huge storage array, so that the overall layout and wiring of the chip are more flexible, the time sequence convergence is easier, and the design complexity and the physical implementation difficulty of the chip are remarkably reduced.

The invention belongs to the field of vehicle trajectory tracking control, and discloses an intelligent vehicle trajectory tracking control method and system based on differential programming, and the method comprises the steps: constructing a vehicle dynamics model; a reference trajectory time-varying curvature is introduced, delay of a steering execution mechanism is expressed as pure delay plus a first-order inertia link, and construction of a road tracking model is completed; assuming that the system is in a steady state, calculating reference values of a state quantity and a control quantity; constructing an MPC optimization problem, converting the MPC optimization problem into a QP problem, and calculating to obtain an MPC loss value; constructing a differential programming training calculation network diagram; a hypercube is used for sampling the state quantity of a vehicle, the driving speed and the time-varying reference items of a road, and construction of a network training initial state data set is completed; carrying out MPC trajectory tracking task integration, and constructing a physical model in network training; using a full-link layer network, adding tire slip angle soft constraints, completing the construction of a strategy network, carrying out end-to-end network training, and completing the control of a turning angle instruction. According to the method, the MPC online solving optimization problem can be avoided.

Provided in the present invention is a low-latency redundant communication protocol based on an improved PRP, which protocol is compatible with the PRP standard of IEC 62439-3-2016 and operates at a link layer. Two redundant ports are connected to an upper-layer protocol by means of a link redundancy entity, and are transparent to the upper-layer protocol; a network-end node has two or three redundant network ports, which are respectively connected to networks that are independent of each other and have the same topological structure, and the networks operate in parallel; and network ports belonging to PRP-supporting end nodes are configured with the same IP address and MAC address. The improvements in the present invention are as follows: a redundancy discarding algorithm is modified to a mode of directly uploading a first-arriving communication frame to an application layer; {source IP address, source MAC address and frame sequence number} is used as a determination condition for a redundant frame; by means of file pre-configuration, the IP address of a single-network-port node in a network is written into a configuration file in advance in a node; and statistics for the number of network port link up / down events, out-of-receive-window statistics, statistics for non-sequential frame sequence numbers, and statistics for the number of out-of-sync redundant frames are added.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

A method for transmitting secured Ethernet frames on a communication line, the method including the following in a transmitter module: receiving an Ethernet frame comprising payload data from a network layer; retrieving a secure policy, defining the type of security to be applied to the Ethernet frame; producing an initialization vector based on an encryption counter and a physical address of the transmitter module; creating an authentication tag by applying an authentication algorithm on the secure policy, the initialization vector and the payload data using a shared key and the initialization vector; adding the secure policy, the initialization vector and the authentication tag to the payload data to create a secured Ethernet frame; and sending the secured Ethernet frame to a data link layer for transmission on the communication line.

The invention belongs to the technical field of intelligent building automation communication, and discloses a KNX protocol hierarchical communication system and method, and the system comprises a microcontroller subsystem and a main control subsystem. The main control subsystem runs a standard Linux operating system and deploys a standard KNX protocol stack, the standard KNX protocol stack comprises a link layer, a network layer, a transmission layer and an application layer and provides a standard programming interface for upper-layer application, and a Web server running on the same Linux system calls the standard programming interface to process KNX communication; the microcontroller subsystem is used for realizing a physical layer function of a KNX protocol; the master control subsystem is connected with the microcontroller subsystem through a USB interface, and the USB interface adopts a private protocol to carry out data transmission. By decoupling a hardware processing layer and a software protocol part, the overall architecture of hierarchical communication is used as a KNX equipment communication node, a complex algorithm can be realized, a bus signal can be responded at a microsecond-level speed, and completeness and reliability of data transmission are ensured by constructing a self-defined private protocol.

The invention discloses an automatic testing device and method for a self-defined bus of a DCS, and belongs to the technical field of testing of industrial control systems.The device comprises a controller, an FPGA module, an adapter module, a main control case and a bus adapter card, the FPGA module serves as a lower computer to execute physical layer and data link layer processing of a communication protocol, and achieves electrical matching with a DCS custom bus through an adapter. A customized backboard and a bus adapter card are arranged in the main control case and are used for connecting a to-be-tested main control card, an I / O card and a communication card; the method is based on a layered protocol architecture, LVDS signal transmission and 4B / 5B coding are adopted in a physical layer, CRC32 verification and frame packaging are carried out in a data link layer, and node simulation, message framing, fault insertion and state monitoring are completed in an application layer. The method can effectively solve the problem that the private protocol bus lacks general testing means, and has high expandability and deep testing capability.

The invention belongs to the technical field of industrial control, and discloses an industrial control virtual equipment resource pool construction method, system, equipment and medium, and the method comprises the steps: optimizing parameters of a transition probability and an observation probability in a time sequence data statistical algorithm according to time sequence characteristics of an industrial control scene, and extracting resource characteristics; generating a virtual resource model, and constructing a bidirectional mapping table of physical resources and virtual resources; optimizing a clustering algorithm by using a time weight factor, dynamically aggregating the time sequence metadata in combination with a streaming computing framework, and performing anomaly detection on a resource state in combination with the aggregated time sequence metadata based on an anomaly detection technology; based on a layered decoupling flattening architecture, a resource pool is divided into a resource layer, a data layer, a link layer, a technical support layer and an interface layer. According to the method, logic-physical layered decoupling of the industrial control resource pool is realized, seamless access and dynamic optimal distribution of multi-protocol equipment are supported, and high-reliability and low-delay bottom support is provided for users.