362 results about "Link layer" patented technology

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention discloses a PCIe (Peripheral Component Interconnect Express) switching chip for realizing calculation in transmission, a switch with the PCIe switching chip and a communication system with the PCIe switching chip, the switching chip comprises a physical layer, a data link layer, a transaction layer and a calculation module, and is used for responding to the condition that a specific prefix of a transaction layer data packet is analyzed by the transaction layer and carries a preset calculation instruction; if yes, the calculation module analyzes the calculation instruction analyzed by the transaction layer so as to extract a calculation parameter field in the calculation instruction; the calculation module generates and executes a task of calculating the data in transmission according to the calculation parameter field, and calculation does not need to be started after all the data to be calculated are in place; firstly, part of the currently received data to be calculated is calculated to obtain an intermediate calculation result; and aggregating the subsequent newly received data to be operated and the intermediate operation result. According to the invention, by inserting the programmable calculation path into the PCIe switch, an innovative mechanism of'transmission while calculation 'is realized, the system delay is reduced, and the bandwidth occupation is reduced.

The invention belongs to the field of PCIe (Peripheral Component Interconnect Express) chips, and relates to a CXL switching chip of a multi-core-grain architecture and a cross-core-grain routing switching method thereof, and a plurality of CXL switching core grains with uniform specifications are packaged and interconnected to form the CXL switching chip; each CXL switching core particle comprises a plurality of ports, each port can be configured to be in a CXL mode and a D2D mode, and the port of each CXL switching core particle at least comprises a physical layer, a CXL link layer, a CXL transaction layer, a D2D routing layer, a bypass and a multipath selection module; the CXL switching chip further comprises a multi-VC on-chip CXL switching network, and the multi-VC on-chip CXL switching network comprises at least one order-preserving switching VC and one out-of-order switching VC. According to the method, CXL switching chips of various specifications can be flexibly constructed, the design complexity and verification difficulty of the large-scale or multi-port CXL switching chips are effectively reduced, and the production yield of the chips is improved.

The invention provides an optimized kernel network and an implementation method thereof, and relates to the technical field of kernel networks, the kernel network comprises a fast data channel component XDP arranged on a data link layer; when the network card equipment receives a message data packet, the XDP analyzes and filters the received data packet, or encapsulates or de-encapsulates the received data packet, and modifies a field to forward the data packet; and the XDP matches and filters the received data packet with the rules in the BPF Maps, and discards the data packet when the data packet is illegal. The method comprises the steps that hardware initialization comprises the step of adding a zero copy processing flow when an NAPI polling point processing function is added; the application program configures an XDP socket; the xsk unit executes a BPF instruction, calls a network card driving unit to configure an XSK cache pool, and establishes a DMA mapping relationship between the device and the UMEM shared cache; and the network card drives zero-copy receiving and receiving of the data packet. According to the invention, the kernel network communication efficiency is improved.

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

The invention discloses a video data transmission method and system based on an FPGA, and relates to data transmission. The method comprises the steps that a video data stream is acquired, and a time sequence signal of the video data stream is analyzed; writing the parallel data into an external memory to form a frame buffer area; packaging the read video data into a data packet meeting a USB3.2 transmission protocol; packaging the data packet based on a USB3.2 link layer protocol; and converting the USB3.2 protocol transmission frame into a differential signal, and transmitting video data in the USB3.2 protocol transmission frame according to the differential signal. In view of data loss caused by mismatching of a video input rate and a USB output rate in the prior art, by establishing an annular buffer structure and adopting a dynamic pointer management and waterline threshold monitoring mechanism, rate adaptive matching of a video data stream is realized, and continuous and stable transmission of video data is ensured.

The invention relates to the technical field of integrated circuits and distributed computing, in particular to a chip computing network-oriented clock synchronization method, which is convenient for a receiving end to quickly identify and reduce analysis overhead by customizing a simplified synchronization frame format. A hardware synchronization module is deployed between a physical layer and a link layer to record a high-precision timestamp to eliminate an error caused by protocol stack processing, and a slave node calculates clock skew based on timestamp information interacted by a master node and a slave node and corrects the clock skew in real time to realize accurate synchronization. Master-slave roles are independently configured through each communication port, and automatic topology discovery is supported to adapt to a complex network structure. According to the method, an existing routing protocol and a physical link of the chip are reused, hardware overhead is reduced, synchronization precision is high, flexibility is high, the method can be widely applied to a computing network formed by an artificial intelligence acceleration chip graphics processor, a data processor and the like, and multi-chip cooperative computing efficiency and data consistency are effectively improved.

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

The invention belongs to the field of vehicle trajectory tracking control, and discloses an intelligent vehicle trajectory tracking control method and system based on differential programming, and the method comprises the steps: constructing a vehicle dynamics model; a reference trajectory time-varying curvature is introduced, delay of a steering execution mechanism is expressed as pure delay plus a first-order inertia link, and construction of a road tracking model is completed; assuming that the system is in a steady state, calculating reference values of a state quantity and a control quantity; constructing an MPC optimization problem, converting the MPC optimization problem into a QP problem, and calculating to obtain an MPC loss value; constructing a differential programming training calculation network diagram; a hypercube is used for sampling the state quantity of a vehicle, the driving speed and the time-varying reference items of a road, and construction of a network training initial state data set is completed; carrying out MPC trajectory tracking task integration, and constructing a physical model in network training; using a full-link layer network, adding tire slip angle soft constraints, completing the construction of a strategy network, carrying out end-to-end network training, and completing the control of a turning angle instruction. According to the method, the MPC online solving optimization problem can be avoided.

Provided in the present invention is a low-latency redundant communication protocol based on an improved PRP, which protocol is compatible with the PRP standard of IEC 62439-3-2016 and operates at a link layer. Two redundant ports are connected to an upper-layer protocol by means of a link redundancy entity, and are transparent to the upper-layer protocol; a network-end node has two or three redundant network ports, which are respectively connected to networks that are independent of each other and have the same topological structure, and the networks operate in parallel; and network ports belonging to PRP-supporting end nodes are configured with the same IP address and MAC address. The improvements in the present invention are as follows: a redundancy discarding algorithm is modified to a mode of directly uploading a first-arriving communication frame to an application layer; {source IP address, source MAC address and frame sequence number} is used as a determination condition for a redundant frame; by means of file pre-configuration, the IP address of a single-network-port node in a network is written into a configuration file in advance in a node; and statistics for the number of network port link up / down events, out-of-receive-window statistics, statistics for non-sequential frame sequence numbers, and statistics for the number of out-of-sync redundant frames are added.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

A method for transmitting secured Ethernet frames on a communication line, the method including the following in a transmitter module: receiving an Ethernet frame comprising payload data from a network layer; retrieving a secure policy, defining the type of security to be applied to the Ethernet frame; producing an initialization vector based on an encryption counter and a physical address of the transmitter module; creating an authentication tag by applying an authentication algorithm on the secure policy, the initialization vector and the payload data using a shared key and the initialization vector; adding the secure policy, the initialization vector and the authentication tag to the payload data to create a secured Ethernet frame; and sending the secured Ethernet frame to a data link layer for transmission on the communication line.

The invention belongs to the technical field of intelligent building automation communication, and discloses a KNX protocol hierarchical communication system and method, and the system comprises a microcontroller subsystem and a main control subsystem. The main control subsystem runs a standard Linux operating system and deploys a standard KNX protocol stack, the standard KNX protocol stack comprises a link layer, a network layer, a transmission layer and an application layer and provides a standard programming interface for upper-layer application, and a Web server running on the same Linux system calls the standard programming interface to process KNX communication; the microcontroller subsystem is used for realizing a physical layer function of a KNX protocol; the master control subsystem is connected with the microcontroller subsystem through a USB interface, and the USB interface adopts a private protocol to carry out data transmission. By decoupling a hardware processing layer and a software protocol part, the overall architecture of hierarchical communication is used as a KNX equipment communication node, a complex algorithm can be realized, a bus signal can be responded at a microsecond-level speed, and completeness and reliability of data transmission are ensured by constructing a self-defined private protocol.

A data processing method, a communication device, and a computer readable storage medium, the data processing method comprising: acquiring data of at least one service, the at least one service comprising a first service; processing the data of the first service by using a packet data convergence protocol (PDCP) entity corresponding to the first service to obtain a first service data unit, the PDCP entities corresponding to different services being different; a first protocol data unit is generated based on the first service data unit, the first protocol data unit comprises first indication information, and the first indication information is at least used for indicating the first service; and submitting the first protocol data unit to a radio link layer control (RLC) entity so as to send the first protocol data unit. According to the scheme provided by the invention, the security of the data of the data surface can be improved while the data transmission requirement of the data surface is met.

The invention provides a low-delay real-time analysis architecture and analysis method of a PCIe protocol, belongs to the technical field of integrated circuit chip design, and aims at solving the problems that a traditional software analysis scheme is low in throughput and high in delay, and a special protocol analyzer is high in cost and poor in integration level. The analysis architecture comprises a data preprocessing module, a parallel 8b / 10b decoding module, a parallel descrambling module and an analysis state machine. The analysis method comprises the following steps: S1, data preprocessing; s2, decoding the data in parallel; s3, descrambling the data in parallel; s4, data clock synchronization; and S5, data analysis. According to the method, PCIe 2.0 full protocol stack analysis can be realized, real-time analysis of 5GT / s physical layer, data link layer and transaction layer data is supported, the end-to-end processing delay is only 70 ns, the low delay characteristic enables engineers to observe protocol behaviors in real time and locate data packet errors in time in the debugging process, and the debugging efficiency and accuracy are greatly improved.

The invention discloses an OFDM (Orthogonal Frequency Division Multiplexing) communication channel estimation and signal detection method and system, and belongs to the technical field of channel estimation. The OFDM communication channel estimation and signal detection method comprises the following steps: receiving an LDACS downlink OFDM baseband signal; pilot frequency and data subcarriers are separated; arranging pilot frequency observation into a time sequence block according to a frequency index, and constructing a channel estimation subnet input tensor; performing convolution feature extraction and LSTM (Long Short Term Memory) time sequence modeling on the pilot frequency time sequence block in sequence, and outputting channel estimation of each subcarrier; performing frequency domain equalization on the data subcarriers; the signal detection subnet firstly extracts time sequence features through LSTM, then distributes weights through a self-attention mechanism, and finally outputs bit judgment through full connection; performing parameter optimization on the channel estimation subnet and the signal detection subnet by adopting a two-stage training strategy; the number K of subcarriers, the number P of pilots, the CP length and subcarrier mapping are set according to an LDACS frame structure and a protection interval, and an LDACS link layer interface is directly connected. By adopting the OFDM communication channel estimation and signal detection method and system provided by the invention, the problems of poor estimation precision and insufficient robustness of the existing method in a complex LDACS airspace channel environment can be solved.

The invention belongs to the field of computer system compatibility and peripheral interfaces, and relates to a domestic desktop terminal peripheral compatibility method and system based on protocol reverse mapping and a computer readable storage medium. According to the method, after peripheral access, three-layer analysis of physical layer signal reversal, data link layer structure reversal and application layer semantic reversal is carried out in sequence, and an equipment interface type, a frame structure and instruction semantics are dynamically identified. And based on the reverse result, dividing the equipment into a standard protocol or a private protocol through a protocol type decision, respectively routing the protocol to a drive straight-through module or an instruction translation executor for processing, and finally providing compatible services for a domestic service system through a unified virtual equipment interface. According to the method, the adaptation problem of a document-free private protocol is solved, plug and play of a Wintel peripheral by a non-x86 architecture domestic terminal is achieved, the protocol compatibility coverage rate is remarkably increased, meanwhile, the CPU occupancy rate is reduced, and the harsh requirement for millisecond response of specific industries such as electric power is met.

The invention relates to a UDP communication fault diagnosis and recovery method based on protocol stack health degree multi-dimensional perception, and belongs to the technical field of embedded systems and computer network communication. According to the method, aiming at a difficult fault that Ping communication is carried out between devices but UDP applications cannot carry out communication, an internal state of a network protocol stack is actively sensed through a built-in diagnosis agent module, and a traditional external packet capturing means is replaced. The diagnosis process comprises the steps of link layer reachability verification, protocol stack load channel detection, Socket interface state auditing and memory pool and task health degree inspection. The system constructs a protocol stack health degree vector through multi-dimensional sensing data, and performs fault mode matching based on a preset rule base. Once the fault root cause is positioned, the system can automatically trigger a repair action or report an accurate alarm. According to the invention, through automatic and intelligent diagnosis and self-healing embedded in the system, the reliability and maintainability of the embedded network equipment are greatly improved.

This application belongs to the field of channel coding technology. This application provides a WSC-assisted encoding and decoding method for PC-Polar codes. The embodiments disclosed herein can be used in any communication system employing PC-Polar codes with minimal impact on the overall design of the communication system. By assisting in the verification of multiple candidate paths, the correct path can be identified more accurately, resulting in additional coding gain compared to PC-Polar codes in simulations. The PC-Polar code is endowed with link-layer frame error detection and indication functions, allowing the system to definitively determine whether the decoding result is correct, thus enhancing the reliability of the communication system. The introduced WSC coding has low code rate loss overhead, low computational complexity, and is easy to implement in hardware, achieving a good balance between performance gain and overhead.

This disclosure relates generally to configuring a legacy application or service with a reconfigurable cryptographic provider capable of leveraging many different cryptographic algorithms, protocols or functions. The application or service can be configured with the reconfigurable cryptographic provider by redirecting cryptographic API calls intended for a linked static shared cryptographic library or provider to a cryptographic adapter configured to emulate responses provided by the linked static shared cryptographic library. A cryptographic adapter is also described and is configured to generate abstracted versions of the cryptographic API calls and pass them on to the reconfigurable cryptographic provider, which selects and implements an appropriate cipher solution based on the abstracted cryptographic API calls.

The invention relates to the technical field of network security and information, in particular to an Agent surveying and mapping method and system for isolating network blind area asset discovery, and the method comprises the steps: deploying an Agent at a terminal, collecting local data including an ARP cache, a network connection table, a hardware fingerprint and a behavior portrait, and encrypting and uploading the local data. The main control center performs asset deduplication and identity verification based on hardware fingerprints, processes connection data by using a time window alignment and session continuity analysis algorithm to solve association ambiguity caused by time sequence dislocation and temporary connection, and establishes a cross-Agent connection relationship with high confidence. And finally fusing the connection relation and behavior portrait data, and incorporating the data into unmanaged assets found by a link layer to synthesize a global asset topology of a cross-logic network segment. According to the method, the coverage rate, the identification accuracy and the real-time performance of asset discovery in a complex isolation network environment are improved, and meanwhile, the interference risk of a scanning process on a service network is eliminated.

The invention relates to the technical field of connector data transmission, in particular to a transmission data integrity detection method in the flight process of an unmanned aerial vehicle. The method comprises the following steps: acquiring state data of a connector in a flight process of the unmanned aerial vehicle and real-time transmission state data of a link layer and an application layer in a data transmission process; determining an environmental influence factor of the connector based on the state data; analyzing the change of the environmental influence factor, and determining a degradation trend coefficient; determining a real-time data transmission state coefficient in combination with the real-time transmission state data; weighting the real-time data transmission state coefficient through the degradation trend coefficient to obtain a data transmission loss degree; and obtaining a transmission integrity evaluation index of the connector according to the data transmission loss degree and the data accumulation loss amount. According to the invention, the timeliness of abnormal positioning and repairing in the data transmission process is improved, and the transmission loss rate of the unmanned aerial vehicle data is reduced.

The invention relates to a VxWorks system network fault positioning method based on hierarchical diagnosis and cross validation, and belongs to the technical field of embedded network fault diagnosis. The method is suitable for an embedded device of a VxWorks system to quickly distinguish a local network card fault and a remote switch fault in a network disconnection scene, and accurate diagnosis of a network fault in the VxWorks system is realized through layered fault isolation and cross validation of a physical layer, a link layer and a network device layer. The network fault diagnosis and positioning method provided by the invention is suitable for systems of various versions of VxWorks, the fault positioning accuracy of a physical layer can reach 98% or above, and the fault positioning accuracy of a driving layer can reach 96% or above.

The invention provides an automatic networking method for a train communication network and a storage medium. The method comprises the following steps: a management center reads a networking planning file and constructs a logical topology; based on a link layer discovery protocol, the management center interacts with managed equipment to construct a physical topology; if the physical topology is matched with the logical topology, the management center establishes network configuration protocol connection with the managed equipment; the management center distributes automatic networking configuration data to the managed equipment; and based on a publishing and subscribing mode, the management center performs state monitoring on the managed equipment.

This application provides a packet forwarding method and device. The method involves: determining whether to perform Layer 3 forwarding based on the destination MAC address of the Ethernet packet (which is the gateway MAC address); searching the link layer address mapping table based on the destination IP address of the inner IP packet of the Ethernet packet; obtaining a new destination MAC address from the matching link layer address mapping table entry when a matching entry for the destination IP address is found; searching the MAC address table based on the new destination MAC address; obtaining the outgoing port and outgoing VLAN from the matching entry when a matching entry for the new destination MAC address is found; modifying the destination MAC address, source MAC address, and incoming VLAN of the Ethernet packet to the new MAC address, gateway MAC address, and outgoing VLAN, respectively; and sending the modified Ethernet packet through the outgoing port.

The application belongs to the field of computer system compatibility and peripheral interface, and relates to a domestic desktop terminal peripheral compatibility method and system based on protocol reverse mapping and a computer readable storage medium. After the peripheral is accessed, the method sequentially performs three-layer analysis of physical layer signal reverse, data link layer structure reverse and application layer semantic reverse, dynamically identifies device interface type, frame structure and instruction semantics. Based on the reverse result, the device is divided into standard protocol or private protocol through protocol type decision, and is routed to a drive pass-through module or an instruction translation executor for processing, respectively, to finally provide compatibility services for domestic business systems through a unified virtual device interface. The application solves the adaptation problem of undocumented private protocols, realizes plug-and-play of Wintel peripherals for non-x86 architecture domestic terminals, significantly improves protocol compatibility coverage, reduces CPU occupancy, and meets the stringent requirements of millisecond-level response in the power and other specific industries.

This invention belongs to the field of electronic digital data processing technology, specifically relating to a low-altitude communication data anomaly detection system and method based on edge intelligence. The system parses protocol fields from the raw bitstream of the low-altitude communication link layer, extracts type identifiers and payload lengths to construct a protocol state machine transition matrix, and utilizes a Long Short-Term Memory (LSTM) network to extract state transition probability sequence features. Geographically adjacent edge nodes are set as micro-federated learning groups. Each node, after training using local features, only uploads network gating weight parameters to its neighboring nodes for weighted aggregation to update its local model. An alarm is triggered when the real-time state transition probability sequence deviates from the normal transition matrix and exceeds a preset topology threshold. This invention can identify protocol state machine logic errors and transition anomalies, reducing the amount of communication data required for collaborative model updates between edge nodes.

A method for enhanced broadcasting in an ATSC 3.0 system includes: selectively choosing among various input sources available to components within the system, including STLTP (Studio to Transmitter Link Transport Protocol), ALPTP (ATSC Link-layer Protocol Transport Protocol), DS (Data Source), and RF (off-air signals); inserting local content into a broadcast stream by at least one component within the system; and regenerating standard-compliant signaling information to ensure compatibility with ATSC 3.0 standards.

The invention discloses a self-adaptive network topology detection method based on an AI computing power data center, and the method comprises the steps: S1, the starting of data center physical equipment and the communication preparation of a cable, and guaranteeing the connection of an equipment physical link of an AI computing power data center network; step S2, deploying an agent program of an LTDP (Link Topology Discovery Protocol) protocol, which supports protocol extension based on an LLDP (Link Layer Discovery Protocol), for switch equipment of the computing power network data center, and deploying an agent program of an LTDP (Link Topology Discovery Protocol) protocol, which supports protocol extension based on the LLDP (Link Layer Discovery Protocol); s3, starting an agent program on the switch equipment to start to collect local LTDP information, wherein the content comprises LLDP information and computing power network characteristic information related to interfaces, flow control and equipment; and S4, deploying the adaptive network topology detection device at a universal server node of a computing power network data center, and starting the adaptive network topology detection device. And after receiving the TDP response message, the topology detection device continues to construct the TDP of the far-end equipment, so that intelligent detection and information collection of network equipment topology in the computing power center are realized.