115 results about "Data link layer" patented technology

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention provides an optimized kernel network and an implementation method thereof, and relates to the technical field of kernel networks, the kernel network comprises a fast data channel component XDP arranged on a data link layer; when the network card equipment receives a message data packet, the XDP analyzes and filters the received data packet, or encapsulates or de-encapsulates the received data packet, and modifies a field to forward the data packet; and the XDP matches and filters the received data packet with the rules in the BPF Maps, and discards the data packet when the data packet is illegal. The method comprises the steps that hardware initialization comprises the step of adding a zero copy processing flow when an NAPI polling point processing function is added; the application program configures an XDP socket; the xsk unit executes a BPF instruction, calls a network card driving unit to configure an XSK cache pool, and establishes a DMA mapping relationship between the device and the UMEM shared cache; and the network card drives zero-copy receiving and receiving of the data packet. According to the invention, the kernel network communication efficiency is improved.

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

A method for transmitting secured Ethernet frames on a communication line, the method including the following in a transmitter module: receiving an Ethernet frame comprising payload data from a network layer; retrieving a secure policy, defining the type of security to be applied to the Ethernet frame; producing an initialization vector based on an encryption counter and a physical address of the transmitter module; creating an authentication tag by applying an authentication algorithm on the secure policy, the initialization vector and the payload data using a shared key and the initialization vector; adding the secure policy, the initialization vector and the authentication tag to the payload data to create a secured Ethernet frame; and sending the secured Ethernet frame to a data link layer for transmission on the communication line.

The invention belongs to the field of computer system compatibility and peripheral interfaces, and relates to a domestic desktop terminal peripheral compatibility method and system based on protocol reverse mapping and a computer readable storage medium. According to the method, after peripheral access, three-layer analysis of physical layer signal reversal, data link layer structure reversal and application layer semantic reversal is carried out in sequence, and an equipment interface type, a frame structure and instruction semantics are dynamically identified. And based on the reverse result, dividing the equipment into a standard protocol or a private protocol through a protocol type decision, respectively routing the protocol to a drive straight-through module or an instruction translation executor for processing, and finally providing compatible services for a domestic service system through a unified virtual equipment interface. According to the method, the adaptation problem of a document-free private protocol is solved, plug and play of a Wintel peripheral by a non-x86 architecture domestic terminal is achieved, the protocol compatibility coverage rate is remarkably increased, meanwhile, the CPU occupancy rate is reduced, and the harsh requirement for millisecond response of specific industries such as electric power is met.

The application belongs to the field of computer system compatibility and peripheral interface, and relates to a domestic desktop terminal peripheral compatibility method and system based on protocol reverse mapping and a computer readable storage medium. After the peripheral is accessed, the method sequentially performs three-layer analysis of physical layer signal reverse, data link layer structure reverse and application layer semantic reverse, dynamically identifies device interface type, frame structure and instruction semantics. Based on the reverse result, the device is divided into standard protocol or private protocol through protocol type decision, and is routed to a drive pass-through module or an instruction translation executor for processing, respectively, to finally provide compatibility services for domestic business systems through a unified virtual device interface. The application solves the adaptation problem of undocumented private protocols, realizes plug-and-play of Wintel peripherals for non-x86 architecture domestic terminals, significantly improves protocol compatibility coverage, reduces CPU occupancy, and meets the stringent requirements of millisecond-level response in the power and other specific industries.

Systems, methods, and circuitry for adaptive playback of data link packets in a peripheral interface are described. A data link layer according to a peripheral interface protocol may include a replay buffer memory to simultaneously support sequential replay and selective replay in response to packet errors. In response to detecting an error packet, the receiver may determine an adaptive threshold for selecting a playback mode based on a set of link operating parameters, and then select between a selective playback mode and a sequential playback mode by comparing a fill level of a playback buffer to the adaptive threshold determined for the packet error.

The application provides an AI intelligent calculation platform reasoning resource scheduling method and system, relates to the technical field of computer resource management and task scheduling, and obtains task load information of a to-be-reasoned task, memory allocation records of an AI intelligent calculation platform in a preset time window, and a retransmission event timing sequence of a bus data link layer; obtains the discrete entropy of each computing node through a Shannon entropy formula according to the memory allocation records; counts the retransmission times of the retransmission event timing sequence in a sliding time window to generate a communication congestion index of each computing node; determines a weight coefficient according to the task load information, constructs a weighted bipartite graph, and determines a matching edge set that satisfies the most matching edges and the smallest sum of edge weights in the weighted bipartite graph by using a Hungarian algorithm, so as to be used for resource scheduling of the to-be-reasoned task. The problem of throughput decline caused by serious memory fragmentation and communication interference in the large model concurrent reasoning scene is solved.

The present disclosure provides a data transmission method, a chip and an electronic device. The method is applied to a first chip, the first chip comprises a first data link layer and a first physical layer, and the method comprises: generating, by the first data link layer, a first target protection code word according to a first target data of a current clock cycle and a first protection code word of the current clock cycle in the current clock cycle, the first target protection code word being used as a first protection code word of a next clock cycle; and in response to the first target data being data of a last clock cycle in first to-be-sent data, sending, by the first physical layer, the first target data to a second chip. The present disclosure is applied to the technical field of chips, can reduce the chip cross-chip transmission delay, reduce the calculation amount of the protection code word, and improve the clock frequency.

Systems, methods, and circuits for adaptive replay of data link packets in a peripheral interface are described. The data link layer according to a peripheral interface protocol may include a replay buffer memory to support both sequential and selective replay in response to packet errors. Responsive to detecting a packet in error, the receiver may determine an adaptive threshold for selecting a replay mode based on a set of link operating parameters and then select between selective and sequential replay modes by comparing the fill level of the replay buffer to the adaptive threshold determined for that packet error.

The invention relates to an ad hoc network MAC layer scheduling method, belongs to the technical field of ad hoc networks, and solves the problem of low transmission efficiency of routing information exchange when the node scale is relatively large in the prior art. S1, a data packet sent by a user generates an original Ethernet frame, and the original Ethernet frame enters a data link layer; s2, packaging the original Ethernet frame into a data frame including a destination node address at a time; s3, searching an optimal next-hop wireless node from the current node to the destination node, and judging whether link switching is needed or not according to the routing information of the current wireless node to obtain an actual next-hop wireless node address; s4, performing secondary packaging on the actual next-hop wireless node address and the primary packaging data frame, and sending to the actual next-hop wireless node; and S5, analyzing the destination node address and the original Ethernet frame by the actual next-hop wireless node, taking the destination node address and the original Ethernet frame as the current node, and repeating the steps S2 to S5 until the data frame is sent to the destination node. The efficient ad hoc network MAC layer scheduling method is realized.

This application provides a smart park hyperconverged integrated machine system based on edge computing. This integrated machine integrates a multi-mode heterogeneous communication interface unit, a protocol adaptive conversion module, an edge computing unit, and an instruction control unit. The protocol adaptive conversion module uses an FPGA and a protocol feature library to identify data frames of different communication protocols in real time at the data link layer, convert them into a unified data format, and then deliver them to shared memory via DMA zero-copy. The edge computing unit adopts a heterogeneous architecture of ARM and NPU, performing spatiotemporal alignment and multi-source data fusion analysis based on graph neural networks on the unified data, outputting a state vector. The instruction control unit is independent of the edge computing unit, generating control instructions based on the state vector and independently generating key control instructions in response to hard-wired signals from the IO input interface. This invention eliminates the problems of distributed device deployment and protocol incompatibility, reduces bandwidth consumption and construction costs, and improves system response speed and reliability.

The invention relates to the technical field of communication, and discloses a chip testing method, device, system and equipment, a storage medium and a program product. The method is applied to a data link layer, test data corresponding to a plurality of ports of a to-be-tested target are generated firstly, the test data are generated by first data frame generators corresponding to the ports according to protocol types and data generation parameters, and the test data are obtained by adjusting the protocol types and the data generation parameters. And various test data can be generated to comprehensively test the chip. According to the corresponding protocol types, the return data of the multiple ports are distributed to the multiple verification modules, reference data corresponding to the distributed return data are generated through second data frame generators of the verification modules, and the protocol types and data generation parameters of the reference data are the same as those of the corresponding return data; therefore, the integrity and correctness of the corresponding return data are verified through the reference data. According to the scheme, the chip testing efficiency is high, and the accuracy and the real-time performance are good.

The invention provides a multi-protocol data unified packaging method based on data link layer frame structure static feature matching, which comprises the following steps of: (1) extracting static feature parameters of each protocol based on frame structure specifications of common data link layer protocols, and constructing an extensible feature library; (2) carrying out frame-by-frame analysis on the mixed data stream to be processed, and extracting static features of candidate frames; (3) based on the extracted static characteristics of the candidate frames, determining a protocol type by adopting a multi-stage matching strategy; and (4) according to a protocol type matching result, converting the multi-protocol frame into packaging data in a unified format. According to the method, automatic identification and unified packaging of multi-protocol data in a hybrid network environment are realized through static feature library construction and a multi-stage matching strategy, the data packaged in a unified format can be directly input into an upper-layer system, independent analysis modules do not need to be developed for different protocols, and the cost is reduced. And the processing efficiency and the system compatibility of the multi-protocol data are remarkably improved.

The invention relates to a reliable data link transmission method, and belongs to the technical field of data transmission. According to the method, a handshake mechanism based on data packet response is introduced into an RGMII interface data link layer communicating with the processor, so that the problem of packet loss caused by rear-end Stream data flow blockage is fundamentally solved, and reliable transmission of each data packet between the FPGA and the processor is realized.

The application belongs to the field of chip interconnection communication, and particularly discloses a chip interconnection communication method and system based on Manchester coding, which comprises the following steps: a master control device generates and sends a communication frame, the physical layer of which adopts Manchester coding, logic 1 is high-to-low transition, and logic 0 is low-to-high transition, and the frame start / end is defined by a specific high-low level sequence; the data link layer of the communication frame comprises a synchronization code, an address field, a control field, a data field and an end code, the control field comprises pin intervals and quantity identification, and a clock is sent simultaneously to synchronize the slave device; the slave device decodes the received signal, determines the target pin range according to the identification when the address is matched, and sets the pin level according to the data field. The application improves the communication rate and efficiency, simplifies the wiring, and adapts to the chip interconnection requirements in multiple scenes.

This application relates to the field of integrated circuit technology and provides a physical IP verification device, verification method, computer equipment, and medium. The physical IP verification device includes: a first reusable multi-mode test sequence generator, a verification component physical interface, a second reusable multi-mode test sequence generator, and a verification component serial interface. This allows for the consideration of different simulation needs and scenarios, such as accelerating simulation efficiency and integrating verification. It supports protocol consistency verification, physical layer subsystem-level functional verification completeness, and standardized protocol verification. It provides a rich set of test vectors to meet the interfacing test scenarios and completeness verification needs of different layers, including the transaction layer, data link layer, and physical layer. It supports richly layered debugging interfaces and debugging methods, different physical interface versions and interface data bus widths, and also supports hierarchical and fine-grained low-power management.

The application relates to a DHCP server offloading method and device based on FPGA, which comprises the following steps: screening a UDP message from an original Ethernet message, screening a DHCP request message from the UDP message; performing protocol processing on the DHCP request message according to a state machine corresponding to a DHCP protocol to obtain a message processing result; generating a corresponding DHCP response message and encapsulating the DHCP response message into an application layer message according to the message processing result; adding a transport layer UDP header, a network layer IP header and a data link layer Ethernet header on the application layer message layer by layer to form a complete Ethernet response message and send the Ethernet response message externally.

The invention relates to a low-delay low-power-consumption protocol stack oriented to a wireless body area network, a message transmission method and a message transmission system. The protocol stack comprises a physical layer, a data link layer and a network layer which are arranged in sequence, wherein the data link layer defines transmitted maximum effective data and corresponding effective data area address allocation, and the network layer constructs tree structures through data channels and conditions of adjacent tree structures are associated. The transmission layer and the application layer are used for constructing an associated node communication mode, a non-associated node communication mode and a fast channel communication mode to realize information transmission; judging a message transmission method based on the data volume of the to-be-transmitted message; according to the system, monitoring equipment is used for obtaining monitoring information, the monitoring equipment serves as a child node of a network layer, the personal transceiver corresponding to the monitoring equipment is used for obtaining the monitoring information, the center transceiver obtains the monitoring information of the personal transceiver and summarizes the monitoring information to the monitoring center, and information transmission is achieved based on a protocol stack. According to the invention, the system power consumption of the wireless body area network is reduced, the real-time performance of the wireless body area network is improved, and the expandability and maintainability of the system are greatly enhanced.

The invention discloses an Ethernet data link layer unvarnished transmission method and device based on a secure digital input / output interface, and a medium. The method comprises the following steps: establishing communication connection between the master control micro-control unit and the Ethernet module through the secure digital input / output interface; the master control micro-control unit generates an Ethernet frame conforming to an Ethernet data link layer protocol specification, and sends the Ethernet frame to the Ethernet module through the secure digital input / output interface; the Ethernet module receives an external Ethernet frame through a physical layer chip, and transmits the Ethernet frame to the master control micro-control unit through the secure digital input / output interface; and interaction of the Ethernet data link layer frame is directly carried out between the master control micro-control unit and the Ethernet module. Through transparent transmission of the data link layer, the embedded device can be directly connected with other devices in the local area network, and the requirements of production testing and local area network debugging are met.

The application relates to the technical field of communication, and provides a communication method, device and protocol stack based on an SPI bus. The communication method based on the SPI bus receives a command message sent by a function application in an application layer, calculates a corresponding command length according to the command message, calls a first sending interface of a transmission layer, carries out frame processing on the command message according to the command length through the first sending interface, obtains at least one frame data, adds a first frame start symbol and a first check code to the at least one frame data through a second sending interface of a data link layer, obtains first communication data, and sends the first communication data to a peer end through a driving layer and a physical layer. The application can provide more reliable connection management.

The application relates to a data transmission method and device based on a PCIe speed reduction bridge, equipment and a storage medium, which are applied to the PCIe circuit verification field and include the following steps: initializing a speed reduction bridge module, so that a first PCIe link and a second PCIe link enter a normal operation state and an activated state; a control verification platform end generates to-be-transmitted data, and the to-be-transmitted data is transmitted to a simulation terminal module; the simulation terminal module analyzes the to-be-transmitted data, generates a data link layer package and a transaction layer data package, and performs data checking on the data link layer package and the transaction layer data package respectively; valid data passing the checking is stored in a preset data storage module; the valid data stored in the data storage module is transmitted to a full-speed terminal module and then to an upper computer end. The application has the technical effects that the PCIe link two-end speed mismatch data transmission problem is solved, and the cost of board verification is reduced.

Provided in the present application are a flow control initialization method and apparatus. The method is applied to the Flit-Mode of a PCIE data link local end, and comprises: in response to entering an initialization stage of a data link layer, switching to a negotiation state; in the negotiation state, acquiring a reserved size corresponding to each header field of a TLP data packet; on the basis of the reserved size corresponding to each header field, generating a first negotiation data packet; and sending the first negotiation data packet to a PCIE data link peer end, so that the PCIE data link peer end determines the initial credit count of the PCIE data link peer end on the basis of the reserved size of each header field carried in the first negotiation data packet.

A periodic control window is embedded in a data link layer data stream transmitted over a serial data link. This control window is configured to provide data link layer information, including details for initiating state transitions on the data link. The data link layer data can be sent during a link transmission state, and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data, indicating an attempt to change the number of active traces on the link.

The application discloses a kind of simulation flight data determinacy communication demonstration system based on time sensitive network, including by end system and switch form airborne network, demonstration manager and network tester.Demonstration manager is used to set the simulation parameter of end system and switch.Simulation end system has flight simulation application module, interface service module and network driver module;It is the interaction of simulating the flight data stream of real end system in time sensitive network;Through simulating periodic flight data, the flight state synchronization interaction of application layer is simulated, the data frame of data link layer is configured and encapsulated guarantee, and the communication function of simulation end system is simulated.Simulation switch has switching module and TSN protocol configuration module;It is according to scheduling or forwarding logic processing data frame.

The invention discloses an MQTT protocol deterministic communication method and system based on an AUTBUS bus, and relates to the technical field of bus networks, and the method comprises the following steps: collecting a service quality level field in an MQTT control message, and mapping the service quality level field of an MQTT protocol into a real-time priority parameter of an AUTBUS application layer data entity; obtaining service channel resources based on the real-time priority parameters in combination with a resource configuration table in an AUTBUS data link layer management entity; according to the invention, the service quality level of the MQTT protocol is mapped into the real-time priority parameter of the AUTBUS, and the fixed time slot resource allocated by the fixed bandwidth data service is utilized to provide strict time window guarantee for the high-priority MQTT message, so that the problem that the traditional MQTT cannot guarantee the transmission delay in the TCP and IP networks is solved, and the transmission delay of the MQTT is ensured. And the end-to-end time deterministic communication is realized.

Disclosed are systems, apparatuses, methods, and computer-readable media for extending and standardizing heterogeneous network devices using instrumentation. A method includes: receiving, by a client device using a first network interface, instrumentation bytecode to supplement with a data link layer from a management device, wherein a verifier of the client device verifies that the instructions of the bytecode are constrained for security based on a plurality of rules; in response to detecting a trigger at the client device, executing the instrumentation bytecode at the client device to perform at least one function associated with the trigger; and sending a response from the client device based on an execution result of the instrumentation bytecode.

A cloud server obtains a defined signature from a first communication device, where the defined signature is associated with a digital asset at the first communication device. The cloud server validates the defined signature based on a search of the defined signature in a main action database in the cloud server. The cloud server determines that a copyright check is required for the digital asset associated with the defined signature. The cloud server determines an occurrence of copyright violation for digital asset based on resemblance search of the digital asset in copyright database. The cloud server interrupts, based on the validation of the defined signature and the occurrence of the copyright violation, consumption of one or more data packets of the digital asset from being consumed at a datalink layer and a wire speed, prior to exposure of the one or more data packets to an application layer of the first communication device.