202 results about "Data link layer" patented technology

The invention discloses a power line carrier communication protocol data link layer simulation method, which comprises the following steps of: constructing a physical layer interface simulation module, simulating power line carrier or wireless air interface transmission through TCP socket communication, and creating a high-priority task process to process time slot-level time sequence synchronization for triggering a physical layer transceiving action at a specified time slot; configuring a time sequence synchronization control mechanism, obtaining a timestamp carried by a beacon frame sent by a concentrator, calling a clock synchronization function to align a site local clock with the timestamp when receiving the head of the beacon frame, adding delay compensation before sending data, and delaying and starting a physical layer receiving action to offset IP network transmission delay when receiving the data; a data frame processing flow is realized, a header callback function is controlled through a registration frame to respond to a physical layer state change, TCP message data is cached by using an annular queue, and a physical layer interface simulation module analyzes a message, distributes a memory and processes a load at a specified time slot after time sequence synchronization.

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The invention discloses a PCIe (Peripheral Component Interconnect Express) switching chip for realizing calculation in transmission, a switch with the PCIe switching chip and a communication system with the PCIe switching chip, the switching chip comprises a physical layer, a data link layer, a transaction layer and a calculation module, and is used for responding to the condition that a specific prefix of a transaction layer data packet is analyzed by the transaction layer and carries a preset calculation instruction; if yes, the calculation module analyzes the calculation instruction analyzed by the transaction layer so as to extract a calculation parameter field in the calculation instruction; the calculation module generates and executes a task of calculating the data in transmission according to the calculation parameter field, and calculation does not need to be started after all the data to be calculated are in place; firstly, part of the currently received data to be calculated is calculated to obtain an intermediate calculation result; and aggregating the subsequent newly received data to be operated and the intermediate operation result. According to the invention, by inserting the programmable calculation path into the PCIe switch, an innovative mechanism of'transmission while calculation 'is realized, the system delay is reduced, and the bandwidth occupation is reduced.

The invention provides an EtherCAT slave station port identification and topology diagnosis system and method. Comprising a master station access interface module which is used for being in butt joint with an EtherCAT master station protocol stack and establishing a read-write channel for a data link layer register of a slave station controller; the port state acquisition module is used for analyzing to obtain a physical connection indication, a loop opening and closing state and a communication state of each port, and generating a port state record; the state analysis and control module is used for writing a port opening instruction into a data link layer control register when physical connection exists and a loop is closed, and selecting a preset recovery port of the system to execute register writing when all ports of the target slave station are detected to be in a closed state, so as to obtain a port judgment result; and the topology and diagnosis output module is used for establishing a connection relationship between slave stations based on the port judgment result to generate network topology data. According to the application, unified collection and analysis of registers, automatic judgment and recovery of ports, topology reconstruction and standardized diagnosis output can be realized.

The invention provides an optimized kernel network and an implementation method thereof, and relates to the technical field of kernel networks, the kernel network comprises a fast data channel component XDP arranged on a data link layer; when the network card equipment receives a message data packet, the XDP analyzes and filters the received data packet, or encapsulates or de-encapsulates the received data packet, and modifies a field to forward the data packet; and the XDP matches and filters the received data packet with the rules in the BPF Maps, and discards the data packet when the data packet is illegal. The method comprises the steps that hardware initialization comprises the step of adding a zero copy processing flow when an NAPI polling point processing function is added; the application program configures an XDP socket; the xsk unit executes a BPF instruction, calls a network card driving unit to configure an XSK cache pool, and establishes a DMA mapping relationship between the device and the UMEM shared cache; and the network card drives zero-copy receiving and receiving of the data packet. According to the invention, the kernel network communication efficiency is improved.

The invention belongs to the field of computer networks, data compression and mobile internet and wireless communication, and discloses a TCP (Transmission Control Protocol) data packet compression and aggregation self-adaption method, which comprises the following steps of: 1, receiving a TCP data packet and separating a header from a payload; step 2, storing the effective load part; step 3, compressing the head and updating context data according to the serial number, the confirmation number, the mark and the window size field of the head; step 4, combining the compressed header with the effective load to obtain a compressed message; 5, extracting the compressed messages according to a set aggregation threshold value, aggregating the compressed messages, and sending the aggregated compressed messages to a data link layer; and step 6, storing the operation records, comparing the operation records with the previous N operation records, and changing a set aggregation threshold according to a comparison result. According to the invention, the message can be efficiently processed under the condition of a complex network, so that the overall network throughput and the message processing efficiency are improved.

To provide an information processing system, an information processing apparatus, and an information processing method for appropriately supporting a caregiver's assistance for a person to be cared.SOLUTION: An information processing system includes: a device including an application that executes processing corresponding to tacit knowledge of a skilled person; and a server system that transmits a data frame including a media access control (MAC) header, a frame body, and a trailer in a data link layer of communication with the device. The server system transmits the data frame in which an area with a fixed length including a first area storing ability information, a second area storing scene information, and a third area storing device type information, is included in the frame body. The device determines active or non-active of the application based on at least one of the ability information, scene information, and device type information.SELECTED DRAWING: Figure 1

The invention provides a wind turbine generator master control system software and hardware security and credibility mutual recognition measurement mechanism and method, and relates to the field of wind turbine generator control, and the method comprises the following steps: carrying out the hierarchical division of a wind turbine generator master control system, and carrying out the behavior measurement of all hierarchies according to the division result; the method comprises the following steps of: performing hierarchical bidirectional authentication on each hierarchy of a main control system of a wind turbine generator by combining a data link layer encryption technology on the basis of a cross-hierarchy credible mutual recognition mechanism; based on a cross-equipment-level credible mutual recognition mechanism, carrying out equipment-level identity bidirectional authentication between a main control system and a peripheral system of the wind turbine generator; and the change conditions of the behavior measurement result, the hierarchical authentication result and the equipment-level authentication result are tracked in real time, the credible state of the main control system of the wind turbine generator is evaluated, and a response strategy is dynamically executed according to the evaluation result. According to the method, the security problems of hardware tampering, software malicious injection, cross-device communication hijacking and the like can be solved, and meanwhile, the industrial control requirements of real-time performance and low resource occupation are met.

The invention discloses a satellite network encrypted traffic preprocessing method and system under multi-feature fusion, and the method comprises the steps: cooperatively processing original traffic data from two dimensions of a data packet level and a session level: at the data packet level, deleting an invalid TCP control segment and a TLS / DNS key exchange segment to eliminate redundancy, and removing a data link layer header to reduce interference; anonymization mask processing is carried out on an IP header to prevent overfitting, data normalization and standardization operations are executed to balance the feature scale, and meanwhile the data length is unified through truncation and zero filling strategies; in a session level, session splitting is carried out based on a quintuple sharing a source IP, a target IP, a port number and a protocol, statistical features such as the total number of data packets and session duration are extracted to capture time sequence association, and feature vectorization is realized by adopting Min-Max normalization. The double-layer fusion mechanism effectively combines data packet level microscopic fine-grained features with session level macroscopic context information to jointly improve the accuracy of encrypted traffic classification and the model generalization ability.

The invention relates to the technical field of city management, in particular to a multi-global intelligent connection platform comprehensive sensing system and method. Comprising a high-low altitude linkage sensing layer, a data link layer, an AI scheduling layer, an application layer and a closed-loop management module. The high-low altitude linkage sensing layer comprises a high-position video monitoring device deployed in an iron tower base station, a multi-rotor unmanned aerial vehicle in an unmanned aerial vehicle hangar, and an Internet of Things sensor array arranged on the ground, the high-position video monitoring device is coupled with a multispectral camera through a cradle head with an adjustable pitch angle, and covers a monitoring area with a radius not less than 500 meters; the unmanned aerial vehicle hangar is internally provided with a charging pile and a meteorological monitoring unit, the unmanned aerial vehicle carries an edge calculation module and a dual-light camera, and the Internet of Things sensor array comprises a voiceprint sensor, an air quality sensor and a vibration sensor; according to the design, geographical limitation can be broken through, and global seamless monitoring is realized, so that the timely discovery rate of events in a hidden area and the cross-department co-processing efficiency are improved.

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

A method for transmitting secured Ethernet frames on a communication line, the method including the following in a transmitter module: receiving an Ethernet frame comprising payload data from a network layer; retrieving a secure policy, defining the type of security to be applied to the Ethernet frame; producing an initialization vector based on an encryption counter and a physical address of the transmitter module; creating an authentication tag by applying an authentication algorithm on the secure policy, the initialization vector and the payload data using a shared key and the initialization vector; adding the secure policy, the initialization vector and the authentication tag to the payload data to create a secured Ethernet frame; and sending the secured Ethernet frame to a data link layer for transmission on the communication line.

The invention discloses an automatic testing device and method for a self-defined bus of a DCS, and belongs to the technical field of testing of industrial control systems.The device comprises a controller, an FPGA module, an adapter module, a main control case and a bus adapter card, the FPGA module serves as a lower computer to execute physical layer and data link layer processing of a communication protocol, and achieves electrical matching with a DCS custom bus through an adapter. A customized backboard and a bus adapter card are arranged in the main control case and are used for connecting a to-be-tested main control card, an I / O card and a communication card; the method is based on a layered protocol architecture, LVDS signal transmission and 4B / 5B coding are adopted in a physical layer, CRC32 verification and frame packaging are carried out in a data link layer, and node simulation, message framing, fault insertion and state monitoring are completed in an application layer. The method can effectively solve the problem that the private protocol bus lacks general testing means, and has high expandability and deep testing capability.

The invention provides a 10-gigabit Ethernet giant frame unpacking and packing device based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of network data packet processing. By arranging the standard frame combination unit, the giant frame splitting unit, the parameter configuration module and the clock module, the device can realize the functions of splitting giant frames to form standard frames, combining the standard frames to form the giant frames, dynamically configuring the MTU, monitoring the transmission quality of a data link in real time and the like. According to the invention, the data frames can be processed at the data link layer, the influence on the running speed of the 10 Gbps Ethernet is small, and the data frames can be quickly processed and forwarded. Meanwhile, flexibility is achieved, and parameters can be dynamically configured according to the specific operation environment so as to achieve the best operation state in the current environment.

The invention provides a low-delay real-time analysis architecture and analysis method of a PCIe protocol, belongs to the technical field of integrated circuit chip design, and aims at solving the problems that a traditional software analysis scheme is low in throughput and high in delay, and a special protocol analyzer is high in cost and poor in integration level. The analysis architecture comprises a data preprocessing module, a parallel 8b / 10b decoding module, a parallel descrambling module and an analysis state machine. The analysis method comprises the following steps: S1, data preprocessing; s2, decoding the data in parallel; s3, descrambling the data in parallel; s4, data clock synchronization; and S5, data analysis. According to the method, PCIe 2.0 full protocol stack analysis can be realized, real-time analysis of 5GT / s physical layer, data link layer and transaction layer data is supported, the end-to-end processing delay is only 70 ns, the low delay characteristic enables engineers to observe protocol behaviors in real time and locate data packet errors in time in the debugging process, and the debugging efficiency and accuracy are greatly improved.

The invention provides a data transmission method, a chip and electronic equipment, the method is applied to a first chip, the first chip comprises a first data link layer and a first physical layer, and the method comprises the following steps: the first data link layer is connected with the first physical layer in a current clock period; generating a first target protection code word according to the first target data of the current clock period and the first protection code word of the current clock period, wherein the first target protection code word is used as the first protection code word of the next clock period; in response to the fact that the first target data does not belong to the data of the last clock period in the first to-be-sent data, sending the first target data to the second chip through the first physical layer; the method and the device are applied to the technical field of chips, the cross-chip transmission delay of the chip can be reduced, the calculated amount of the protection code word is reduced, and the clock frequency is improved.

The invention belongs to the field of computer system compatibility and peripheral interfaces, and relates to a domestic desktop terminal peripheral compatibility method and system based on protocol reverse mapping and a computer readable storage medium. According to the method, after peripheral access, three-layer analysis of physical layer signal reversal, data link layer structure reversal and application layer semantic reversal is carried out in sequence, and an equipment interface type, a frame structure and instruction semantics are dynamically identified. And based on the reverse result, dividing the equipment into a standard protocol or a private protocol through a protocol type decision, respectively routing the protocol to a drive straight-through module or an instruction translation executor for processing, and finally providing compatible services for a domestic service system through a unified virtual equipment interface. According to the method, the adaptation problem of a document-free private protocol is solved, plug and play of a Wintel peripheral by a non-x86 architecture domestic terminal is achieved, the protocol compatibility coverage rate is remarkably increased, meanwhile, the CPU occupancy rate is reduced, and the harsh requirement for millisecond response of specific industries such as electric power is met.

The application belongs to the field of computer system compatibility and peripheral interface, and relates to a domestic desktop terminal peripheral compatibility method and system based on protocol reverse mapping and a computer readable storage medium. After the peripheral is accessed, the method sequentially performs three-layer analysis of physical layer signal reverse, data link layer structure reverse and application layer semantic reverse, dynamically identifies device interface type, frame structure and instruction semantics. Based on the reverse result, the device is divided into standard protocol or private protocol through protocol type decision, and is routed to a drive pass-through module or an instruction translation executor for processing, respectively, to finally provide compatibility services for domestic business systems through a unified virtual device interface. The application solves the adaptation problem of undocumented private protocols, realizes plug-and-play of Wintel peripherals for non-x86 architecture domestic terminals, significantly improves protocol compatibility coverage, reduces CPU occupancy, and meets the stringent requirements of millisecond-level response in the power and other specific industries.

The application discloses a PCIe device based on a Flit transmission mechanism, a communication system and a method, the device comprising a data link layer, a physical coding layer and a reconstruction module, the reconstruction module comprising a Flit packaging processing unit, a fault monitoring unit and a Fault Flit generating unit; the Flit packaging processing unit performs Flit packaging on data transmitted by the data link layer; the fault monitoring unit monitors a PCIe link transmitted by the physical coding layer to a remote device; in response to the fault monitoring unit monitoring that the PCIe link has a preset fault feature, the Fault Flit generating unit generates Fault Flit information reflecting a current fault type and transmits the Fault Flit information to the remote device; the remote device analyzes the Fault Flit information to determine a corresponding recovery strategy, and then the PCIe device and the remote device re-negotiate based on LTSSM state machines of respective physical coding layers to eliminate the fault.

The invention discloses PCIe equipment based on a Flit transmission mechanism and a communication system and method. The equipment comprises a data link layer, a physical coding layer and a reconstruction module, and the reconstruction module comprises a Flit packaging processing unit, a fault monitoring unit and a Fault Flit generation unit; the Flit packaging processing unit carries out Flit packaging on the data sent by the data link layer; the fault monitoring unit monitors a PCIe link transmitted from the physical coding layer to the remote equipment; in response to the fact that the fault monitoring unit monitors that the PCIe link has the preset fault feature, the Fault Flit generation unit generates Fault Flit information reflecting the current fault type and sends the Fault Flit information to the remote equipment; and waiting for the far-end device to analyze the Fault Flit information to determine a corresponding recovery strategy, and then re-negotiating the PCIe device and the far-end device based on the LTSSM state machines of the respective physical coding layers to eliminate the fault.

Systems, methods, and circuitry for adaptive playback of data link packets in a peripheral interface are described. A data link layer according to a peripheral interface protocol may include a replay buffer memory to simultaneously support sequential replay and selective replay in response to packet errors. In response to detecting an error packet, the receiver may determine an adaptive threshold for selecting a playback mode based on a set of link operating parameters, and then select between a selective playback mode and a sequential playback mode by comparing a fill level of a playback buffer to the adaptive threshold determined for the packet error.

The application provides an AI intelligent calculation platform reasoning resource scheduling method and system, relates to the technical field of computer resource management and task scheduling, and obtains task load information of a to-be-reasoned task, memory allocation records of an AI intelligent calculation platform in a preset time window, and a retransmission event timing sequence of a bus data link layer; obtains the discrete entropy of each computing node through a Shannon entropy formula according to the memory allocation records; counts the retransmission times of the retransmission event timing sequence in a sliding time window to generate a communication congestion index of each computing node; determines a weight coefficient according to the task load information, constructs a weighted bipartite graph, and determines a matching edge set that satisfies the most matching edges and the smallest sum of edge weights in the weighted bipartite graph by using a Hungarian algorithm, so as to be used for resource scheduling of the to-be-reasoned task. The problem of throughput decline caused by serious memory fragmentation and communication interference in the large model concurrent reasoning scene is solved.

A cell handover method and apparatus, and user equipment are provided. The method includes: when User Equipment (UE) camps on a first cell, obtaining first information, where the first information is used to indicate an abnormal situation when the UE uses a data network corresponding to the first cell; and when the first information meets a first preset condition, handing over from the first cell to a second cell, where the second cell is a cell whose signal quality parameter meets a second preset condition, or the second cell is a cell with the highest access priority; where the first information includes at least one of the following: information about a target data packet, network-related information corresponding to at least one application, a target uplink resource, a data accumulation amount at a data link layer, and a channel quality parameter of the first cell.

The present disclosure provides a data transmission method, a chip and an electronic device. The method is applied to a first chip, the first chip comprises a first data link layer and a first physical layer, and the method comprises: generating, by the first data link layer, a first target protection code word according to a first target data of a current clock cycle and a first protection code word of the current clock cycle in the current clock cycle, the first target protection code word being used as a first protection code word of a next clock cycle; and in response to the first target data being data of a last clock cycle in first to-be-sent data, sending, by the first physical layer, the first target data to a second chip. The present disclosure is applied to the technical field of chips, can reduce the chip cross-chip transmission delay, reduce the calculation amount of the protection code word, and improve the clock frequency.

Systems, methods, and circuits for adaptive replay of data link packets in a peripheral interface are described. The data link layer according to a peripheral interface protocol may include a replay buffer memory to support both sequential and selective replay in response to packet errors. Responsive to detecting a packet in error, the receiver may determine an adaptive threshold for selecting a replay mode based on a set of link operating parameters and then select between selective and sequential replay modes by comparing the fill level of the replay buffer to the adaptive threshold determined for that packet error.

The invention relates to an ad hoc network MAC layer scheduling method, belongs to the technical field of ad hoc networks, and solves the problem of low transmission efficiency of routing information exchange when the node scale is relatively large in the prior art. S1, a data packet sent by a user generates an original Ethernet frame, and the original Ethernet frame enters a data link layer; s2, packaging the original Ethernet frame into a data frame including a destination node address at a time; s3, searching an optimal next-hop wireless node from the current node to the destination node, and judging whether link switching is needed or not according to the routing information of the current wireless node to obtain an actual next-hop wireless node address; s4, performing secondary packaging on the actual next-hop wireless node address and the primary packaging data frame, and sending to the actual next-hop wireless node; and S5, analyzing the destination node address and the original Ethernet frame by the actual next-hop wireless node, taking the destination node address and the original Ethernet frame as the current node, and repeating the steps S2 to S5 until the data frame is sent to the destination node. The efficient ad hoc network MAC layer scheduling method is realized.

The invention provides a communication method, a communication device, a medium and a program product, which are applied to a satellite end or a relay station, and comprise the following steps: receiving a first signal based on a receiving antenna, processing the first signal, and demodulating the first signal into a digital signal; acquiring a data mapping cell; the data mapping cell at least comprises information used for representing a modulation coding mode and a corresponding transmitting channel; sending the digital signal to a corresponding transmitting channel based on the data mapping cell; and carrying out modulation processing on the digital signal based on the data mapping cell to form a second signal, and sending the second signal. According to the communication method and the communication device disclosed by the invention, the original complex signal processing flow in the wireless resource control layer and the data link layer is simplified into a data mapping process, so that the complexity of processing data on a satellite is greatly reduced, the communication efficiency is improved, and the cost and the power consumption of the satellite are also remarkably reduced.

In one aspect, a method for packet orchestration to provide data encryption at the internet protocol (IP) layer, includes the step of providing a quantum secure pre-shared key derivation scheme for a data link layer bulk encryption algorithm, meaning the ability to setup a separate communication channel, via the SSH protocol, and leverage ECDH over said channel to share pre-shared keys. The method includes the step of providing a set of software-based network bridges. The method includes the step of assigning a set of network ports to specific bridges, wherein the set of network ports implement segmentation and isolation based on an organizational policy.