1110 results about "Executable" patented technology

The invention discloses a prefetch instruction conversion optimization method based on memory access mode virtualization, which comprises the following steps of: when an executable file is executed in a dynamic instruction conversion mode, acquiring an address memory access mode of a prefetch instruction of x86 architecture, and analyzing an operand and an offset calculation mode of the prefetch instruction; according to an address memory access mode, an operand and an offset calculation mode, an instruction or an instruction sequence of an ARM architecture capable of completing memory address calculation and a prefetching function is constructed, a prefetching instruction of an x86 architecture is replaced with a corresponding ARM instruction or instruction sequence to complete instruction dynamic conversion, and conversion of the prefetching instruction of a complex address mode under the x86 architecture is achieved. And the execution reliability of the executable file in the dynamic instruction conversion mode is improved.

The invention discloses a data processing method and device, a storage medium and electronic equipment. The method comprises the following steps: when a target process needs to load a dynamic link library, determining a variable identifier corresponding to a target thread local storage variable needing to be accessed by a patch function and an initial position of an assembly code according to a code snippet associated with the patch function; according to the variable identifier, searching whether target relocation information with the variable identifier exists in the executable file, and if the target relocation information is not searched, modifying an assembly code corresponding to the local storage variable of the same-name thread according to the target offset to obtain a target assembly code; and replacing the initial assembly code with the target assembly code, modifying the relocation type of the local storage variable of the target thread to be relocation forbidding, and updating and loading the dynamic link library. According to the method and the device, the technical problem of patch function loading failure caused by different addressing modes of thread local storage variables in a conventional dynamic mode and a local executable mode is solved.

The invention discloses a memory access instruction reconstruction-based cross-memory page difference compatible operation method, which comprises the following steps of: modifying a dynamic instruction conversion engine (DIT) or a dynamic binary translation engine of a target system to execute an executable file compiled and generated by a source system for a memory access instruction which does not meet the size requirement of a memory page of the target system; in the conversion process, memory access instructions are reconstructed by modifying address offset parameters or adopting instruction combination replacement and the like, and compatible operation of the executable files in a system with memory page differences is achieved on the premise that source codes do not exist.

The invention discloses a memory partition-based dynamic instruction conversion memory access conflict optimization method, which comprises the following steps of: allocating memory sub-regions for each computing core according to a load condition in an ARM (Advanced RISC Machines) many-core system to establish a first mapping relation table; when the executable file is loaded and executed in a dynamic instruction conversion mode, obtaining a second mapping relation table between the thread and the calculation core, and obtaining a thread and a memory address corresponding to a to-be-converted instruction of a memory access instruction class, obtaining a converted first ARM virtual address and a related first address space according to the first mapping relation table and the second mapping relation table, and determining an adjustment mode of the converted instruction according to the relation between the first ARM virtual address and the first address space to complete instruction conversion. The memory access conflict in the dynamic conversion process from the x86 instruction to the ARM instruction on an ARM many-core system is effectively reduced, and the execution performance of a program after dynamic instruction conversion is improved.

The invention discloses a chip verification method and device, equipment, a storage medium and a program product. The method comprises the steps that a first executable file of a C model is obtained, the first executable file comprises an original code and a target code which are designed based on a verified function in a chip, and the verified function comprises a plurality of algorithm steps; running the first executable file based on the input signal to obtain running data of each algorithm step; extracting simulation data of each algorithm step from the simulation waveform file with the verified function; and respectively comparing the operation data and the simulation data of each algorithm step to determine an abnormal algorithm step in which the operation data and the simulation data are inconsistent. Therefore, by automatically comparing the operation data and the simulation data of each algorithm step, the abnormal algorithm step with the problem can be quickly determined, and the manual inspection and analysis time is shortened.

The invention discloses a multi-language dynamic switching system and method of embedded equipment, and relates to the technical field of human-machine interfaces and embedded systems.The method comprises the steps that source codes in an HMI program are traversed through a character extraction module to extract all character strings; eliminating repeated items, numbering the character strings, and outputting a database file and a replacement array; substituting the serial number into the source code file again by using the substitution array to replace the character string at the corresponding position; outputting the translated database file as a C language source code, compiling the C language source code into a dictionary generation module project, generating an executable file, and outputting the dictionary file to an HMI running directory after the device is started; after the HMI program is started, the dictionary is read into different dictionary arrays according to blocks, and character strings at corresponding positions in the dictionary arrays are extracted after a page sends a request. The method has the advantages of being lower in maintenance difficulty, more efficient in resource utilization, shorter in indexing time, better in system robustness and the like.

The invention provides a distributed compiling method and device, electronic equipment and a storage medium, and belongs to the technical field of data processing.The method comprises the steps that a source code file is sent to a server side to be compiled and assembled, a compiling result returned by the server side is obtained, and the compiling result comprises information of a compiled target file; based on the compiling result, a corresponding pseudo file is created, and the pseudo file comprises a rebuilding method of the compiling result file; after pseudo files corresponding to all the compiling results are obtained, a link command is sent to a server side, and the link command indicates the server side to conduct file link operation on all the target files; and receiving the executable file returned by the server. According to the method and the device, the intermediate file is prevented from being copied for multiple times between the client and the server, so that the network load required by file transmission is reduced, and the distributed compiling efficiency is improved.

The invention relates to the technical field of chips, in particular to a large-scale chip code coverage rate obtaining method, electronic equipment and a medium, and the method comprises the following steps: S1, constructing different test clusters; s2, setting verification configuration information, test parameters and a to-be-verified interface set for the Giq; s3, generating a corresponding file list based on each Aiq in parallel, and compiling to generate a corresponding executable file Fiq; s4, transmitting the Biq to a test case in the Giq in parallel, executing a corresponding verification operation based on the Fiq, and obtaining a set Eiq of the interfaces to be verified which are overturned by the Giq; s5, after the Gq is completely executed, obtaining a union set GEiq of all Eiq corresponding to the Gq; and S6, after all Gq are executed, obtaining a union set GE of all GEiq, and determining the code coverage rate of the large-scale chip based on GE and GD. According to the method, the large-scale chip code coverage rate can be accurately and quickly obtained.

The invention relates to a virtual machine management unloading method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps that a shared file directory is obtained, the shared file directory is mounted on a host when the host loads a drive of a data processing unit, and the host and the data processing unit share a file source through the shared file directory; storing an executable file of a command execution component server side in the host in the shared file directory, wherein the executable file of the command execution component server side is used for storage, starting and management of the command execution component server side; and the command execution component server side is communicated with the command execution component client side in the data processing unit through virtio-vsock. By adopting the method, the influence on the HOST performance can be avoided.

The invention discloses a Direct3D deep cutting behavior compatible method based on an atomization shader, which comprises the following steps: establishing a scene combination metadata table in a DXVK compiling stage, constructing a shader template library containing atomization components and variants, and generating an executable file of the DXVK; after the DXVK is started, deep processing API calling of the D3D application is intercepted, parameters are extracted to generate an atomization parameter set, and scene combination metadata are matched or newly added in a scene combination metadata table to obtain a recommendation strategy and shader component combination; a conversion mode is adaptively selected according to scene metadata to calculate a Vulkan depth value, and a depth comparison operation is adapted to generate a Vulkan depth conversion parameter; the DXVK maps the parameters into DRM depth control parameters irrelevant to hardware and transmits the DRM depth control parameters to a kernel, the DRM packages the DRM depth control parameters and converts the DRM depth control parameters into hardware instructions matched with the GPU, the DXVK loads a shader template and binds the parameters, original logic is spliced to generate a Vulkan shader module, a Vulkan command stream containing the hardware instructions is generated and submitted to the GPU after a pipeline is bound, and finally the GPU executes the Vulkan command stream to obtain a depth rendering result conforming to D3D native logic.

The invention provides a performance analysis method, electronic equipment, a storage medium and a program product. The method is applied to an agent side, a user mode program and a kernel mode program run in the agent side, and the method comprises the steps that the user mode program reads an executable file executed by the agent side in a user mode, and backtracking information used for backtracking a target service is extracted from the executable file; the user mode program generates a backtracking table based on the backtracking information, and transmits the backtracking table to a kernel mode where the kernel mode program is located; when a performance analysis event is triggered, the kernel mode program backtracks a function call process in a target service execution process according to backtracking information recorded in a backtracking table in a kernel mode to generate statistical data of a function call stack; and the user mode program obtains statistical data of the function call stack generated by the kernel mode program, and converts the statistical data of the function call stack into performance analysis data.

The invention provides a software integration method and a software management system of a power domain controller, and belongs to the field of automobiles, the method comprises the following steps: generating an ARXML file based on a variable data type and a system transfer function interface defined in a software architecture; based on the ARXML file, generating a code file of the basic software; based on the ARXML file, a code file of the application software is generated, and the code file of the application software is matched with the software interface described by the ARXML file; based on the ARXML file, a code file of a middle layer is generated, the middle layer is used for connecting the basic software and the application software, and the code file of the middle layer is matched with the software interface described by the ARXML file; and performing integrated compiling on the code file of the basic software, the code file of the middle layer and the code file of the application software to obtain an executable file. The software integration method and device can be compatible with various modes for software development, rapid integration of the software is facilitated, and the software integration efficiency is improved.

The embodiment of the invention provides a container creating method, device and system and a storage medium. In the embodiment of the invention, the snapshot of the container instance and the compiled driver of the parallel processing unit are cached in the cache pool of the storage cluster in advance, namely the executable file of the cache driver is cached. When the container is created, the container mirror image snapshot and the executable file of the driver of the parallel processing unit are read from the cache pool through the intranet, and the container mirror image and the driver do not need to be pulled from a mirror image warehouse through a public network, so that on one hand, downloading of a mirror image layer is reduced, and the container creation speed can be increased; on the other hand, the executable file of the driver is directly obtained, the driver does not need to be compiled and installed in the instance creating process, the compiling and installing time of the driver can be shortened, and the container creating speed is further increased. The increase of the container creation speed is beneficial to increase of the container starting speed.

A system and method for data compaction with adaptive codebook statistical estimates. Training data sets determine sourceblock frequencies while a dynamic mismatch probability system continuously refines estimates based on observed patterns. Context-aware handling selects appropriate secondary encoding methods for different data types (text, binary, image, executable). Machine learning models predict optimal mismatch probabilities from extracted features. Edge-optimized training enables codebook development on resource-constrained devices with intelligent resource management. Differential updates transmit only changes between codebook versions, minimizing bandwidth usage. Federated learning enables multiple devices to contribute to shared codebooks while maintaining data privacy. A secure synchronization protocol with authentication and verification ensures codebook consistency. The distributed maintenance method provides systematic validation, conflict resolution, and optimization across device networks, enabling efficient encoding across heterogeneous systems.

The invention relates to a debugging method and device of embedded equipment, an electronic device and a storage medium, and the debugging method of the embedded equipment comprises the steps: obtaining instruction set information of the embedded equipment through a UART (Universal Asynchronous Receiver / Transmitter) interface; configuring a corresponding cross compiling component based on the instruction set information; compiling a preset probe source code into an executable file by utilizing a cross compiling component; extracting a minimum code subset in the executable file, and determining a code probe according to the minimum code subset; and injecting the code probe into the free memory space on the embedded device through the UART interface, and debugging the embedded device. According to the method and the device, the problem of low debugging flexibility of the embedded equipment is solved.

The invention provides an I / O speed limiting method and device, electronic equipment, a storage medium and a program product, and belongs to the technical field of containers. According to the embodiment of the invention, a target virtual machine is constructed based on a target kernel; then deploying the target virtual machine to at least one target container of the container cluster, and constructing to obtain a target mirror image based on the target virtual machine and a preset executable file; and finally, running the target mirror image in the target container, so that the target virtual machine runs an I / O speed limiting daemon process corresponding to the executable file, and carrying out I / O speed limiting on the target container. According to the embodiment of the invention, the executable file used for carrying out I / O speed limiting on the container is deployed into the target mirror image, so that the target virtual machine can run the I / O speed limiting daemon process when the container is started, I / O speed limiting management on the target container is realized, and the running stability of a container cluster is effectively ensured.

Systems and methods for analyzing memory architectures and for mapping data structures in software programs to appropriate memory to take advantage of the different memory architectures. A computer architecture having a processor connected to one or more first memories and one or more second memories is defined, wherein the first memories and the second memories are characterized by different performance profiles. An executable of a software program is instrumented to capture, during runtime, patterns of access to selected data structures of the executable. Based on an analysis of the patterns of access, allocation of the selected data structures between the first and second memories is determined.

The invention discloses a lightweight cross-platform PLC (Programmable Logic Controller) multi-language code generation method, which relates to the field of industrial process control, and firstly provides a unified intermediate data model, and on the basis, a module for converting each PLC language into the unified intermediate data model is realized; on the basis of a standardized JSON data structure, a modularized unified intermediate language conversion chain is further supported, an analyzer and a generator communicate through a JSON interface, a cross-platform conversion path is supported, and unified intermediate language conversion from PLC to JSON to XML to ST to C is completed; the method comprises the following steps of: integrating an open source compiler and runtime, constructing an open and pluggable automatic execution framework, compiling a generated C code into a platform executable file by using an adaptive GCC tool chain aiming at different target platforms, and deploying a program generated by compiling to a soft PLC runtime system supporting multiple platforms. According to the method, a JSON intermediate data structure which is light in weight, unrelated to languages and uniform in structure and a matched conversion framework of the JSON intermediate data structure are constructed.

The invention discloses an AVX data vector segmentation optimization method based on data access semantic analysis, which comprises the following steps: in a dynamic instruction conversion process of an executable file, determining an instruction function and the precision and bit of a data vector according to semantic analysis on an AVX instruction, and dynamically determining a Neon instruction corresponding to a computational AVX instruction; according to semantic analysis of an AVX instruction and a related AVX instruction, an instruction function, precision and digit of a data vector and a data segmentation strategy are clarified, instruction-level data segmentation strategy optimization is realized, a Neon instruction corresponding to a data loading type AVX instruction and a mapping relation between AVX registers and Neon registers are dynamically determined, and the data loading type AVX instruction is optimized. On the basis, the Neon instruction simulates the execution of the AVX instruction, and the execution performance of the AVX instruction during simulation execution on an ARM platform is effectively improved.

Embodiments assess security vulnerability of an application. An embodiment identifies one or more executables associated with an application and identifies one or more libraries associated with the application. In turn, based on the identified one or more executables and identified one or more libraries, static vulnerability of the application and dynamic vulnerability of the application are determined. Then, an indication of security vulnerability of the application is generated based on the determined static vulnerability and the determined dynamic vulnerability.

The invention discloses a three-dimensional structure reasoning method, device and equipment of an amino acid sequence and a medium, relates to the technical field of deep learning, is applied to reasoning equipment, and comprises the following steps: splitting a reasoning model into a first sub-model and a second sub-model; performing operation on the to-be-reasoned amino acid sequence by using the first sub-model through the first processor; splitting the second sub-model, the weight data of the second sub-model and the operation result by using a splitting unit determined based on the dimension information through a second processor, compiling the split sub-model into an executable file, and performing operation on the split operation result by using the split weight data and the executable file to obtain a plurality of operation results; and splicing the plurality of operation results through a second processor, and determining a three-dimensional structure of the amino acid sequence to be reasoned by utilizing a splicing result. According to the method, the problems that the memory of a high-performance computing unit is limited and inference operation with relatively high dynamic performance cannot be well processed are solved.

The invention provides a method and a system for exporting Allegro file packages in batches based on Python. The method comprises the following steps: configuring an Allegro executable file path and a pre-recorded Skill script path; selecting a target export directory through a graphical interface, and updating export path parameters in the Skill script; selecting Allegro PCB files to be processed in batches through a graphical interface; verifying the file list and the export path, and starting batch processing after confirmation; traversing the file list, and executing the following steps on each Allegro PCB file to be processed: calling an Allegro command line tool, and opening the PCB file in a batch processing mode; automatically loading a pre-recorded Skill script to execute a packaging and exporting operation; and capturing and feeding back a command line execution state. The efficiency can be improved, multi-file batch automatic processing is supported, and manual operation is reduced; human errors are avoided through automatic path configuration and an exception capture mechanism; the interaction is friendly, and the operation threshold is reduced while the operation steps are simplified.

This invention discloses a full lifecycle management system and method for scientific computing programs. The system includes a build environment subsystem and a production environment subsystem. The former provides computer resources for the build process of the scientific computing program throughout its lifecycle, while the latter provides computer resources for the testing and deployment processes. This invention, through a full lifecycle management method for scientific computing programs, operates on corresponding computing resources, encompassing a series of steps including querying, triggering scheduling, build execution, result distribution, and test deployment. It automatically generates the executable file of the scientific computing program and configures its runtime dependencies. Simultaneously, it automatically generates a corresponding description file recording the entire lifecycle process. Furthermore, based on version management of these description files and their sets, it achieves full lifecycle traceability and cross-platform migration and deployment of scientific computing programs in a high-performance computing environment.

The invention discloses a confusion encryption protection method and device for an executable file. The method comprises the following steps: confusing an executable program file, carrying out self-defined key and algorithm encryption on the confused file, carrying out key verification and algorithm decryption on the confused and encrypted executable file, and de-confusing a decrypted result file. The device comprises a file selection module, an executable file confusion encryption module, an executable file decryption and de-confusion module, a user-defined key module, an execution module and a result file output module. Compared with the prior art, the compiled executable file is subjected to confusion encryption processing and de-confusion decryption processing, confusion and encryption double guarantees are provided for the executable file, and multiple safety guarantees of the executable file are achieved.

The invention relates to a method, a device and a system for locally deploying a cross-platform graph database program. The method mainly comprises the steps that a vcpkg package manager is deployed, and a vcpkg.json file is created under a directory where a program is located; creating CMakeLists.txt in a catalog where the program is located for defining how to construct the program and linking a third-party library installed through the vcpkg; an executable file of the database is generated by running the CMake command; recursively collecting all third-party libraries on which the program depends through an ldd command and an awk command, and copying all the third-party libraries on which the program depends and an ld interpreter of the program to a directory where the program is located; through the patchelf file, modifying an ld interpreter path of the program to be a relative path under a catalog where the program is located, and modifying a rpath of the program to be the relative path under the catalog where the program is located; and packaging and delivering the files in the catalog where the program is located to a user. According to the method, a developer can construct a database program deployed in a zero-dependence manner.

The invention discloses a reconfigurable AI chip-oriented neural network reasoning deployment method, which comprises the following steps of: exporting a trained model into an ONNX format by using an ONNX library corresponding to a deep learning framework, and analyzing the ONNX format model to obtain a network topology structure, operator information and general control information; dividing each operator according to the operator information to obtain a division result; assembling and splicing operator division results in combination with a network topology structure to obtain task information, and the like. Hardware resources of the reconfigurable AI chip are fully utilized. And finally, organizing general control information and task information of all operators into a final executable file, and efficiently completing reasoning deployment of the neural network model on the reconfigurable AI chip. According to the method and the device, the technical problems of high development threshold and low efficiency of the existing specific AI chip architecture compiler can be solved, and the technical problem that the existing automatic code generation method possibly cannot fully utilize the chip performance can be solved.

The embodiment of the invention relates to the technical field of MacOS injection, and discloses a static injection method and a storage medium. The method comprises the following steps: inserting a blank character in a loading command area of an executable file, and writing a first target loading command at the position of the blank character; a second target loading command in the loading command area is processed, so that a non-first loading command in the loading command area is shortened by a target length, position information, corresponding to the loading command, of the loading command area is adjusted according to processing of a second target recorded command, and the position information comprises the size of a virtual memory, the address of the virtual memory and a file deviation value; the executable file keeps normal operation after being processed by the second target loading command, and the target length is not smaller than the length of the blank character. The problem that the reserved space is not enough to insert the loading command of the injection library is solved, the static injection process can be simplified, the implementation difficulty of the static injection is reduced, and successful implementation of the static injection is guaranteed.

An automated system attempts to characterize code as safe or unsafe. For intermediate code samples not placed with sufficient confidence in either category, human-readable analysis is automatically generated to assist a human reviewer in reaching a final disposition. For example, a random forest over human-interpretable features may be created and used to identify suspicious features in a manner that is understandable to, and actionable by, a human reviewer. Similarly, a k-nearest neighbor algorithm may be used to identify similar samples of known safe and unsafe code based on a model for, e.g., a file path, a URL, an executable, and so forth. Similar code may then be displayed (with other information) to a user for evaluation in a user interface. This comparative information can improve the speed and accuracy of human interventions by providing richer context for human review of potential threats.

Systems and methods for decompiling binary code or executables are provided herein. In some embodiments, a method of training a machine learning algorithm for decompiling binary code into readable source code includes collecting a data set of source code and at least one element associated with the source code; providing binary code using the data set; training a model configured to decompile the binary code into source code using the data set by: decompiling the collected binary code into intermediate source code; comparing the source code in the data set with the intermediate source code; and updating the model and repeating the training if the source code in the data set differs from the intermediate source code by more than a threshold amount.

The invention provides a VTCU controller task allocation method and device based on AUTOSAR and electronic equipment, and the method comprises the steps: dividing an application layer into a plurality of software components according to the functional characteristics of the application layer, and generating an application layer code; importing the application layer code into a configuration tool of the runtime environment to configure related modules of the runtime environment, and generating a runtime environment code; according to the functional characteristics of the running entity of each software component, a periodic task and related modules of the periodic task are configured through a configuration tool of a real-time automobile operating system, and a real-time automobile operating system code is generated; integrating an application layer code, a runtime environment code and a real-time automobile operating system code into a Tasking project, and generating an executable file; and downloading the executable file into a whole vehicle and a gearbox controller through the UDE, and running the executable file. According to the scheme, the load rate of the CPU is effectively reduced, and the running efficiency of the VTCU controller software driving program is improved.