1017results about "Multiple digital computer combinations" patented technology

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

The invention discloses a GPU Box hardware decoupling system based on a Retimer card and a PCIe Switch chip, and belongs to the technical field of computer hardware architecture and high-speed interconnection. According to the system, a Retimer card and a PCIe Switch chip are integrated in an independent GPU Box, and a decoupling link of a CPU server and a GPU acceleration card is constructed; the Retimer card realizes 30-meter long-distance PCIe signal transmission and breaks through physical distance limitation; the PCIe Switch chip pools GPU resources through a dynamic routing and MRIOV technology, supports flexible allocation of computing power by multiple servers, and realizes Peer-to-Peer direct connection communication between GPUs. Aiming at a large model reasoning scene, the system optimizes KV cache bandwidth allocation and video memory and memory cooperative scheduling, so that the 100B parameter model reasoning throughput is greatly improved; and meanwhile, the usability of the system is greatly improved through fault isolation and hot plug design. According to the method, the problems of physical binding of the CPU and the GPU, limited transmission distance, rigid resource allocation and the like in a traditional architecture are solved, and the method is suitable for large-scale AI calculation and distributed GPU cluster deployment.

The invention belongs to the technical field of metal crack detection, and discloses a metal microcrack ultrasonic detection method, which comprises the following modules: an ultrahigh frequency composite array probe with a center frequency dynamic adjustable range of 5-50 MHz; the dual-mode excitation and receiving module is used for independently generating a pulse reflection mode excitation signal and a diffraction mode chirp frequency modulation signal; the phase-controlled synthetic aperture dynamic focusing module is used for realizing + / -60-degree deflection and sub-wavelength level focusing of acoustic beams; the nonlinear harmonic enhancement module is used for exciting a crack nonlinear effect by superposing 1-2MHz fundamental waves; and a time-space-frequency three-domain data fusion module. According to the method, signal-to-noise ratio collapse caused by the diffraction effect in a traditional method is overcome, more importantly, the system has low-frequency penetrability and high-frequency resolution at the same time due to 80%-120% of broadband coverage of chirp frequency modulation signals, the diffraction signal gain is increased by 20 dB or above, a near-surface blind area is compressed to be within 0.2 mm, and the system can be applied to the field of radar imaging. And the core pain point of missing detection of the near-surface microcracks of the thin-wall component is solved.

The invention relates to an activation value re-segmentation communication method for a heterogeneous AI acceleration chip server. The activation value re-segmentation communication method comprises the following steps: scanning through chips, network interface cards and PCIe levels in the AI acceleration chip server, extracting network topology information of the server, calculating delay and bandwidth from each chip to each network interface card, and generating an affinity matrix; based on the affinity matrix, each chip is bound to a network interface card in an exclusive or shared mode through maximum matching; based on the server network topology information, the chip-network interface card affinity and the network interface card and PCIe single line bandwidth, activation value communication mode matching is carried out, and communication modes comprise a transmitting / receiving mode, a transmitting / receiving + collecting mode and a transmitting / receiving + broadcasting mode; and double-level multi-channel communication between the chip and the network interface card is realized. The method has the advantages of remarkably improving the bandwidth utilization rate, being highly adaptive to topology difference, being high in heterogeneous compatibility and the like.

The disclosed computer-implemented method includes determining that incoming media item requests are to be skewed from a random distribution among server nodes, using a random distribution algorithm, to a directed distribution among the server nodes. The method then includes identifying, in a loading assignment, which media items are to be loaded onto specific server nodes to produce the directed distribution of media item requests. The method next includes preloading the identified media items onto the server nodes according to the loading assignment and receiving media item requests for the preloaded media items. The method then includes routing the received media item requests to the server nodes using the random distribution algorithm, where the random distribution algorithm is skewed to the directed distribution based on the preloading of the media items according to the identified loading assignment. Various other methods, systems, and computer-readable media are also disclosed.

This application describes systems and methods for facilitating memory access for graph neural network (GNN) processing. An example system includes a plurality of processing units, each configured to perform graph neural network (GNN) processing; and a plurality of memory extension cards, each configured to store graph data for the GNN processing, wherein: each of the plurality of processing units is communicatively coupled with three other processing units via one or more interconnects respectively; the plurality of processing units are communicatively coupled with the plurality of memory extension cards respectively; and each of the plurality of memory extension cards includes a graphic access engine circuitry configured to acceleratre GNN memory access.

The invention relates to the technical field of AI chips, in particular to a calculation method of an AI chip based on RISC-V CPU Core and the chip. The AI chip comprises a scheduling core and a plurality of computing cores based on an RISC-V instruction set architecture, and the method comprises the following steps: the scheduling core analyzes an AI task to determine one or more computing operation types required by the AI task, and selects one or more computing cores capable of executing the computing operation types from the plurality of computing cores according to the computing operation types; the scheduling core allocates the AI task to a calculation core corresponding to the calculation operation type, and activates the calculation core; and the calculation cores obtain respective kernel codes and required calculation data so as to execute respective calculation tasks. It can be understood that according to the technical scheme, the scheduling core and the computing core are both based on the RISC-V instruction set architecture, the ecological barrier problem is solved, flexible iteration of the architecture and optimal configuration of computing resources are achieved, and the method has the beneficial effects of ecological openness, high flexibility, remarkable cost effectiveness and the like.

A database system analyzes a query to determine the resources required to execute the query by identifying the department that issued the query (the “source department”) and identifying query-recited tables and determining the department by which each of the query-recited tables is controlled (the “accessed departments”). The database system determines that the resources required to execute the query are controlled by more than one department: the source department and one or more accessed departments. For each accessed department, a cost of a first strategy involving a SQL rewrite and a cost of a second strategy not involving a SQL rewrite are determined by preparing a query execution plan, determining the cost of the resources, and considering whether data controlled by the accessed department is not accessible except to the accessed department. The first strategy is chosen for at least one of the accessed departments because the first-strategy cost is lower.

The invention discloses an efficient data flow transceiving controller applicable to a multi-core storage and calculation system, which comprises two transmitting controllers and two receiving controllers, and the transmitting controllers and the receiving controllers are arranged on the peripheries of cores and are used for performing data packaging and transmitting and data flow judgment work; wherein the sending controller comprises a configurable asynchronous FIFO (First In First Out), a data packaging unit and an error correction code generating unit; the receiving controller comprises an error correction code decoding unit, a data packet unpacking unit and a microchip detection unit; the flit detection unit is used for detecting information in a head flit to judge whether data meet the calculation requirement of the current core particle or not, and if the data do not belong to the task range of the current core particle, the data are redirected to the sending controller through a bypass transmission mechanism. According to the application, the transmission speed of the data stream among different core particles is improved, and the data stream can be dynamically planned and transmitted according to the preset rule by constructing the efficient data transceiving controller.

Techniques for enhancing performance in Industrial Internet-of-Things (IIoT) scenarios, including techniques for time-sensitive networking (TSN) and 5G wireless network integration. An example method, performed by a wireless device, comprises receiving system information (SI) from a radio base station (RBS) of a radio access network (RAN), the SI being indicative of support for TSN through the RBS, and establishing at least one TSN stream with an external data network, through the RBS. The example method further includes receiving a first timing signal from the wireless communications network, via the RBS, receiving a second timing signal from the external TSN data network to which the wireless device is connected, comparing the first timing signal to the second timing signal to determine an offset, and transmitting the offset to the wireless communications network.

The invention discloses a server node shell and a server node with the server node shell, and relates to the technical field of servers. The wind scooper assembly comprises a first support, a second support, a wind scooper and a locking assembly, the first support and the second support are arranged on the wind scooper in a spaced mode, one of the first support and the second support is rotatably connected with the base, and the locking assembly is arranged on the other one of the first support and the second support; the locking assembly comprises a movably-arranged locking structure, and the locking assembly is provided with a locking position where the locking structure retracts to be matched with the base in a limiting mode and an unlocking position where the locking structure stretches out to be separated from the base. The problem that the disassembly and assembly efficiency of the computing node shell is low in the prior art is at least solved.

The invention provides a data processing method of an AXI bus and an AXI bus maintenance and measurement unit and system.The method comprises the steps that when it is monitored that a target signal interaction instruction sent by sender equipment to receiver equipment reaches the AXI bus, control information corresponding to the target signal interaction instruction is stored, and a target clock is started; monitoring each sub-operation indicated by the control information in real time, determining arrival information of a target sub-operation, and determining whether the AXI bus is abnormal or not according to the arrival information of the target clock and / or the target sub-operation; if yes, residual control information corresponding to the target signal interaction instruction is determined; and according to the residual control information, simulating the receiver equipment to send response information to the sender equipment, so that the sender equipment executes subsequent operation according to the response information. According to the method and the device, the AXI bus can be prevented from being hung, normal operation of the AXI bus is ensured, and the stability and the reliability of operation of a system where the receiver equipment and the sender equipment are located are improved.

The invention provides a storage and calculation integrated structure and a chip, and belongs to the technical field of integrated circuits, and the storage and calculation integrated structure comprises at least one near storage core grain which is used for providing large-capacity storage; the in-memory computing unit is used for providing computing processing, and the near-memory core grains provide cache space for data and / or instructions processed by the in-memory computing unit; the at least one logic processing core particle is used for loading the data and / or instructions stored in the near memory core particle into the in-memory computing unit, and updating and storing the data and / or instructions processed by the in-memory computing unit into the near memory core particle; and the logic processing core particle is integrated with the near memory core particle and the in-memory computing unit through hybrid bonding and / or TSV (Through Silicon Via). The storage and calculation integrated structure is applied to high-performance calculation, the high-performance calculation requirement and the large-capacity storage requirement can be met at the same time, the high-performance calculation of the system is maximized, and support is provided for the development of the calculation power technology from the hardware structure.

Techniques are provided for microservices management and orchestration. A chart package is selectively retrieved from a chart repository based upon the chart package corresponding to a set of services to host within a cluster and dependencies amongst the set of services. A set of container images may be retrieved from a container repository based upon the set of container images corresponding to the set of services. A cluster may be created within a computing environment. The set of services may be deployed as resources of the computing environment within the cluster and the dependencies may be configured using the chart package and the set of container images.

Various embodiments herein provide techniques to enable communication between a user equipment (UE) microservice and a microservice of a wireless cellular network via service mesh. A first solution is described, in which the service mesh is in the network, and the network includes a service mesh proxy to communicate with the UE. A second solution is also described, in which the UE is part of the cellular network service mesh and includes a service mesh proxy in the UE. Other embodiments may be described and claimed.

A system and method in a building or vehicle for an actuator operation in response to a sensor according to a control logic, the system comprising a router or a gateway communicating with a device associated with the sensor and a device associated with the actuator over in-building or in-vehicle networks, and an external Internet-connected control server associated with the control logic implementing a PID closed linear control loop and communicating with the router over external network for controlling the in-building or in-vehicle phenomenon. The sensor may be a microphone or a camera, and the system may include voice or image processing as part of the control logic. A redundancy is used by using multiple sensors or actuators, or by using multiple data paths over the building or vehicle internal or external communication. The networks may be wired or wireless, and may be BAN, PAN, LAN, WAN, or home networks.

The present application relates to the field of accelerators, and discloses an accelerator architecture for near IO pipeline computing, and an AI acceleration system. A multi-channel direct access module comprises N DRAM controllers, and the N DRAM controllers are connected to DRAMs in a one-to-one correspondence; each DRAM controller is at least connected to k DMA controllers, and is connected to a corresponding core group cluster by means of the DMA controllers; a pipeline synchronization ring is connected to N core group clusters and comprises M cascaded forward transmission blocks and M cascaded backward transmission blocks, and the head-end forward transmission block and the tail-end forward transmission block are respectively connected to a data receiving module and a data transmitting module; the output of the tail-end forward transmission block is cascaded to the first backward transmission block; the ith forward transmission block and the (M-i)th backward transmission block correspond to each other in a front-rear direction, and are jointly connected to at least one computing core group. The accelerator of the architecture replaces a traditional multi-level cache structure, reduces the time delay caused multi-layer search, and accelerates the computing rate between the interior of the accelerator and the accelerator.

A method of managing distribution of power among different hardware entities of a central computing unit for a vehicle, and / or different software processes running on the CCU, the method comprising: assigning to each element of a set of different hardware entities of the CCU and / or different software processes running on the CCU a respective demand class defining a priority level for powering this respective hardware entity or software process; determining an amount of power being available to be supplied to the CCU; defining a power distribution scheme for distributing the available power, at least in parts, among different elements of the set as a function of the determined amount of available power and the assigned demand classes of these elements of the set; and controlling the distribution of the available amount of power, or parts thereof, among the different elements of the set according to the power distribution scheme.

Method, device and computer program product for wireless communication are provided. A method includes: transmitting, by an application function to a first application server, a tunnel ready notification to allow the first application server to transfer an application layer traffic to a second application server via a tunnel between a first local user plane function for the first application server and a second local user plane function for the second application server.

In one example, a communications system includes a unified communications platform and a channel-communications management circuit. The unified communications platform is to process different types of communications services respectively using different types of communications channels. The channel-communications management circuit may be used to provide an effective merging of data communications received via the different types of communications services to develop an interaction record for a reply communication on a preferred channel and / or for use in a subsequently-received inbound data communication. The channel-communications management circuit may also react to a subsequently-received inbound data communication such as by using the interaction record in another communication subsequent to the inbound data communications, and / or by accessing the record and / or replying to content in the different types of communications services based on a determined identity of a sender or participant of the data communications.

A computer-implemented method for trace-driven call-graph-aware proactive coordinated autoscaling of component microservices in an application includes generating performance-resource elasticity models of endpoints of the component microservices of the application. Workload levels of the endpoint of the component microservices is predicted based on user traffic observed at a front end service. A trace-level performance of the application is predicted for different microservice replica scaling based on the performance-resource elasticity models at end points, the ends points on the trace call graph and the predicted workload levels. A microservice replica scaling is recommended for each of the component microservices to meet predefined trace-level user service level objectives.

The invention provides a multi-chip system interrupt transmission method, chips and a multi-chip system, and aims to solve the problems of complex design and low efficiency caused by lack of an effective interrupt transmission mechanism in the prior art. The method comprises the following steps: receiving and collecting a local interrupt message which needs to be reported to the basic core particle by controlling an interrupt action of a first interrupt repeater arranged in the functional core particle; the first interrupt relay initiates an AXI write request, and writes a local interrupt message containing a global interrupt identifier into a specific target address pre-allocated by system software; and packaging the AXI write request into a data packet in a core grain interconnection protocol format through a core grain interconnection protocol controller of the functional core grain, and triggering the processor of the basic core grain to interrupt in response to the write-in of the local interrupt message.

The invention discloses a detection and power-on optimization method for contact resistance of an electric connector. The detection and power-on optimization method comprises an integrated design of a multi-parameter acquisition module, a real-time calculation engine and a piezoelectric regulation and control module. The multi-parameter acquisition module synchronously acquires the micro-friction coefficient, the electrochemical reaction product concentration and other physical quantities; the real-time calculation engine executes three-formula linkage calculation of basic contact resistance, vibration-friction coupling correction and service life attenuation; the piezoelectric regulation and control module dynamically outputs pre-tightening force to compensate pressure loss; the method solves the defect that multi-factor coupling is ignored in the prior art, improves the contact resistance detection precision and the service life prediction accuracy, guarantees the power-on reliability of the electric connector, and is suitable for a high-reliability power electronic system.

Techniques for providing administrator-authorized applications are provided. In an example method, a computing device accesses a first application configuration for a first application. The computing device receives a first request to access a resource by the first application on behalf of one or more users and requests, from an authorization provider, authorization to access the resource by the first application on behalf of the one or more users. The computing device receives the authorization and updates the first application configuration with information about the authorization. The computing device receives a first indication from a first client device associated with a first user to add the first application to the first client device and determines a user authorization for the first user to access the resource using the first application based on the information about the authorization. The computing device provides access to the resource based on the user authorization.

The invention discloses a microprocessor dynamic power consumption optimization system based on deep learning, which belongs to the technical field of microprocessor power consumption management, and comprises a working load feature extraction module, a neural network prediction module, a dynamic core distribution module and a particle size power supply management module, the working load feature extraction module extracts feature parameters of calculation intensity, memory access intensity and input and output intensity of an application program in real time through a hardware circuit; the neural network prediction module predicts future power consumption and performance requirements based on a deep reinforcement learning network; the dynamic core distribution module intelligently selects an optimal core combination; the particle size power supply management module independently executes dynamic voltage frequency regulation on each core; according to the invention, accurate power consumption optimization of the heterogeneous multi-core processor is realized through deep coupling and closed-loop cooperation of the four modules, and compared with the prior art, the energy efficiency ratio is improved by more than 40%, and the power consumption prediction error is reduced to be within 5%.

There is provided a method for merging data frames performed by a data frame merge device for a vehicle network system. The method comprises receiving a plurality of control data frames from a lower level of the vehicle network system; and merging the plurality of control data frames for a preset standby time in a traffic section in which the plurality of the control data frames are not transmitted to a higher level of the vehicle network system.

Draft message object collaboration in a group-based communication platform is described. A request to generate a message object can be received from a first client associated with a first entity of a group-based communication platform. A first instance of a composition user interface, configured to enable a draft of the message object to be generated, can be presented via the first client and a request to add a second entity as a collaborator can be received. A second instance of the composition user interface can be presented via a second client of the second entity. A modification to the draft of the message object can be received and, in response to receiving the modification, the message object can be updated as presented via respective instances of the composition user interface.

The invention discloses a server case unit and a server cabinet, and relates to the technical field of servers, the server case unit comprises a computing node and a switching node, the computing node is orthogonally connected with the switching node, the switching node is provided with a data interface, the data interface is used for being connected with another data interface, and the computing node is connected with the switching node. The computing node is used for realizing networking among a plurality of server case units, the computing node comprises an external interface group, and at least one external interface in the external interface group is used for being connected with a server machine head, so that the ratio of the computing node to the server machine head is adjusted. Through the design of the modularized server case unit, a single server case unit can be used as an independent high-density reasoning server; and convenient networking can be performed in the server cabinet through the data interface on the back surface of the server case unit, so that a large-scale training cluster can be constructed. And an external interface group is designed in the computing node, so that the flexible configuration of the ratio between the server head and the computing node is realized.

An NFV infrastructure system based on a container infrastructure includes a master node configured to distribute and manage a virtual network function (VNF) which is an individual network function according to a request by an administrator; and a worker node of an extended container infrastructure structure which allocates the distributed VNF to a VM based infrastructure or a container based infrastructure, wherein a resource model between the master node and the worker node is a resource model which is the same as a resource model according to the request by the administrator.

The invention provides a bus link layer, an on-chip bus and a chip, and relates to the technical field of chip design and manufacture, and the bus link layer comprises an upstream virtual channel distributor which is used for determining an upstream virtual channel based on a credit value of each virtual channel; the upstream virtual channel memory is used for receiving the target data sent by the upstream module and storing the target data to a storage space corresponding to an upstream virtual channel; the downstream virtual channel distributor is used for determining a downstream virtual channel based on the credit value of each virtual channel; and the downstream virtual channel memory is used for storing the target data to a storage space corresponding to a downstream virtual channel and sending the target data to a downstream module. According to the device provided by the invention, the upstream module and the downstream module do not need to integrate and manage a huge storage array, so that the overall layout and wiring of the chip are more flexible, the time sequence convergence is easier, and the design complexity and the physical implementation difficulty of the chip are remarkably reduced.