544 results about "Branch" patented technology

The invention belongs to the technical field of computers, particularly relates to a prefetch instruction management method, system and equipment, and aims to solve the problem of low instruction fetch efficiency of an instruction prefetch technology. The method comprises the following steps: receiving branch prediction information from a branch prediction unit, and performing label comparison on table entries in an instruction fetching target queue and the branch prediction information; under the condition that the table item is hit, querying an instruction fetching address corresponding to the branch prediction information in the hit table item; under the condition that the table item is not hit, a new storage table item is allocated to the branch prediction information, and an instruction fetching address carried by the branch prediction information is determined through the storage table item; in response to a received prefetching request sent by the prefetching unit, determining a target table item based on the prefetching request, and returning an instruction fetching address queried in the target table item to the prefetching unit; and storing the stable cache line in the target table item to a flow buffer area. According to the method, multiple prediction requests can be processed in parallel, the front-end throughput is improved, and the instruction fetching efficiency is improved.

The invention relates to an instruction execution method, device and system, equipment and a storage medium. The instruction execution method comprises the steps of obtaining current instruction information and branch historical information of a current branch instruction; calculating a jump probability value of the branch instruction based on the current instruction information and the branch historical information through a pre-trained reasoning model deployed on a hardware accelerator; determining a branch prediction result according to the jump probability value and a set branch prediction decision; wherein the branch prediction result comprises a prediction execution result and target instruction information; and based on the prediction execution result, executing a target instruction determined according to the target instruction information. According to the method provided by the invention, the accuracy of branch prediction is improved, the performance loss of the processor caused by misprediction is reduced, and the accuracy of instruction execution is also ensured.

A system that includes at least one multi-threaded processor forms a multitude of converged thread sub-groups from a main thread group, wherein each thread sub-group includes a common code block. A loop is configured to jump to a different target address of a branch instruction in an order determined by a priority configured for each different target address.

The invention relates to the technical field of GPGPU (General Purpose Graphics Processing Unit), and relates to an SIMT stack and thread scheduling optimization method and device for GPGPU (General Purpose Graphics Processing Unit) branch instructions, a medium and a GPGPU architecture. The method comprises the steps that in a GPGPU, an SIMT stack is optimized, an SM unit is expanded to be a double-instruction assembly line, and a main thread beam scheduler and an auxiliary thread beam scheduler are arranged. And in a non-branch state, half threads of each tube of the scheduler are executed in parallel by the assembly line. When a branch instruction is encountered, instruction addresses, thread masks and branch reunion points of the two branch paths are pressed into the SIMT stack. Judging conflicts according to the thread masks; if conflicts exist, performing serial execution; and if no conflict exists, executing on double pipelines in parallel. And when the branch is completed to a reunion point, the SIMT stack pops up an entry, and the execution is continued. The method has remarkable effects in the aspects of improving the thread resource utilization rate, improving the calculation efficiency, simplifying the branch control complexity, enhancing the GPGPU flexibility and the like.

Apparatuses and methods for branch prediction are provided. Branch prediction circuitry generates prediction with respect to branch instructions of whether those branches will be taken or not-taken. Hypervector generation circuitry assigns an arbitrary hypervector in deterministic dependence on an address of each branch instruction, wherein the hypervectors comprises at least 500 bits. Upon the resolution of a branch a corresponding hypervector is added to a stored taken hypervector or a stored not-taken hypervector in dependence on the resolution of the branch. The branch prediction circuitry generates a prediction for a branch instructions in dependence on a mathematical distance metric of a hypervector generated for that branch instruction from the stored taken hypervector or the not-taken hypervector.

A multi-core processor according to some example embodiments may be a multi-core processor including a plurality of cores, and may include a first core that receives a task migration instruction, and transmits metadata including branch prediction data obtained during execution of a migration subject task determined as a subject of the task migration instruction among a plurality of tasks, to an external memory, and a second core that receives a task execution instruction, and reads the metadata from the external memory on the basis of the task execution instruction, and executes the migration subject task using the metadata.

The embodiment of the invention discloses a processor front-end branch prediction and instruction fetching verification method and device and a storage medium, relates to the technical field of processor function verification, and can reduce the complexity of instruction scene construction and improve the verification efficiency. The method comprises the following steps: acquiring instruction fetching information and a test vector; the fetch information comprises a fetch address range and branch prediction information of the target instruction block, and jump instruction marking information is configured in the test vector; according to the fetch address range and the jump instruction mark information, generating an instruction boundary of each cache line in the fetch address range; respectively associating the branch prediction information and the jump instruction mark information to the instruction boundary of each cache line, and constructing to obtain an instruction stream; the instruction stream is used for simulating execution logic of processor front-end branch prediction and instruction fetching; and decoding simulation verification is carried out based on the instruction stream, and processor front-end branch prediction and instruction fetching accuracy is determined. The method is suitable for a verification scene of processor front-end branch prediction and instruction fetching.

Techniques for early resteering of a branch misprediction are described. Examples detailed herein use a virtual run-ahead mechanism in the core. On a branch misprediction for an hard-to-predict (H2P) branch, a subset of the backslice of the H2P branch are replayed from the out-of-order engine directly (while the main thread is flushing and restarting execution from the front-end).

In some implementations, a code testing device may receive, from a first device associated with a developer, a first instruction to merge a first code branch. The code testing device may perform a first set of tests, associated with a first environment, in response to the first instruction. The code testing device may merge the first code branch based on the first set of tests resulting in a passing outcome for the first code branch. The code testing device may receive, from a second device associated with a reviewer, a second instruction to deploy the merged first code branch. The code testing device may perform a second set of tests, associated with a second environment, in response to the second instruction. The code testing device may deploy the merged first code branch based on the second set of tests resulting in a passing outcome for the merged first code branch.

The invention discloses an SIMT architecture-oriented program branch compilation optimization system, which relates to the technical field of program branch compilation optimization, and comprises a compiler rear end which takes code intermediate representation as input, executes hardware-related optimization and code generation work, converts the intermediate representation into binary codes and stores the binary codes in a video memory; the SIMT execution unit is responsible for reading the binary code from the video memory and executing a corresponding instruction; the SIMT stack is responsible for storing an address and an active mask of a non-jump branch when the Split instruction is executed, and is responsible for loading the stored non-executed branch and executing or setting the active mask to perform branch reconvergence after the Join instruction is executed; the branch performance analysis module is responsible for recording distribution of active threads of different branch paths; and the branch optimization module is responsible for analyzing and optimizing the code intermediate representation according to the recorded information, and replacing the input of the rear end of the compiler by using the optimized code intermediate representation. The code execution efficiency can be improved.

The invention provides a branch prediction method, a loop stack structure and related equipment, and the method comprises the steps: obtaining a branch instruction, determining whether the branch instruction belongs to a target instruction or not, and enabling the target instruction to be a backward jump condition branch instruction; if the branch instruction belongs to the target instruction, executing a first updating operation for a loop stack according to the branch instruction; if the branch instruction does not belong to the target instruction, the type of the branch instruction is determined, a second updating operation is executed on the loop stack according to the type of the branch instruction, and the type of the branch instruction comprises a calling function type, a loop jumping-out type and a returning type.

The invention discloses a mimicry thought-based code dynamic obfuscation compiling method, system and equipment. The method comprises the following steps of: sensing a source code, and performing compiler annotation on a key function in combination with a large language model and expert knowledge; a global character string constant is extracted, an ASCII value of a character is coded into an MBA expression, a decoding function is inserted into a position where the constant is used, mimicry replacement is performed on an original character string in a data segment, and functions of other programs are disguised; adding a clone block irrelevant to function logic, and constructing a mimicry branch by using a dynamic opaque predicate as a jump condition; adding an equivalent heterogeneous shadow branch, and using a random predicate as a jump condition; a flower instruction is inserted, and an MBA expression is used for instruction replacement; and performing control flow flattening on the function. According to the method, the mimicry multi-variant thought is combined, accurate diversified confusion compilation is performed, and key fragments of program codes in the fields of industrial control, power grids, Internet of Things and the like are effectively protected.

Embodiments of the invention provide a compiling method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of converting a branch instruction in a target function into a control flow pseudo instruction related to an architecture of a compiler; performing a first instruction processing operation on any control flow pseudo instruction, and performing a second instruction processing operation on a vector instruction of which the operand type corresponding to the operand is a first preset type; and under the condition that the operand type corresponding to the operand of the control flow pseudo instruction or the vector instruction is a second preset type, determining a target physical predicate register and replacing the virtual predicate register corresponding to the control flow pseudo instruction or the vector instruction with the target physical predicate register. In this way, the number of the generated instructions is reduced, and the running efficiency of the program is improved to a certain extent. The target physical predicate registers are respectively distributed for different control flows, so that the overall execution efficiency of the program is improved, and the parallel execution capability and throughput of the program are improved.

The invention discloses a design method of an advanced branch target address buffer area, which comprises the following steps of: S1, judging whether a first group of jumped branch instructions are unconditional direct branches or not, if so, entering S5; if not, entering S2; s2, judging whether the branch is a conditional direct branch, if so, entering S5; if not, entering S3; s3, when the first group of jump branch instructions are unconditional indirect branches, entering S4; s4, judging whether the actual jump address is the same as the address provided by the leading branch target address buffer area or not, and if not, resetting a saturation counter; if yes, the saturation counter counts, the first instruction block is expanded, and S5 is executed; and S5, linking the two instruction blocks. The invention further discloses a prediction system, and the flow predictor is introduced into the decoupling predictor. According to the method, the operation logic of the advanced branch target address buffer area is optimized, instruction parallel and instruction block extension connection are allowed, and the prediction efficiency is improved; the flow predictor is additionally arranged, the bubble waiting problem is solved, and the prediction speed is increased.

The invention provides an instruction pipeline processing method of a processor and the processor. A processor includes: a control module; the control module is set to execute the branch instruction speculatively according to the branch prediction direction when detecting that the first instruction subjected to initial decoding is the branch instruction, and execute the branch instruction if detecting that the second instruction subjected to initial decoding is the function call instruction or the function return instruction before the speculation execution result of the first instruction is generated. If yes, pausing all operations after the instruction processing assembly line performs initial decoding on the second instruction, and blocking the instruction fetching operation of the instruction processing assembly line on the next instruction until a speculation execution result of the first instruction is obtained; wherein the operation after the initial decoding comprises the step of carrying out a push-in or push-out operation of a return address stack (RAS) according to the second instruction. According to the technical scheme, the pollution risk caused by speculative execution of the branch instruction to the return address stack can be shielded, so that the hardware implementation logic of the return address stack is simplified, and the circuit area and power consumption are saved.

The invention provides an instruction obtaining method and device, equipment and a storage medium. The method comprises the steps that a first instruction is obtained; the first instruction is an instruction which is in an instruction fetching stage of the processor and is not executed; under the condition that the first instruction is a branch instruction, determining that the next instruction is a second instruction for skipping execution; searching a jump address, a jump cache line and pre-decoding information of the second instruction in the first branch target buffer; under the condition that the jump address, the jump cache line and the pre-decoding information of the second instruction are cached in the first branch target buffer, outputting the jump cache line and the pre-decoding information of the second instruction; and obtaining the second instruction according to the jump cache line and the pre-decoding information of the second instruction. According to the invention, the idle period can be eliminated while the accuracy of the first branch target buffer is ensured.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

The embodiment of the invention discloses a self-adaptive frequency modulation method and device which are used for improving the frequency modulation accuracy of a processor. The method comprises the steps that the computing device collects real-time monitoring data of the processor, the real-time monitoring data comprises one or more events monitored by a performance monitoring unit (PMU) of the processor, and the events comprise one or more of the following items: the number of instruction execution times, the cache hit rate and the branch prediction error rate. A predicted performance change rate of the processor is calculated based on the real-time monitoring data, the predicted performance change rate is determined based on a current performance change rate of the processor, the current performance change rate is determined based on the real-time monitoring data, and the predicted performance change rate is used for indicating the proportion of a reference performance value to an operation performance value of the processor. And determining a target frequency of the processor based on the target performance loss rate and the predicted performance change rate, wherein the target performance loss rate is used for indicating the predicted performance change rate tolerable by the processor.

The disclosed device uses a control circuit configured to (i) receive branch misprediction information corresponding to a mispredicted branch window of instructions and (ii) send a misprediction status of a memory access from the mispredicted branch window of instructions, and a cache prefetcher of a cache configured to train using a set of memory accesses that are updated in response to receiving the misprediction status from the control circuit.

The embodiment of the invention discloses an instruction processing method and device, a chip, equipment and a storage medium. The method comprises the steps that a to-be-executed branch instruction and a target thread bundle used for executing the branch instruction are acquired; the target thread bundle comprises K threads, P effective threads exist in the K threads, and the branch instruction needs to be executed and processed in each effective thread; wherein K > = P > = 1, and K and P are integers; performing thread compression processing on the target thread bundle to obtain a sub-thread bundle; the sub-thread bundle comprises P effective threads of the target thread bundle; obtaining the number of available execution units in the target processor, and selecting corresponding effective threads for the execution units from the sub-thread bundles according to the number of the available execution units; and calling the execution unit to execute the branch instruction in the corresponding effective thread. The instruction processing efficiency of the target processor can be improved.

The embodiment of the invention provides an instruction processing method and device, electronic equipment and a readable storage medium, and the method comprises the steps: based on multiple pieces of source data and branch conditions corresponding to a to-be-executed branch jump instruction in a source program, selecting at least two to-be-selected branches contained in the branch jump instruction, determining jump branches respectively corresponding to the plurality of pieces of source data; taking at least two pieces of source data with the same jump branches as at least two pieces of target data, and writing the at least two pieces of target data into a first vector register; the operation types of the jump branches of the at least two pieces of target data serve as target types, a target vector instruction is generated based on the target types and the first vector register, and the target vector instruction is used for executing the operation of the target types on the at least two pieces of target data in the first vector register; and executing the target vector instruction. And the instruction execution efficiency is improved.

The invention discloses a branch predictor selection method and device and a storage medium. The method comprises the steps of obtaining record data of a target jump instruction in a local historical register and a global historical register based on the target jump instruction; determining an instruction type of the target jump instruction based on the recorded data; determining a load state of the processor based on the operation parameters of the processor; and determining a target predictor according to the instruction type and the load state, and outputting a branch prediction result based on the target predictor. According to the selection method provided by the invention, the prediction accuracy can be improved, the adaptability is higher, the energy consumption is reduced, and the optimal balance between the prediction accuracy and the energy efficiency is realized.

A computer workflow including computer managed activities organized in an execution ordering and one or more conditional branching decision nodes is specified. One or more activity execution conditions associated with at least one of the plurality of computer managed activities are determined, wherein the one or more activity execution conditions comprise at least one branch execution condition associated with at least one of the one or more conditional branching decision nodes. The computer workflow is executed. Based on at least one of the one or more activity execution conditions, it is determined whether a condition to start an execution of the at least one of the plurality of computer managed activities is satisfied. Based on the at least one branch execution condition, it is dynamically determined whether the at least one of the plurality of computer managed activities is to be visualized.

An analysis function providing method executed by an analysis function providing device includes first analyzing a virtual machine of a script engine, and acquiring a hook point that is a part where an analysis code is inserted by applying a hook, and a virtual program counter that is a variable indicating an instruction of the virtual machine to be executed next, second analyzing an instruction set architecture that is a system of instructions of the virtual machine and acquiring a branch virtual machine instruction that is a virtual machine instruction that causes branch, and providing an analysis function by applying a hook, to the hook point of the script engine, the hook including processing of, when an exception has occurred, changing a destination pointed by the virtual program counter to a head of a basic block immediately after a basic block in which the exception has occurred.

The invention discloses a processor, a chip, equipment and an instruction execution method. The processor comprises a shared memory for storing first quantity information, second quantity information, third quantity information and fourth quantity information; the first number information is the total number of threads in the working group, the second number information is the number of threads waiting to be synchronized on the N instruction branches, the third number information is the number of threads not needing to be synchronized, and the fourth number information is the number of finished threads. And the synchronization instruction assembly line is used for calculating the sum of the thread numbers of the second, third and fourth number information, and when the sum of the thread numbers is equal to the total number of the threads, unfinished threads in the working group are triggered to execute an instruction behind the rendezvous point. According to the scheme, under the condition that the sum of the thread numbers is equal to the total thread number, the synchronization instruction assembly line can trigger the threads which are not finished in the working group to continue to execute subsequent instructions, and the problem of task deadlock caused by the fact that part of the threads cannot reach the synchronization point is avoided.

The present application relates to the field of processors, and discloses an instruction acquisition method, a central processing unit, a device, a medium, and a program product. The method comprises: acquiring a main path predicted for each branch instruction (310); on the basis of the magnitude relationship between the historical error prediction quantity of the main path for the same branch instruction and a confidence threshold, determining a confidence level of the main path corresponding to each branch instruction (320); determining a confidence level proportion (330), the confidence level proportion being the proportion of branch instructions corresponding to a first level in all instructions, and the first level being a confidence level in which the historical error prediction quantity is greater than the confidence threshold; and taking the confidence level proportion as an expected proportion to serve as a control objective, adjusting the confidence threshold (340). According to the method, the problem of the proportion of first branch instructions (branch instructions corresponding to a main path of which the confidence level is the first level) in all instructions being too large due to a fixed threshold being too small for different load programs can be avoided.

The invention discloses a hybrid branch predictor capable of dynamically selecting different prediction methods and application, and relates to the technical field of high-performance processor design, the hybrid branch predictor mainly comprises a branch direction predictor and a branch target predictor; the branch direction predictor is used for predicting whether a branch instruction jumps or not; and the branch target predictor is used for predicting a specific jump target address when the branch direction is predicted to be jump. By implementing the hybrid branch predictor capable of dynamically selecting different prediction methods and the application provided by the invention, the branch prediction accuracy can be improved, and the hardware resource overhead can be reduced.

Embodiments of the present application disclose an adaptive frequency modulation method and apparatus, which are used for improving the frequency modulation accuracy of a processor. The method in the embodiments of the present application comprises: a computing device acquiring real-time monitoring data of a processor, the real-time monitoring data comprising one or more events monitored by a performance monitoring unit (PMU) of the processor, and the events comprising one or more of the following: the number of times of instruction execution, a cache hit rate, and a branch prediction error rate; on the basis of the real-time monitoring data, computing a predicted performance change rate of the processor, the predicted change rate being determined on the basis of a current performance change rate of the processor, the current performance change rate being determined on the basis of the real-time monitoring data, and the predicted performance change rate being used for indicating the ratio of a reference performance value of the processor relative to an operating performance value; and, on the basis of a target performance loss rate and the predicted performance change rate, determining a target frequency of the processor, the target performance loss rate being used for indicating a predicted performance change rate tolerable by the processor.

The invention relates to the technical field of cloud fusion application operation support platforms, and discloses a session flow intelligent scheduling method under a fusion communication architecture, which comprises the following steps: monitoring a session flow logic sequence number of a current node; constructing an asynchronous mirror instance at the target node, and obtaining a computing power comparison parameter; adjusting an asynchronous mirror instance instruction execution rate to execute serial number chasing; after the sequence number difference value enters a synchronous threshold value, processor assembly line branch prediction data is injected, and instruction prefetching sequence filling is driven; according to the instruction level feature injection and execution phase alignment method, hardware execution momentum imbalance in a heterogeneous computing power environment is eliminated through instruction level feature injection and execution phase alignment, and progress connection and logic consistency of session streams at a migration interface are guaranteed.

According to the instruction fetching module and the processor, a first prediction unit generates and backwards sends a first prediction address according to a first historical reference address and a stack top address; the instruction queue generates corresponding hit information according to the first historical reference address and sends the hit information backwards; when the first historical reference address is not hit, the instruction cache obtains and sends an instruction corresponding to the first historical reference address backwards; when the hit information is hit, the instruction queue sends an instruction corresponding to the hit information to the second-order prediction unit; and the second-order prediction unit generates a second prediction address according to the received instruction and the reference address, and if the second prediction address is different from the first prediction address, the second prediction address is provided for the reference unit. The address prediction speed can be guaranteed by arranging the first-order prediction unit, so that the instruction fetching speed is increased, meanwhile, the second-order prediction unit is arranged for common prediction, the accuracy of the prediction result can be guaranteed, the problem of insufficient bandwidth utilization caused by sequential instruction fetching only is solved, and the branch instruction processing efficiency is improved.