430 results about "Branch" patented technology

The invention belongs to the technical field of computers, particularly relates to a prefetch instruction management method, system and equipment, and aims to solve the problem of low instruction fetch efficiency of an instruction prefetch technology. The method comprises the following steps: receiving branch prediction information from a branch prediction unit, and performing label comparison on table entries in an instruction fetching target queue and the branch prediction information; under the condition that the table item is hit, querying an instruction fetching address corresponding to the branch prediction information in the hit table item; under the condition that the table item is not hit, a new storage table item is allocated to the branch prediction information, and an instruction fetching address carried by the branch prediction information is determined through the storage table item; in response to a received prefetching request sent by the prefetching unit, determining a target table item based on the prefetching request, and returning an instruction fetching address queried in the target table item to the prefetching unit; and storing the stable cache line in the target table item to a flow buffer area. According to the method, multiple prediction requests can be processed in parallel, the front-end throughput is improved, and the instruction fetching efficiency is improved.

The embodiment of the invention discloses a processor front-end branch prediction and instruction fetching verification method and device and a storage medium, relates to the technical field of processor function verification, and can reduce the complexity of instruction scene construction and improve the verification efficiency. The method comprises the following steps: acquiring instruction fetching information and a test vector; the fetch information comprises a fetch address range and branch prediction information of the target instruction block, and jump instruction marking information is configured in the test vector; according to the fetch address range and the jump instruction mark information, generating an instruction boundary of each cache line in the fetch address range; respectively associating the branch prediction information and the jump instruction mark information to the instruction boundary of each cache line, and constructing to obtain an instruction stream; the instruction stream is used for simulating execution logic of processor front-end branch prediction and instruction fetching; and decoding simulation verification is carried out based on the instruction stream, and processor front-end branch prediction and instruction fetching accuracy is determined. The method is suitable for a verification scene of processor front-end branch prediction and instruction fetching.

The invention discloses a mimicry thought-based code dynamic obfuscation compiling method, system and equipment. The method comprises the following steps of: sensing a source code, and performing compiler annotation on a key function in combination with a large language model and expert knowledge; a global character string constant is extracted, an ASCII value of a character is coded into an MBA expression, a decoding function is inserted into a position where the constant is used, mimicry replacement is performed on an original character string in a data segment, and functions of other programs are disguised; adding a clone block irrelevant to function logic, and constructing a mimicry branch by using a dynamic opaque predicate as a jump condition; adding an equivalent heterogeneous shadow branch, and using a random predicate as a jump condition; a flower instruction is inserted, and an MBA expression is used for instruction replacement; and performing control flow flattening on the function. According to the method, the mimicry multi-variant thought is combined, accurate diversified confusion compilation is performed, and key fragments of program codes in the fields of industrial control, power grids, Internet of Things and the like are effectively protected.

The invention discloses a design method of an advanced branch target address buffer area, which comprises the following steps of: S1, judging whether a first group of jumped branch instructions are unconditional direct branches or not, if so, entering S5; if not, entering S2; s2, judging whether the branch is a conditional direct branch, if so, entering S5; if not, entering S3; s3, when the first group of jump branch instructions are unconditional indirect branches, entering S4; s4, judging whether the actual jump address is the same as the address provided by the leading branch target address buffer area or not, and if not, resetting a saturation counter; if yes, the saturation counter counts, the first instruction block is expanded, and S5 is executed; and S5, linking the two instruction blocks. The invention further discloses a prediction system, and the flow predictor is introduced into the decoupling predictor. According to the method, the operation logic of the advanced branch target address buffer area is optimized, instruction parallel and instruction block extension connection are allowed, and the prediction efficiency is improved; the flow predictor is additionally arranged, the bubble waiting problem is solved, and the prediction speed is increased.

The invention provides an instruction pipeline processing method of a processor and the processor. A processor includes: a control module; the control module is set to execute the branch instruction speculatively according to the branch prediction direction when detecting that the first instruction subjected to initial decoding is the branch instruction, and execute the branch instruction if detecting that the second instruction subjected to initial decoding is the function call instruction or the function return instruction before the speculation execution result of the first instruction is generated. If yes, pausing all operations after the instruction processing assembly line performs initial decoding on the second instruction, and blocking the instruction fetching operation of the instruction processing assembly line on the next instruction until a speculation execution result of the first instruction is obtained; wherein the operation after the initial decoding comprises the step of carrying out a push-in or push-out operation of a return address stack (RAS) according to the second instruction. According to the technical scheme, the pollution risk caused by speculative execution of the branch instruction to the return address stack can be shielded, so that the hardware implementation logic of the return address stack is simplified, and the circuit area and power consumption are saved.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

The disclosed device uses a control circuit configured to (i) receive branch misprediction information corresponding to a mispredicted branch window of instructions and (ii) send a misprediction status of a memory access from the mispredicted branch window of instructions, and a cache prefetcher of a cache configured to train using a set of memory accesses that are updated in response to receiving the misprediction status from the control circuit.

The embodiment of the invention discloses an instruction processing method and device, a chip, equipment and a storage medium. The method comprises the steps that a to-be-executed branch instruction and a target thread bundle used for executing the branch instruction are acquired; the target thread bundle comprises K threads, P effective threads exist in the K threads, and the branch instruction needs to be executed and processed in each effective thread; wherein K > = P > = 1, and K and P are integers; performing thread compression processing on the target thread bundle to obtain a sub-thread bundle; the sub-thread bundle comprises P effective threads of the target thread bundle; obtaining the number of available execution units in the target processor, and selecting corresponding effective threads for the execution units from the sub-thread bundles according to the number of the available execution units; and calling the execution unit to execute the branch instruction in the corresponding effective thread. The instruction processing efficiency of the target processor can be improved.

The invention discloses a processor, a chip, equipment and an instruction execution method. The processor comprises a shared memory for storing first quantity information, second quantity information, third quantity information and fourth quantity information; the first number information is the total number of threads in the working group, the second number information is the number of threads waiting to be synchronized on the N instruction branches, the third number information is the number of threads not needing to be synchronized, and the fourth number information is the number of finished threads. And the synchronization instruction assembly line is used for calculating the sum of the thread numbers of the second, third and fourth number information, and when the sum of the thread numbers is equal to the total number of the threads, unfinished threads in the working group are triggered to execute an instruction behind the rendezvous point. According to the scheme, under the condition that the sum of the thread numbers is equal to the total thread number, the synchronization instruction assembly line can trigger the threads which are not finished in the working group to continue to execute subsequent instructions, and the problem of task deadlock caused by the fact that part of the threads cannot reach the synchronization point is avoided.

The invention discloses a hybrid branch predictor capable of dynamically selecting different prediction methods and application, and relates to the technical field of high-performance processor design, the hybrid branch predictor mainly comprises a branch direction predictor and a branch target predictor; the branch direction predictor is used for predicting whether a branch instruction jumps or not; and the branch target predictor is used for predicting a specific jump target address when the branch direction is predicted to be jump. By implementing the hybrid branch predictor capable of dynamically selecting different prediction methods and the application provided by the invention, the branch prediction accuracy can be improved, and the hardware resource overhead can be reduced.

The invention relates to the technical field of cloud fusion application operation support platforms, and discloses a session flow intelligent scheduling method under a fusion communication architecture, which comprises the following steps: monitoring a session flow logic sequence number of a current node; constructing an asynchronous mirror instance at the target node, and obtaining a computing power comparison parameter; adjusting an asynchronous mirror instance instruction execution rate to execute serial number chasing; after the sequence number difference value enters a synchronous threshold value, processor assembly line branch prediction data is injected, and instruction prefetching sequence filling is driven; according to the instruction level feature injection and execution phase alignment method, hardware execution momentum imbalance in a heterogeneous computing power environment is eliminated through instruction level feature injection and execution phase alignment, and progress connection and logic consistency of session streams at a migration interface are guaranteed.

According to the instruction fetching module and the processor, a first prediction unit generates and backwards sends a first prediction address according to a first historical reference address and a stack top address; the instruction queue generates corresponding hit information according to the first historical reference address and sends the hit information backwards; when the first historical reference address is not hit, the instruction cache obtains and sends an instruction corresponding to the first historical reference address backwards; when the hit information is hit, the instruction queue sends an instruction corresponding to the hit information to the second-order prediction unit; and the second-order prediction unit generates a second prediction address according to the received instruction and the reference address, and if the second prediction address is different from the first prediction address, the second prediction address is provided for the reference unit. The address prediction speed can be guaranteed by arranging the first-order prediction unit, so that the instruction fetching speed is increased, meanwhile, the second-order prediction unit is arranged for common prediction, the accuracy of the prediction result can be guaranteed, the problem of insufficient bandwidth utilization caused by sequential instruction fetching only is solved, and the branch instruction processing efficiency is improved.

According to the branch prediction method provided by the invention, the branch prediction result is obtained by indexing the historical branch prediction instructions in the branch prediction condition table, and the relevance between the historical branch prediction instructions can be well utilized, so that the success rate of branch prediction is greatly improved; meanwhile, the last four bits of the branch prediction instruction and values in the global historical register are subjected to logical operation, an operation value is obtained and then indexed, and the influence of the alias of the branch prediction instruction on branch prediction can be reduced; meanwhile, when the branch prediction result is skipping and the operation code of the branch prediction result is matched with the operation code of the indexed historical branch prediction instruction, the branch prediction result is trusted, so that the branch prediction accuracy is further improved; and moreover, the jump address is obtained by adopting a direct operation method, so that the area overhead and the delay caused by storing a large number of branch addresses by the BTB (Branch Target Buffer) can be saved.

The invention discloses a test case generation method, a branch predictor verification method and related equipment, and the test case generation method comprises the steps: obtaining a target global branch historical sequence which is generated by a TAGE branch predictor in a target application scene; according to the target global branch historical sequence, a corresponding target linear address sequence is obtained, and the target linear address sequence is obtained by arranging addresses of a plurality of target branch instructions in a target branch instruction stream in sequence; and according to the obtained multiple target linear address sequences, generating a target test case for testing the target branch instruction stream. According to the technical scheme provided by the embodiment of the invention, the verification coverage rate of the TAGE branch predictor can be improved, so that the verification efficiency and accuracy of the TAGE branch predictor are improved.

A branch prediction device includes a hierarchy of successively slower to access branch target buffers that store branch target buffer entries identifying branch instructions, branch prediction circuitry configured to predict future branch instructions, and a branch target buffer prefetch table coupled to receive candidate entries corresponding to predicted future branch instruction branch target buffer misses, each entry of the candidate entries corresponding to a precursor branch instruction, and to receive predicted precursor branch instructions that trigger promotion of an entry in a branch target buffer of the branch target buffers to a faster branch target buffer of the branch target buffers.

The invention relates to the technical field of software configuration management, and discloses a monorepo-based multi-version control and management method, which comprises the following steps: receiving a version switching instruction containing a target global version identifier and an environment identifier; loading the physically isolated environment version configuration file from a preset path according to the environment identifier; a target configuration node corresponding to the target global version identifier is positioned in the configuration file, recursive branch information merging operation is executed based on inheritance attributes and branch attributes in the node, and a final branch configuration set containing all sub-module target states is generated; and traversing the final branch configuration set, and calling a version control tool to switch the working area state of each sub-module to the corresponding target sub-module version identifier. Through the environment isolation and increment inheritance model, the problems of version definition redundancy and environment confusion in a multi-module warehouse are solved, and accurate backtracking and atomization switching of sub-module states are achieved.

The embodiment of the invention discloses an instruction prefetching method, a processor, electronic equipment and a computer readable storage medium. The method comprises the following steps: predicting and generating an instruction fetching block of a target instruction based on a branch prediction unit, and sending the instruction fetching block into an instruction fetching target queue; if the fetch block does not carry the first group of index information and the first path information of the target instruction, sending a prefetch request to an instruction cache unit based on the fetch target queue so as to cache the target instruction into the instruction cache unit; based on an instruction fetch unit, reading a fetch block from the fetch target queue so as to read a target instruction from an instruction cache unit; if the fetch block carries the first group of index information and the first path information, the fetch block is read from the fetch target queue based on the instruction fetch unit to obtain the first group of index information and the first path information, and the target instruction is read from the instruction cache unit according to the first group of index information and the first path information, so that redundant pre-fetch requests are reduced, and the operation efficiency is improved. And the power consumption of the processor is reduced.

The embodiment of the invention relates to the technical field of computers, in particular to an R-BTB table item retrieval method and system, computer equipment and a storage medium. The R-BTB table item retrieval method comprises the following steps: searching a branch prediction R-BTB table according to an obtained to-be-retrieved address value to obtain a current table item where the to-be-retrieved address value is located; determining a next retrieval address value according to the head address of the current table item and the byte length of the current instruction block of the current table item; taking the next retrieval address value as a to-be-retrieved address value, re-searching from the branch prediction R-BTB table to obtain a next table item where the next retrieval address value is located, and re-determining a new retrieval address value according to the head address of the next table item and the byte length of the next instruction block of the next table item until a set number of table items are retrieved; and according to all the obtained retrieval address values, performing parallel searching in the corresponding table entries to obtain a target instruction corresponding to each retrieval address value. The R-BTB table item retrieval method provided by the invention is higher in efficiency.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

The invention provides an RISC-V-oriented eBPF cycle vectorization compiling method and device, and the method comprises the steps: generating an RVV vector machine code, executing the parallel operation when a condition is satisfied, achieving the parallel processing of a single instruction and multiple data, carrying out the serial conversion of the time dimension of eBPF cycle into the parallel spatial dimension of an RVV vector, remarkably improving the processing throughput, and improving the compiling efficiency. And the task response time delay and the CPU occupancy rate are reduced. According to the RVV vector execution mode, a large number of repeated loop control instructions and memory read-write instructions can be reduced, the register overflow problem caused by eBPF scalar register resource shortage is relieved, the cache pressure and the branch prediction failure rate are reduced, and the energy efficiency ratio is increased. Meanwhile, an RVV vector machine code and a scalar fallback code are generated, a parallel priority and scalar bottom double execution path is formed, and it is ensured that under the conditions that a hardware environment is not supported, the data size does not reach a threshold value, vectorization verification fails or operation is abnormal, the scalar fallback code can be seamlessly switched to be executed.

The invention relates to an instruction type-independent visual language navigation method, which comprises the following steps of: 1, mixing various types of instructions to form a mixed instruction text # imgabs0 #, carrying out text coding on I, and classifying through an instruction discriminator to obtain a classification probability p < omega > as an expert routing basis in an expert network; step 2, a cross-modal hard branch routing expert network CrossMoE is constructed; and step 3, based on an LLM instruction specification, performing instruction specification on the mixed instruction text I by using a large language model LLM to obtain an instruction element set I ', and the like. The method disclosed by the invention has the superior technical effects that the processing capability of a system on various types of instructions can be effectively improved, and the defect that the performance of a traditional navigation model is reduced when the traditional navigation model processes the various types of instructions and faces complex and diversified instructions is overcome; complicated operation steps are avoided, man-machine interaction is more natural and smoother, and particularly, the use threshold of a non-technical user system is greatly reduced.

The embodiment of the invention relates to an instruction execution method and device, a processor and a related product, an MIMD framework is adopted in a GPU, a first SIMT stack and a second SIMT stack are configured for managing execution information of different branch basic blocks in the same thread bundle, and on the basis, the execution information of the different branch basic blocks in the same thread bundle can be managed through the first SIMT stack and the second SIMT stack. According to the method, the state of at least one of a first SIMT stack and a second SIMT stack is updated according to a basic block to be executed, and under the condition that the updated first SIMT stack and the updated second SIMT stack are both non-empty, instructions in all branch basic blocks are taken out respectively according to execution information of the first SIMT stack and execution information of the second SIMT stack and transmitted to an MIMD for concurrent execution. According to the method, when the execution channels of the MIMD concurrently execute the branch instructions, the resource utilization rate of the ALU can be improved, and therefore the running performance of a GPU program is improved.

The invention discloses a dynamic instruction fetch and instruction coverage method and a processor based on a double-track assembly line, and the dynamic instruction fetch method comprises the steps: when the current instruction fetch is a branch instruction, two instructions are fetched from a current instruction PC value plus 4 and a branch target address at the same time in a next clock period; and when the instruction is a non-branch instruction, taking one instruction in the next clock period. According to the instruction coverage method, primary and secondary parallel assembly lines are set, the primary assembly line processes an instruction with a previous instruction PC value plus 4, and the secondary assembly line processes a branch target address instruction; when branch jumping and target address matching are judged in the execution stage, instructions in all stages of the secondary assembly line cover instructions in corresponding stages of the main assembly line. The method can solve the problems of high delay, large misprediction penalty and low power consumption efficiency of branch prediction, and improves the performance of a processor.

The invention discloses an identification processing method and system for a difficult-to-predict branch, and the method comprises the steps: determining a branch instruction which is a difficult-to-predict branch in a program execution process according to information generated in a processor when the program is executed in history; when a branch instruction appears in the program execution process, whether the branch instruction is the determined branch difficult to predict or not is judged; under the condition that the branch instruction is a branch difficult to predict, information used for representing a jump relation when the program is executed is obtained, and the jump relation is the jump relation of the branch difficult to predict; and performing branch prediction on the difficult-to-predict branch at least according to the information used for representing the jump relation. According to the method and the device, the problem that the processing efficiency of a CPU (Central Processing Unit) is possibly reduced due to the fact that H2P branches are not processed differently during branch prediction is solved, so that the possibility is provided for improving the execution efficiency of the CPU.

The invention provides a cyclic branch prediction instruction fetching device, a processor and electronic equipment. A reference unit generates a reference address according to acquired address data; the instruction storage unit reads a historical reference address to pre-fetch an instruction, and when the instruction storage unit is hit, after K clock cycles, a target instruction corresponding to the historical reference address is transmitted to the first branch predictor; the first branch predictor is used for reading a historical reference address, performing address prediction according to the historical reference address and a target instruction corresponding to the historical reference address, and providing a predicted address to the reference unit; and the second branch predictor is used for reading the historical reference address, and providing the stored cycle start address to the reference unit under the condition that the historical reference address is the same as the cycle end address stored in the historical reference address and the number of to-be-cycled times is greater than 0. The instructions are reduced to maintain cyclic variables and judgment conditions, so that the complexity and maintenance difficulty of codes can be reduced, the acquisition efficiency of the instructions is improved, and the performance potential of a processor is fully exerted.

The invention discloses a register renaming device, a processor and a method for maintaining a register mapping table, and belongs to the technical field of computers. The register renaming device comprises a mapping table caching module, a control module, a recovery module and a reordering caching ROB module, and the recovery module is configured to rename a renamed register when a speculative path of a branch instruction is wrong and a copy distributed for the branch instruction is covered. And if the number of the program instructions between the program instruction pointed by the retirement pointer of the ROB module and the branch instruction in the ROB module is greater than the number of the program instructions on the speculative path, restoring the modification of the first register mapping table based on the branch instruction according to the copy and the ROB module. According to the register renaming device provided by the invention, unexpected modifications in the first register mapping table can be recovered by combining the copies and the ROB module under the condition that the number of the copies is smaller than the number of the branch instructions, the recovery efficiency is high, and the resource overhead is low.

The invention provides a software development testing method and system, electronic equipment and a storage medium, and the method comprises the steps: building connection with a testing environment in response to a performance testing instruction which is used for triggering a performance test of a program code of to-be-tested software and is generated based on a compilation success identifier of the program code; deploying an installation package generated by compiling the program code into a test environment, and performing performance test to obtain a target test value of a performance index; and if the target test value meets a threshold condition, determining that the performance test result is passed, thereby completing the software development test, the threshold condition comprising that the increment of the target test value is less than or equal to a preset increment threshold and the target test value is less than or equal to a preset upper limit threshold. After the program code compilation verification is passed, the performance test of the program code is triggered, so that the performance test is completed before the code is put in storage, and the problem that the program code with the performance problem is merged into a development branch warehouse can be effectively prevented.

The embodiment of the invention provides a processor pipeline device and an instruction processing method, the processor pipeline device comprises a branch prediction unit, an instruction fetching unit, a decoding unit and a compression detection subunit, the branch prediction unit predicts a jump direction and a jump target address of a branch instruction in a CPU front end; the branch prediction unit comprises a branch target buffer area BTB, the compression detection subunit detects whether N fetch blocks at the rear end of a jump target contain a jump instruction or not, and when the N fetch blocks do not contain the jump instruction, the N fetch blocks are compressed into a table item of the branch target buffer area BTB, and N is a natural number larger than 1; and when the table item is used for predicting the branch corresponding to the jump target, performing multi-beat access according to the maximum instruction fetching bandwidth of the branch prediction unit. According to the processor assembly line device provided by the embodiment of the invention, compression type access can be carried out during subsequent prediction, and the bandwidth of a prediction unit is improved.

According to the SIMT architecture branch processing system and method based on the structured nodes, explicit node marks are inserted into branch codes through a compiler, accurate control over active masks of all threads in the program execution process is achieved, and part of branch codes, not needing to be executed currently, of the threads are shielded; a full-branch consistent detection unit is designed to judge three mask states of'all true / all false / divergence 'of current active masks of the same group of threads, so that the operation of instructions of irrelevant branches is directly skipped under a full-branch consistent scene (all true / all false), all instructions of all branches are normally executed under a divergence scene, and all the instructions of all the branches are normally executed under the divergence scene. The active masks control which instructions are executed by each thread, and the state of the active mask of each thread is accurately controlled through node marks.

A microprocessor includes a prediction unit (PRU) comprising a fetch block (FBlk) predictor (FBP) that predicts a sequence of FBlks, each FBlk having a corresponding fetch block start address (FBSA), and branch predictors; a macro-op (MOP) cache (MOC) includes MOC entries (MEs) including multi-FBlk MOC entries (MF-MEs) for holding MOPs decoded from instructions of multiple FBlks. The PRU detects a hit of a current FBSA on an MF-ME; performs a set of actions K times: looking up the current FBSA in the FBP and branch predictors to obtain outputs, using the outputs to predict a successor FBSA of a successor FBlk; and making the current FBSA the successor FBSA; and predicts that an FBSA of a successor FBlk to the MF-ME is the current FBSA resulting from performing K times the set of actions. K is a number of FBlks built into the MF-ME (alternatively times a loop unroll factor).