The object is to develop an
integrated circuit arrangement (100) with at least one application circuit (40) to be tested. In addition, with at least one self-test circuit (10, 20, 32, 34, 36, 50) provided for testing the application circuit (40) and generating at least one pseudo-random
test sample, wherein the said pseudo-random
test sample can be converted into at least one
test vector that is programmable and / or deterministic. Moreover, that can be supplied to the application circuit (40) for testing purposes via at least one
logic gate (32, 34, 36). And by means of at least one
signal that can be applied to said
logic gate (32, 34, 36), and wherein the output
signal arising in dependence on the deterministic
test vector can be evaluated by the application circuit (40) by means of at least one signature register (50). As well as a method of testing the application circuit (40) present in the
integrated circuit arrangement (100) by means of the self-test circuit (10, 20, 32, 34, 36, 50) further such that the BIST [build in
self test] hardware connected to the additional deterministic logic can be reduced. It is suggested that the
signal to be supplied to the
logic gate (32, 34, 36) can be made available by a BFF [bit flipping function] logic circuit (10) based on at least one.