37 results about "Pseudo random testing" patented technology

A test case generator including a test model generator for generating test models. A test case instance generator uses a permutation engine to generate test matrices from the tests models and generates XML documents from the test matrices. The documents are applied to an XML-based application interface to test the interface.

A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

An electronic system with a self-test function has a pseudo-random test pattern generator that serially generates data constituting a pseudo-random test pattern, and stores a 1-bit shifted pseudo-random test pattern obtained by shifting the pseudo-random test pattern by one bit. When a scan-path circuit supplies the pseudo-random test pattern to a tested circuit which carries out an operation based on the pseudo-random test pattern, and then loads an operation result of the tested circuit, the 1-bit shifted pseudo-random test pattern is supplied to the tested circuit as the next pseudo-random test pattern. This makes it possible to solve a problem of a conventional electronic system in that it takes a long time to evaluate the operation results of the tested circuit because it takes at least (1+n)xm clock cycles, where m is the number of pseudo-random test patterns supplied to the tested circuit and n is the number of stages of the scan-path circuit.

The invention provides a software simulation verification method based on a Cache coherence protocol. According to the method, pseudo random test which is capable of compiling constraint models and also carrying out band constraint in a manual mode is subject to software simulation and verification; specific objects are verified, and the accuracy and defect of the protocols are fed back. The method based on software simulation comprises the following steps of: firstly determining a multi-stage coherence description mode based on an expanded Cache Coherence protocol; and subsequently realizing the software simulation verification method, counting the coverage rate and carrying out error report. With the adoption of the method, the Cache Coherence protocol in multi-stage domains in a multi-state space can be verified effectively so as to enable a protocol table to realize the establishment of corresponding logic relationship, judge whether the state transition of a system in accordance with the protocol table accords with the coherence definition through an overall checker, and primarily judge whether a mode established in accordance with the protocol table has expected properties. The model system has the remarkable advantages that counter-examples can be generated automatically so as to assist in debugging errors of the system and accelerating system diagnosis and debugging.

A method is described of calibrating a write pre-equalization circuit in the write channel of a magnetic data storage device which maximizes the rate at which the write channel can write to a data storage medium. The method includes the steps of: setting an amplitude of a delayed current to a minimum value ; setting a delay period of the delayed current to a minimum value; setting an amplitude of a main driver current to a minimum value; recording a low frequency test signal to the data storage medium; reading the low frequency test signal from the data storage medium; monitoring a quality metric of the low frequency test signal; varying the amplitude of the main driver current over a range of amplitudes; selecting an optimum amplitude of the main driver current; setting the delay period of the delayed signal to a predetermined value; recording a pseudo-random test signal to the data storage medium; reading the pseudo-random test signal from the data storage medium; monitoring a quality metric of the read pseudo-random test signal; varying the amplitude of the delayed current over a range of amplitudes; and selecting an optimum value of the delayed current, depending on the monitored quality metric.

The invention relates to a dynamic error testing method and device for an intelligent ammeter. The device consists of a synchronous circuit with a three-phase voltage and/or a three-phase current, a synchronous pseudo random sequence control signal generating circuit, a pseudo random sequence selecting circuit, an ammeter dynamic load power control circuit, an ammeter dynamic error testing unit, a display and keyboard unit and a dynamic error measuring algorithm. The method and device can effectively generate multi-modal pseudo random testing excitation current and power and effectively reflect randomness of change of the dynamic load current and the power, thereby tracing the source from dynamic load electric energy value to a dynamic load electric energy value of the pseudo random change and fully testing the dynamic error characteristic of the ammeter under multi-modal testing excitation; the method and device solve the problem that exiting determined testing excitation current and power cannot reflect randomness of the dynamic load change and solve the problem of tracing the source of the dynamic load electric energy value and testing the dynamic error under dynamic load of the pseudo random change; the method and device can be widely used in a dynamic error testing system of the intelligent ammeter.

Identical random, or pseudorandom, test patterns in a peripheral device (“receiver”) to be tested, and in a transmitter that sends the test pattern to the receiver, are generated by using pattern generation circuitry in both the transmitter and the receiver that operates identically based on a pattern input value, or seed. The same seed is input to both the transmitter and the receiver. The pattern generation circuitry can be a linear-feedback shift register (“LFSR”), which generates pseudorandom numbers, and identical LFSRs in both the transmitter and the receiver are provided with the same seed. The LFSR may be reseeded periodically. The new seed can be an output of the LFSR itself, or a second LFSR is provided whose output is used to determine the new seed for the first LFSR. Alternatively, cryptographic modules are used in the transmitter and the receiver to generate the test pattern based on identical keys.

A method and system for pseudo-random testing a fault tolerant network for determining the network's response to failure includes generating an image of the network on a host. At least one path of the network is selected to be physically failed through the use of a random number generator such that the selection is done pseudo-randomly. The part is then failed and the network's response to the failure is detected and all attempts to repair the failure logged up to and including the first successful attempt to repair the failure. In the event of a failure to repair a path occurs, the test is stopped, a repair effected, and the test restarted at the point the failure to repair occurred.

The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output.

The present invention provides a low-power consumption weighted pseudo-random test method, a low-power consumption weighted pseudo-random test system, a low-power consumption weighted pseudo-random test device and a storage medium. The test method includes the following steps that: a scan forest is established; all scan chains controlled by the same multi-output selector are all set in be the same scan chain subset; weight assignment is performed on test enable signals in each scan chain subset according to a testability gain function; the scan forest is adopted to perform a pseudo-random test, and a pseudo-random test vector is outputted; and a pseudo-random test result is calculated according to the pseudo random test vector. The fault coverage rate of the test method and test system is high and is 20% higher than the fault coverage rate of a traditional method; the low hardware overhead of the test method and test system is low, no additional delay overhead being brought about; the structure of the test method and test system is simple, so that the test method and test system can be widely applied to the industrial community, can be easily embedded into an existing EDA tool, and can support pseudo-random testing and deterministic self-testing; and combined with the deterministic self-testing, the test method and test system can effectively reduce test data capacity.

A logic built-in self-test reset circuit test system comprises a test vector generator, a logic built-in self-test controller and a test response analyzer, the test vector generator generates a reset test vector and a pseudo-random test vector, receives an instruction of the logic built-in self-test controller, and analyzes the reset test vector and the pseudo-random test vector according to the instruction of the logic built-in self-test controller. The reset signal, the clock signal, the scanning enable signal and the scanning vector output signal are output to a circuit to be tested; the logic built-in self-test controller is used for respectively controlling the signal output of the test vector generator and controlling the test response analyzer to test the circuit to be tested; and the test response analyzer receives an instruction of the logic built-in self-test controller and tests the circuit to be tested. The invention also provides a reset circuit test method for logic built-in self-test, which solves the problem that the reset signal cannot be highly covered in the traditional logic built-in self-test by using less logic, and improves the fault coverage rate.

A method for testing an electronic circuit includes selecting an input signal using a first multiplexer, selecting a signal to be input to the first multiplexer using at least one other multiplexer, and controlling the at least one other multiplexer using a selection signal output from a control circuit.

The invention discloses a nuclear power plant field bus communication error rate test device and test method. The nuclear power plant field bus communication error rate test device comprises an errorrate detection unit, a terminal resistance configuration unit and a communication parameter input/output unit, wherein the bit error rate detection unit is realized based on a programmable logic device, and is used for generating a pseudo-random test signal and transmitting the pseudo-random test signal to a link of a to-be-tested field bus so as to test a bit error rate of the link of the to-be-tested field bus; the terminal resistance configuration unit is used for realizing electrical isolation between the bit error rate detection unit and the to-be-tested bus, and adjusting a terminal resistance value matched with the link of the to-be-tested field bus according to test parameters; and the communication parameter input/output unit is used for realizing environmental parameter input ofthe to-be-tested field bus and outputting a communication parameter result obtained by testing to an upper computer. According to the nuclear power plant field bus communication error rate test device, the communication function and the transmission signal error rate of the link of the field bus can be comprehensively and systematically tested.