4 results about "Test pattern generators" patented technology

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

The present invention relates to a computer implemented decoding method that includes decoding a number of run-length encoded mask strings to obtain decoded mask bits for each of a number of scan channels. The method also includes applying the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature. Additionally the present invention also relates to an apparatus configured to carry out the method. The apparatus being implemented either with at least one memory and at least one processor or with a plurality of finite state machines and a plurality of logical AND gates.

A system and a method of pattern selection are provided for use by an electronic design automation (EDA) automatic test pattern generator (ATPG) for improved intermediate resistance (IR) drop analysis. The method includes identifying, for each of a plurality of transitional delay fault (TDF) patterns, flip-flops (FFs) toggling during a capture window; identifying coordinates on a grid for each of the toggled FFs; generating a boundary around the toggled FFs; generating tiles within the boundary; determining a number of toggled FFs included within each of the tiles; and ranking the plurality of TDF patterns based on the number of toggled FFs included within each of the tiles of each of the plurality of TDF patterns.

The invention relates to a condition test layout generator construction method, belongs to the technical field of test layouts, and solves the problem that a test layout generation method in the prior art cannot generate a test layout with specified layout attributes. Comprising the steps of obtaining a set number of original layouts, and adding attribute tags to the original layouts to obtain a first sample data set; processing each first sample data set to obtain a second sample data set of each resolution; constructing a label embedding network, and training the label embedding network based on the feature extraction network, the feature regression network and the first sample data set to obtain a trained label embedding network; a conditional generative adversarial network is constructed, the conditional generative adversarial network comprises a conditional generative network and a discriminant network, and the conditional generative network comprises a trained label embedding network and a generative network; and training the conditional generative adversarial network, and taking the trained conditional generative network as a conditional test layout generator.