9 results about "Test pattern generators" patented technology

Techniques for secure built in self test are described. Some examples include a secure test pattern generator to generate a secure test pattern using a pseudo-random function (PRF) circuitry; a scan out hash engine to hash a scan out of a circuit to be tested; and a comparison circuit to compare the hashed scan out to a known value to verify the hash.

The invention relates to a resource board card and a test machine, and the resource board card comprises a test pattern memory which is used for storing test pattern information with different functions; the test pattern generator generates pattern data according to the test pattern information of the current target function, sends the pattern data to the time sequence module, calls the test pattern information of the read operation in the test pattern memory, generates pattern data based on the test pattern information of the read operation, and sends the pattern data to the time sequence module; receiving comparison result data obtained by processing a feedback signal for executing the read operation on the to-be-tested device by the time sequence module; the test pattern generator also reads test pattern information of a next target function from the test pattern memory after determining that the to-be-tested device completes an operation corresponding to the current target function according to the comparison result data, and the test pattern information serves as new test pattern information of the current target function to generate pattern data to be sent to the time sequence module; the waiting time can be reduced, and the test efficiency is improved.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

The present invention relates to a computer implemented decoding method that includes decoding a number of run-length encoded mask strings to obtain decoded mask bits for each of a number of scan channels. The method also includes applying the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature. Additionally the present invention also relates to an apparatus configured to carry out the method. The apparatus being implemented either with at least one memory and at least one processor or with a plurality of finite state machines and a plurality of logical AND gates.

A test device and a testing method for a memory are provided. The test device includes a selection signal generator and a plurality of test pattern generators. The selection signal generator receives a test signal via a signal input end and detects a voltage variation on the test signal to generate a test mode selection signal. The test pattern generators are coupled between the selection signal generator and a row decoder of the memory device. The test pattern generators receive the test mode selection signal, and one of the test pattern generators is activated according to the test mode selection signal to perform a test operation on at least one of a plurality of memory cell rows in the memory device.

A system and a method of pattern selection are provided for use by an electronic design automation (EDA) automatic test pattern generator (ATPG) for improved intermediate resistance (IR) drop analysis. The method includes identifying, for each of a plurality of transitional delay fault (TDF) patterns, flip-flops (FFs) toggling during a capture window; identifying coordinates on a grid for each of the toggled FFs; generating a boundary around the toggled FFs; generating tiles within the boundary; determining a number of toggled FFs included within each of the tiles; and ranking the plurality of TDF patterns based on the number of toggled FFs included within each of the tiles of each of the plurality of TDF patterns.

A test device and a testing method for a memory are provided. The test device includes a selection signal generator and a plurality of test pattern generators. The selection signal generator receives a test signal via a signal input end and detects a voltage variation on the test signal to generate a test mode selection signal. The test pattern generators are coupled between the selection signal generator and a row decoder of the memory device. The test pattern generators receive the test mode selection signal, and one of the test pattern generators is activated according to the test mode selection signal to perform a test operation on at least one of a plurality of memory cell rows in the memory device.

The invention relates to a condition test layout generator construction method, belongs to the technical field of test layouts, and solves the problem that a test layout generation method in the prior art cannot generate a test layout with specified layout attributes. Comprising the steps of obtaining a set number of original layouts, and adding attribute tags to the original layouts to obtain a first sample data set; processing each first sample data set to obtain a second sample data set of each resolution; constructing a label embedding network, and training the label embedding network based on the feature extraction network, the feature regression network and the first sample data set to obtain a trained label embedding network; a conditional generative adversarial network is constructed, the conditional generative adversarial network comprises a conditional generative network and a discriminant network, and the conditional generative network comprises a trained label embedding network and a generative network; and training the conditional generative adversarial network, and taking the trained conditional generative network as a conditional test layout generator.