232 results about "Functional verification" patented technology

The invention discloses a conversion method and system based on SysML and Modelica model semantic mapping. The method comprises the following steps that S1, a Modelica standard model library is imported into a SysML modeling tool; s2, completing the definition of behavior elements, and forming an SysML model instance; s3, exporting a Modelica model which can be executed by the Modelica simulator; s4, establishing a mapping relation table between SysML model elements and Modelica model elements; s5, when a change event occurs in the SysML model, updating the content of the corresponding Modelica model; s6, the Modelica model is imported into the SysML model, and a corresponding SysML model instance is generated; s7, simulation result mapping and behavior modeling generation are executed, a state transition diagram structure is formed, and structure updating of internal block diagrams in the system model is completed. According to the method, bidirectional conversion and joint simulation optimization between models are realized, and the method is suitable for cross-platform modeling, collaborative design and functional verification scenes of a complex system.

The invention discloses an operation and maintenance knowledge intelligent question and answer interaction method, device and equipment based on an LLM large model. According to the method, questions of operation and maintenance personnel are received through a natural language interaction interface, semantics are analyzed through a pre-trained LLM, candidate answers are generated, the accuracy of the answers is verified in combination with a dynamic operation and maintenance knowledge graph (including equipment model and fault code mapping, a historical case library and a real-time updating knowledge base), and finally a verification result is returned. The device comprises an input module, a processing module, a verification module and an output module, the processing module integrates domain knowledge fine tuning and real-time data integration functions, and the verification module supports multi-source data fusion and confidence evaluation. The platform adopts a multi-tenant architecture, supports visual diagnosis, automatic equipment operation and knowledge use report generation, and ensures that data cannot be tampered through a block chain technology.

The invention discloses an off-line function verification system for an intelligent electric actuating mechanism, and the system comprises an off-line function verification unit which achieves the data interaction through the connection with a system signal terminal unit of the intelligent electric actuating mechanism, so as to achieve the off-line function verification function of the intelligent electric actuating mechanism. The offline function verification unit is an integrated module and comprises a man-machine interaction module, a host control module, an interface module, an instruction control module, a control power supply control module and a power supply control module; the problems that a large amount of manpower and time are consumed, the test process is tedious, the work efficiency of the original test process is low, human errors and test record detection errors are prone to occurring, data analysis depends on manpower, and the error risk is increased due to the fact that a traditional test method at the present stage consumes operations such as frequently changing used tools and modifying wiring in the test process are solved.

The invention relates to the field of industrial automation testing, discloses a multifunctional testing tool and method for an EUROMAP interface of an injection molding machine, and achieves the crossing from single function verification to system-level compliance evaluation. A test network is constructed through a controller, and deep compliance verification, coverage data interaction, exception handling and cross-layer response consistency are realized. The test tool integrates the functions of protocol analysis, signal simulation, fault injection and the like, supports dynamic generation of boundary value test scenes and abnormal injection of signal delay, CRC errors and the like, and verifies the time sequence / logic consistency of a protocol instruction and an execution mechanism response through a hardware-level timestamp alignment technology. According to the method, an evaluation report including compliance rating, fault diagnosis and optimization suggestions is automatically generated, the problems of single coverage dimension, insufficient abnormal simulation, cross-layer verification deficiency and the like of a traditional test are solved, the intelligence and standardization level of the injection molding machine interface test is remarkably improved, and the equipment interconnection and intercommunication performance is guaranteed.

The invention relates to the technical field of function verification, in particular to a processor loading storage unit function verification method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out formalized verification on a processor loading storage unit through a formalized verification tool, and extracting feature data which does not cover a critical path; wherein the feature data at least comprises a time sequence feature, an address feature and a data dependence feature; converting the feature data into constraint rules available for the dynamic simulation platform, and generating test excitation; and executing dynamic simulation verification based on the test excitation to obtain a coverage rate result. According to the processor loading storage unit function verification method provided by the invention, through formalized verification and dynamic simulation closed-loop cooperation, the directional constraint is generated by extracting the key path features, the verification period is greatly shortened, and the coverage rate convergence efficiency is improved.

The embodiment of the invention discloses a processor front-end branch prediction and instruction fetching verification method and device and a storage medium, relates to the technical field of processor function verification, and can reduce the complexity of instruction scene construction and improve the verification efficiency. The method comprises the following steps: acquiring instruction fetching information and a test vector; the fetch information comprises a fetch address range and branch prediction information of the target instruction block, and jump instruction marking information is configured in the test vector; according to the fetch address range and the jump instruction mark information, generating an instruction boundary of each cache line in the fetch address range; respectively associating the branch prediction information and the jump instruction mark information to the instruction boundary of each cache line, and constructing to obtain an instruction stream; the instruction stream is used for simulating execution logic of processor front-end branch prediction and instruction fetching; and decoding simulation verification is carried out based on the instruction stream, and processor front-end branch prediction and instruction fetching accuracy is determined. The method is suitable for a verification scene of processor front-end branch prediction and instruction fetching.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention relates to the technical field of chip development, and discloses a transplanting method and device of a swan gap system, a storage medium and computer equipment, and the method comprises the steps: constructing a swan gap system to be transplanted based on a target chip, obtaining a corresponding source code, and then configuring a compiling configuration file in the source code, the compiling subsystem is used for establishing a compiling environment based on configuration information in the compiling configuration file, performing transplantation adaptation on a kernel layer in the compiling environment to generate a kernel mirror image, configuring the starting recovery subsystem, generating a root file system mirror image based on the file system configuration file, and starting the starting recovery subsystem. And finally burning the kernel mirror image and the root file system mirror image to a target chip, and performing function verification and test on the target chip. According to the method disclosed by the present invention, the swan-gap system transplantation including kernel layer transplantation, subsystem adaptation and root file system customization is designed and realized, so that the swan-gap system is successfully adapted to the target chip, and the accelerator equipment carrying the target chip can stably and reliably operate.

The invention discloses a verification method of an integrated circuit, electronic equipment, a program product and a storage medium, and is applied to the technical field of integrated circuits, and the verification method comprises the following steps: obtaining a time sequence description file used for reflecting a time sequence of a hardware interface protocol of the integrated circuit; analyzing the time sequence description file to generate a structured rule corresponding to the time sequence description file; converting the structured rule into an executable assertion; and integrating the executable assertion into a verification environment, and performing function verification on the integrated circuit by using the verification environment to obtain a verification result of the integrated circuit. By applying the scheme of the invention, end-to-end automatic generation from the time sequence description file to the verification environment is realized, manual coding requirements of workers are not needed, the development cycle is greatly shortened, the efficiency is improved, manual coding of the workers is not needed, and thus human errors can be effectively avoided.

The invention relates to the field of function verification of digital integrated circuits, and discloses an atomic-scale computing chip verification method based on a UVM. The method comprises the following steps: firstly, building a UVM simulation verification platform comprising each core component; then, a software program is used for generating test excitation with physical significance, wherein the test excitation comprises information such as configuration, functional, pseudo potential and track files; then respectively inputting the test excitation into the established UVM verification platform and the software reference model; the UVM verification platform applies the test excitation to the to-be-tested design and outputs a calculation result; the reference model also correspondingly generates a reference result; and finally, comparing the output of the to-be-tested design with the output of the reference model, and verifying the correctness of the function of the atomic calculation chip through visual auxiliary analysis and quantitative error analysis. Through excitation generation based on physical constraints and an effective error evaluation method, the function verification problem of the atomic-scale computing chip can be solved.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention relates to a verification and repair method and device for creative database migration, and after target data of a source database is migrated to a creative database, the creative database is subjected to the following steps: data migration test, function verification test, performance evaluation test, security test, compatibility test and automatic repair. The stability and performance of the credential database in different scenes are verified by simulating different environments and configurations; the test efficiency and accuracy are improved; and the problem can be solved in time through an automatic repair means, and the risk in the replacement process is reduced.

The invention discloses an automatic driving test and evaluation method and device based on a large language model, and solves the problems that the pertinence of a test scene is insufficient, the result understanding depends on manpower, the evaluation interpretation is weak and the like in a traditional method. By means of semantic analysis, logical reasoning and domain knowledge support of a large language model and in combination with an automatic driving test domain knowledge graph, generation of a structured test portrait of a tested system, construction of a test demand list, generation of a semantic test scene description file, interpretable test result attribution, multi-dimensional comprehensive evaluation and report output are completed in sequence. And a test portrait is updated through report feedback to form a closed loop. The method is suitable for function verification and performance evaluation of an automatic driving simulation test, can also be used for post-processing analysis of real vehicle test data, realizes automation of a whole test process and interpretability of an evaluation result, and improves test precision and efficiency.

The embodiment of the invention provides a code generation method and device, equipment and a medium. The method comprises the steps of obtaining a hardware design file corresponding to a to-be-verified function module of a target chip; extracting interface information corresponding to an input interface and an output interface of the to-be-verified module from the hardware design document; based on the function verification code template, the interface information of the reference module and the interface information of the to-be-verified function module, verification codes for the to-be-verified function module are generated, and the reference module and the to-be-verified module have the same function. The verification code is used for controlling the input interfaces of the to-be-verified function module and the reference module to input the same excitation so as to verify whether the function of the to-be-verified function module is normal or not based on the output results of the output interfaces of the to-be-verified function module and the reference module. By adopting the method, the program code for verifying the function of the to-be-verified function module can be automatically generated, so that the verification efficiency of the target chip is improved.

The invention belongs to the technical field of intelligent terminal mainboard testing, and discloses an intelligent terminal mainboard function verification system based on multi-protocol compatibility. Comprising a data acquisition module used for performing benchmark testing on each communication protocol supported by the intelligent terminal mainboard to obtain a benchmark data set of the intelligent terminal mainboard; the analysis and sequence generation module is used for acquiring a resource consumption portrait of the intelligent terminal mainboard; generating a concurrent test instruction sequence based on a pre-constructed test sequence generation engine; the concurrent test and diagnosis module is used for acquiring a concurrent test operation log by executing the concurrent test instruction sequence; identifying a causal relationship between a protocol performance degradation event and a resource state abnormal event based on the concurrent test operation log, and forming a resource protocol conflict event record; and the diagnosis and report generation module is used for acquiring diagnosis results of the resource protocol conflict events and further analyzing and generating a comprehensive verification report, so that a clear decision basis is provided.

The invention provides a chip verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: synchronously operating a to-be-verified chip design and a chip verification model to execute a preset cache line processing method; respectively acquiring a first output signal and first additional information of the to-be-verified chip design, and a second output signal and second additional information of the chip verification model; the first additional information is used for representing intermediate state information of a cache line in the design of the to-be-verified chip; the second additional information is used for representing intermediate state information of a cache line in the chip verification model; and determining a function verification result of the to-be-verified chip design. According to the method and the device provided by the invention, the output signal and the additional information are compared, so that the design defect can be found in time in the early stage of deviation of the internal logic state of the chip, the verification completeness and accuracy are greatly improved, and the overall verification efficiency is improved.

The invention relates to the technical field of chips, and provides an interrupt module verification method and device, a medium and a program product, the method comprises the following steps: when it is monitored that an interrupt module generates an external observable behavior, comparing monitored behavior information with a reference value of the external observable behavior, and verifying the correctness of the external observable behavior; performing state calculation on the interrupt request input to the interrupt module, and determining an internal processing state of the interrupt request; an internal register state of the interrupt module is verified based on an internal processing state of the interrupt request. According to the invention, through a mode of combining black box verification of external observable behaviors with white box verification based on an internal processing state, comprehensive, deep and efficient function verification of a complex interrupt module is realized.

In some aspects, a logic design undergoes functional verification, which includes generating a test stimulus to apply to the logic design. The test stimulus includes test values for variables representing signals in the logic design. Generating the test stimulus involves a first problem of solving for the test values of the variables subject to constraints on the test values. It is solved as follows. A specification of the logic design is accessed. An array implication graph is generated from the specification. The array implication graph represents the problem as a set of two or more single-array constraint problems. Each single-array constraint problem solves for the test values of a single array of the variables subject to the constraints within that single array. The array implication graph also represents dependencies between different single-array constraint problems. The problem is solved based on the dependencies represented in the array implication graph.

According to the technical scheme, the large-scale logic optimization multiplier verification method is characterized in that a four-stage pipeline processing mode is adopted, the first stage is a partial adder tree recovery stage, and the second stage is a partial adder tree recovery stage; the second stage is an architecture generation stage; the third stage is a function verification stage; and the fourth stage is an equivalence checking stage. The verification capability is improved in a breakthrough manner and is far better than that of an existing method; the innovative three-stage decomposition strategy significantly reduces the calculation complexity, the ILP algorithm optimizes resource allocation, the multi-stage scheduling balances the calculation load, and the QACO algorithm efficiently explores the design space, so that the RefSCAT-2.0 framework provided by the invention becomes the most effective solution for verifying a large-scale logic optimization multiplier at present. From the perspective of practice, the technical blank of large-scale logic optimization multiplier verification is filled up, and important tool support is provided for reliability guarantee of key computing systems such as artificial intelligence chips, high-performance CPUs and GPUs.

The invention discloses a progressive event-driven synchronous control method, which comprises the following steps of: performing parallel simulation, simultaneously starting a plurality of simulation processes, respectively simulating each core particle in a multi-core particle system, and managing the synchronization among the simulation processes by a global manager; on-demand synchronization: when the core particles simulated by the simulation process are in inter-core-particle communication, the global manager synchronizes the related processes; the process is synchronized, and the global manager ensures that other cross-process communication events earlier than the request are simulated; if a simulation process does not reach the time point, the process initiating the request is suspended by the global manager until the request can be executed; and network simulation and time sequence simulation: when the request can be executed, the global manager starts the inter-chip network simulator and simulates the communication event. According to the method, the accuracy and the operation efficiency of multi-core particle parallel simulation are remarkably improved, and the method is suitable for function verification and performance analysis of large-scale complex multi-core chips.

The embodiment of the invention provides a function coverage rate model generation method, a function verification method and a related device.The method comprises the steps that register description information is obtained, and the register description information comprises verification function coverage rate description information of various types, the type of the verification function coverage description information is matched with a verification scene of the register during function verification; according to the register description information, a function coverage rate model of the register is generated, and the function coverage rate model comprises a constrainable function coverage rate model corresponding to the type of the verification function coverage rate description information. According to the technical scheme provided by the embodiment of the invention, the register function verification efficiency can be improved.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

An example is a non-transitory computer-readable storage medium including stored instructions. The instructions, which when executed by one or more processors, cause the one or more processors to: obtain an assignment of an assigned bucket; generate stimulus values targeting one or more uncovered bins of the assigned bucket; simulate operation of a circuit design using the stimulus values; determine whether the assigned bucket has been covered by the simulated operation of the circuit design; and expand a size of the assigned bucket following a determination that the assigned bucket has been covered. The assigned bucket, as assigned, has a subset of bins of a functional coverage space.

The invention discloses an RoCEv2 protocol RC service type basic primitive function verification system based on a UVM. The system comprises a test case class used for configuring verification parameters, initializing a verification environment and driving a primitive execution process; the verification environment is used for packaging a plurality of agent components, a reference model, a register model and a scoreboard and carrying out data interaction through a TLM interface; the agent components are used for driving or monitoring an interface designed to be tested, comprise but are not limited to a register read-write agent, a work queue element WQE reading agent, a load data reading and receiving agent, a data packet sending and receiving agent, a complete queue element CQE receiving agent and a register model component, and are constructed based on a register abstraction layer RAL modeling method; and front-door and back-door access paths are supported. The method is high in automation degree, integrates constraint randomization, comparison verification and coverage rate analysis, and realizes full automation of the verification process.

The invention discloses an SRAM (Static Random Access Memory) verification method, system and equipment, relates to the technical field of integrated circuits, and is used for solving the problems of low code reuse rate, long verification period and difficulty in defect positioning in the existing SRAM verification method. The method comprises the following steps: setting a unified virtual shell program module for a to-be-verified SRAM memory module, and packaging key attribute information of the to-be-verified SRAM memory module through macro definition parameters; distributing a serial number for the SRAM type of each SRAM memory module to be verified, and establishing a mapping relation between the serial number and the interface module; calling a corresponding excitation signal from an excitation signal library according to the serial number, and determining a corresponding target interface module through a mapping relation; and connecting a virtual shell program module of the SRAM module to be verified through the target interface module, sending an excitation signal, and triggering function verification. According to the technical scheme provided by the invention, high efficiency, compatibility and expansibility of verification can be realized, and the accuracy of a verification result is improved.

The invention provides a system-level design generation method and system based on AI-Agent. The method provided by the invention comprises the following steps: receiving design demand information input by a user; carrying out system-level architecture design and system segmentation on the design demand information based on the AI-Agent, generating a system architecture scheme, design prompt information and a constraint file, and carrying out feasibility verification on the system architecture scheme by generating a rule checking mechanism to obtain the system architecture scheme, the design prompt information and the constraint file which pass verification; matching a corresponding path generation method based on the design prompt information passing verification or a Python algorithm code input by a user, and generating a hardware description language code based on the path generation method; and performing function verification on the hardware description language code, connecting the hardware description language code passing the function verification and the constraint file passing the verification with a back-end tool, performing layout wiring, and outputting a GDS-II layout file.

1. The name of this design product: Tandem twin-rotor UAV. 2. Purpose of this design product: This design product is used for flight control system design, debugging and functional verification, etc. 3. The key point of the design of this product lies in its shape. 4. The picture or photo that best illustrates the design points: three-dimensional picture.

The application relates to the technical field of chip verification, and discloses an FPGA chip DSP module bit stream verification method and device. In the method, a bit stream file generation method is used to convert configurable parameters of a DSP module from abstract test intentions into specific physical configuration files, the low efficiency of configuring bit stream files for the functions of each DSP module is avoided, then a two-stage routing analysis method is used for function verification of the DSP module, a complete signal path mapping between an SWH port and core logic of the DSP module is accurately constructed, the correctness of the functions of the DSP module itself is ensured, and the interconnection correctness of the DSP module and adjacent modules is ensured, then an initial verification platform is reconstructed based on a port mapping table, and a high-abstraction-level behavior model is combined for result comparison, the verification efficiency and reliability of the DSP module are greatly improved, and the efficiency and accuracy of bit stream verification of the FPGA chip DSP module are ensured.

The application discloses a FLASH application verification system based on FPGA, which comprises a PC, an FPGA application verification board and a FLASH subboard. The FPGA application verification board is provided with two FPGA chips; each FPGA chip is connected with the FLASH and can independently access the FLASH to perform verification operation; each FPGA is externally connected with a large-capacity 160Mb SRAM; and the NOR_FLASH and the SPI_FLASH can be verified by replacing the FLASH subboard. The application also discloses a verification method based on the system, which comprises the following steps: determining power-on sequence, JTAG function verification, digital logic verification and read-write function verification. The application has comprehensive verification function, strong universality and important significance for application verification of a series of FLASH.

The embodiment of the application discloses a hardware accelerator whole system performance evaluation method and device facing high-level synthesis, which comprises the following steps: constructing a cycle-accurate and event-driven hardware accelerator simulation model based on the intermediate representation and static timing report generated by HLS; executing the hardware accelerator simulation model in the whole system simulator through the accelerator simulation object, so as to convert the timing and operation defined by the hardware accelerator simulation model into simulation events in the event queue of the whole system simulator and schedule and execute; collecting cycle-accurate simulation statistical data generated in the running process of the hardware accelerator simulation model in response to the scheduling and execution of the simulation events; and generating a performance evaluation report and a function verification result of the hardware accelerator based on the simulation statistical data and the function execution result of the hardware accelerator simulation model. The embodiment of the application can efficiently and accurately evaluate the performance of the hardware accelerator generated by HLS, so as to realize true hardware-software co-design and optimization.