344 results about "Functional verification" patented technology

The invention discloses a conversion method and system based on SysML and Modelica model semantic mapping. The method comprises the following steps that S1, a Modelica standard model library is imported into a SysML modeling tool; s2, completing the definition of behavior elements, and forming an SysML model instance; s3, exporting a Modelica model which can be executed by the Modelica simulator; s4, establishing a mapping relation table between SysML model elements and Modelica model elements; s5, when a change event occurs in the SysML model, updating the content of the corresponding Modelica model; s6, the Modelica model is imported into the SysML model, and a corresponding SysML model instance is generated; s7, simulation result mapping and behavior modeling generation are executed, a state transition diagram structure is formed, and structure updating of internal block diagrams in the system model is completed. According to the method, bidirectional conversion and joint simulation optimization between models are realized, and the method is suitable for cross-platform modeling, collaborative design and functional verification scenes of a complex system.

The embodiment of the invention discloses a verification platform, method and system for verifying an I2C protocol based on a UVM environment, and relates to the field of function verification. The UVM environment has comprehensive parameterization configuration capability, various test scenes are dynamically matched, and all-directional coverage and deep insight of verification are ensured. And an intelligent mode switching mechanism is adopted, and the role change of the DUT is seamlessly jointed, so that the automation and efficiency of the verification process are improved. And a randomized test strategy is introduced, so that the randomness and robustness of verification are remarkably enhanced, and potential problems are effectively revealed. As standard I2C device simulation, time sequence verification is independently executed in an environment, communication abnormity is accurately captured and analyzed, and fault positioning is accelerated. Through the fusion application of the SystemVerilog and the UVM, the verification complexity is simplified, the simulation process is optimized, and the iteration period is shortened.

The invention discloses an operation and maintenance knowledge intelligent question and answer interaction method, device and equipment based on an LLM large model. According to the method, questions of operation and maintenance personnel are received through a natural language interaction interface, semantics are analyzed through a pre-trained LLM, candidate answers are generated, the accuracy of the answers is verified in combination with a dynamic operation and maintenance knowledge graph (including equipment model and fault code mapping, a historical case library and a real-time updating knowledge base), and finally a verification result is returned. The device comprises an input module, a processing module, a verification module and an output module, the processing module integrates domain knowledge fine tuning and real-time data integration functions, and the verification module supports multi-source data fusion and confidence evaluation. The platform adopts a multi-tenant architecture, supports visual diagnosis, automatic equipment operation and knowledge use report generation, and ensures that data cannot be tampered through a block chain technology.

The invention discloses an NB-IOT technology-based firmware remote upgrading method and an electric energy meter. The upgrading method mainly comprises the following steps of S1, an upgrading preparation stage, wherein the upgrading preparation stage comprises server end preparation and electric energy meter end preparation; s2, a data transmission stage: firmware data transmission, a breakpoint resume mechanism and fragment verification are included; s3, a firmware updating stage which comprises data analysis and storage, preparation before updating and firmware writing and starting; s4, upgrading verification and feedback, including function verification and feedback information sending; and S5, security measures including identity authentication, data encryption and digital signature. An NB-IOT module is arranged in the electric energy meter, and data transmission between the electric energy meter and the server is achieved through the NB-IOT communication technology. According to the remote firmware upgrading method based on the NB-IOT technology and the electric energy meter provided by the invention, reliable remote upgrading of the firmware of the intelligent electric energy meter is realized by adopting an NB-IOT communication mode and combining a fragmented data transmission mechanism, a firmware verification mechanism, a breakpoint resume mechanism and an upgrading feedback mechanism.

The invention relates to the technical field of pre-silicon verification, and discloses a verification environment generation method and device and a function verification method and system.The method comprises the steps that a target configuration file suitable for a to-be-tested chip model is read, and the target configuration file comprises field information; the field information is at least used for representing hierarchical information and a UPF file path of a target power domain module which is currently in an enabled state in the at least one power domain module; according to the target configuration file, generating environment configuration data of a to-be-tested chip model at least comprising UPF loading information and power supply information of a target power domain module; and according to the UPF loading information, loading the UPF file under the UPF file path into a target power domain module represented by the hierarchical information, and configuring a power supply for the target power domain module based on the power supply information to generate a verification environment for the to-be-tested chip model. According to the technical scheme provided by one or more embodiments, the verification environment can be automatically generated.

The invention discloses a method for verifying a digital circuit module in an integrated circuit, which belongs to the technical field of circuit testing and comprises the following specific steps: I, analyzing functional requirements and performance indexes of the circuit module and constructing a virtual model; iI, identifying abnormity and boundary conditions in the circuit module and generating a test case; iII, performing function verification on the circuit module and evaluating module performance; iV, optimizing the current circuit configuration according to a performance evaluation result; v, carrying out randomness verification on the circuit to detect potential vulnerability and design defects; according to the method, the circuit performance can be remarkably improved, the workload of manual parameter adjustment is reduced, the design complexity and verification difficulty are reduced, the performance of a circuit module in various scenes is improved, an input area which may cause problems can be focused on under limited test resources, the comprehensiveness and verification efficiency of the verification process are improved, and the verification efficiency is improved. And the stability evaluation of the circuit is more accurate, and the verification can be continuously improved.

The invention discloses an off-line function verification system for an intelligent electric actuating mechanism, and the system comprises an off-line function verification unit which achieves the data interaction through the connection with a system signal terminal unit of the intelligent electric actuating mechanism, so as to achieve the off-line function verification function of the intelligent electric actuating mechanism. The offline function verification unit is an integrated module and comprises a man-machine interaction module, a host control module, an interface module, an instruction control module, a control power supply control module and a power supply control module; the problems that a large amount of manpower and time are consumed, the test process is tedious, the work efficiency of the original test process is low, human errors and test record detection errors are prone to occurring, data analysis depends on manpower, and the error risk is increased due to the fact that a traditional test method at the present stage consumes operations such as frequently changing used tools and modifying wiring in the test process are solved.

The invention relates to the field of industrial automation testing, discloses a multifunctional testing tool and method for an EUROMAP interface of an injection molding machine, and achieves the crossing from single function verification to system-level compliance evaluation. A test network is constructed through a controller, and deep compliance verification, coverage data interaction, exception handling and cross-layer response consistency are realized. The test tool integrates the functions of protocol analysis, signal simulation, fault injection and the like, supports dynamic generation of boundary value test scenes and abnormal injection of signal delay, CRC errors and the like, and verifies the time sequence / logic consistency of a protocol instruction and an execution mechanism response through a hardware-level timestamp alignment technology. According to the method, an evaluation report including compliance rating, fault diagnosis and optimization suggestions is automatically generated, the problems of single coverage dimension, insufficient abnormal simulation, cross-layer verification deficiency and the like of a traditional test are solved, the intelligence and standardization level of the injection molding machine interface test is remarkably improved, and the equipment interconnection and intercommunication performance is guaranteed.

The invention provides a UVM verification platform of a UCIe adaptation layer. The platform comprises an FDI assembly, the UCIe adaptation layer to be verified, an error injection delay module and an RDI assembly. The FDI component is used for constructing a first data signal from a protocol layer and sending the first data signal to the UCIe adaptation layer to be verified; the UCIe adaptation layer to be verified is used for processing the first data signal to obtain a second data signal; and the error injection delay module is used for performing error injection and delay operation on the second data signal to obtain a third data signal and sending the third data signal to the RDI component, and can perform link delay simulation and error injection scene construction on the UCIe adaptation layer to assist in performing UCIe adaptation layer function verification.

The invention relates to the technical field of function verification, in particular to a processor loading storage unit function verification method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out formalized verification on a processor loading storage unit through a formalized verification tool, and extracting feature data which does not cover a critical path; wherein the feature data at least comprises a time sequence feature, an address feature and a data dependence feature; converting the feature data into constraint rules available for the dynamic simulation platform, and generating test excitation; and executing dynamic simulation verification based on the test excitation to obtain a coverage rate result. According to the processor loading storage unit function verification method provided by the invention, through formalized verification and dynamic simulation closed-loop cooperation, the directional constraint is generated by extracting the key path features, the verification period is greatly shortened, and the coverage rate convergence efficiency is improved.

The invention relates to the technical field of table lamp production, and discloses an automatic design generation method based on a tool table lamp structure model, which allows a user to select design parameters of a table lamp through a user interface, including shape, size, color, material type and the like, and then automatically generates a three-dimensional structure model of the table lamp by using a parametric modeling method. Constructing a performance analysis model through a machine learning algorithm, and generating performance expression data of the table lamp, including environmental protection, durability and manufacturing cost analysis; optical simulation software is used for simulating the illumination effect of the table lamp, illumination index data are calculated, and meanwhile circuit simulation software is used for conducting function verification and testing on a circuit system of the table lamp; and finally, generating a detailed output file of the desk lamp design for production and manufacturing. Clear and accurate guidance is provided for production and manufacturing, and the production difficulty and cost are reduced.

The embodiment of the invention discloses a processor front-end branch prediction and instruction fetching verification method and device and a storage medium, relates to the technical field of processor function verification, and can reduce the complexity of instruction scene construction and improve the verification efficiency. The method comprises the following steps: acquiring instruction fetching information and a test vector; the fetch information comprises a fetch address range and branch prediction information of the target instruction block, and jump instruction marking information is configured in the test vector; according to the fetch address range and the jump instruction mark information, generating an instruction boundary of each cache line in the fetch address range; respectively associating the branch prediction information and the jump instruction mark information to the instruction boundary of each cache line, and constructing to obtain an instruction stream; the instruction stream is used for simulating execution logic of processor front-end branch prediction and instruction fetching; and decoding simulation verification is carried out based on the instruction stream, and processor front-end branch prediction and instruction fetching accuracy is determined. The method is suitable for a verification scene of processor front-end branch prediction and instruction fetching.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention relates to the technical field of chip development, and discloses a transplanting method and device of a swan gap system, a storage medium and computer equipment, and the method comprises the steps: constructing a swan gap system to be transplanted based on a target chip, obtaining a corresponding source code, and then configuring a compiling configuration file in the source code, the compiling subsystem is used for establishing a compiling environment based on configuration information in the compiling configuration file, performing transplantation adaptation on a kernel layer in the compiling environment to generate a kernel mirror image, configuring the starting recovery subsystem, generating a root file system mirror image based on the file system configuration file, and starting the starting recovery subsystem. And finally burning the kernel mirror image and the root file system mirror image to a target chip, and performing function verification and test on the target chip. According to the method disclosed by the present invention, the swan-gap system transplantation including kernel layer transplantation, subsystem adaptation and root file system customization is designed and realized, so that the swan-gap system is successfully adapted to the target chip, and the accelerator equipment carrying the target chip can stably and reliably operate.

The invention relates to the technical field of core board testing, in particular to a core board cross-platform function testing and verifying method which comprises the following steps: building a testing environment of a plurality of operating systems and hardware platforms through a virtualization technology or actual hardware, automatically generating a cross-platform compatible testing script based on core board function requirements, supporting multi-platform operation, and verifying the core board cross-platform function. Executing the test scripts in parallel on the platforms, recording and analyzing running logs and outputting results; functional consistency on different platforms is verified through a Hash comparison algorithm, it is ensured that the core board has the same function under the multi-platform environment, performance testing is conducted on all the platforms, performance bottlenecks are recognized, and optimization is conducted through an adjusting and optimizing tool; and finally, verifying the repairing effect through fault positioning and regression testing, and automatically generating a test report. According to the method, the efficiency of cross-platform testing of the core board, the accuracy of function verification and the effect of performance optimization are improved, and the method is suitable for core board testing and optimization scenes in a complex multi-platform environment.

The invention discloses a verification method for a second-level cache interface protocol, which belongs to the technical field of multi-core verification, and comprises the following steps of: setting verification targets, including function correctness, performance standard, compatibility and exception handling capacity; establishing a verification environment, wherein the verification environment comprises a hardware platform and a test tool; function verification, including read-write operation verification, cache line state transition verification and consistency verification; performance verification including delay testing and bandwidth testing; the compatibility verification comprises the compatibility with a first-level cache and the compatibility with a processor core; the abnormal condition verification comprises interrupt processing verification and error injection verification; and analyzing a test result. According to the verification method for the second-level cache interface protocol, the second-level cache interface protocol can be comprehensively and deeply verified, the function correctness, the performance standard reaching performance and the compatibility with other components of the second-level cache interface protocol are ensured, and a solid guarantee is provided for stable operation of a high-performance computer system.

The embodiment of the invention provides a verification method and device of a chip encryption module, electronic equipment and a storage medium. The method comprises the steps of obtaining random input data; determining a first calculation result according to the random input data and the DUT to be detected, and determining a random detection result corresponding to the random input data according to the random input data and a preset detection model; according to the random detection result and the first calculation result, determining a first verification result corresponding to the DUT to be detected, generating random input data to ensure that the verification process has wide coverage under various inputs and multiple modes, and respectively inputting the random input data into the DUT to be detected and a preset detection model to ensure that the verification process has wide coverage under various input and multiple modes. The first calculation result and the random detection result are obtained and compared, then the verification result is obtained, and the reliability and comprehensiveness of function verification are improved by using a large amount of random excitation and randomly setting register configuration of the AES.

The invention discloses a verification method of an integrated circuit, electronic equipment, a program product and a storage medium, and is applied to the technical field of integrated circuits, and the verification method comprises the following steps: obtaining a time sequence description file used for reflecting a time sequence of a hardware interface protocol of the integrated circuit; analyzing the time sequence description file to generate a structured rule corresponding to the time sequence description file; converting the structured rule into an executable assertion; and integrating the executable assertion into a verification environment, and performing function verification on the integrated circuit by using the verification environment to obtain a verification result of the integrated circuit. By applying the scheme of the invention, end-to-end automatic generation from the time sequence description file to the verification environment is realized, manual coding requirements of workers are not needed, the development cycle is greatly shortened, the efficiency is improved, manual coding of the workers is not needed, and thus human errors can be effectively avoided.

The invention provides a simulation method for message deduplication in a VRA mode and a related device, and relates to the technical field of chip verification. The method comprises the steps that whether a first serial number of a current message is larger than a second serial number or not is judged, the second serial number is the maximum serial number of a sent message in a target table item, the target table item is a table item corresponding to a target flow to which the current message belongs in a lookup table, and the table item of the lookup table further comprises a message record corresponding to the flow; the message record is used for indicating that the processing state corresponding to the serial number of the sent message is sent; if yes, calculating to obtain a difference value between the first serial number and the second serial number; according to the size of the acceptable window, the size of the sliding window and the difference value, a target processing mode of the current message is determined, the lookup table is updated, and the target processing mode indicates that the current message is discarded or sent. Therefore, simulation of message sliding window de-duplication in the VRA mode in FERE can be realized, and function verification of the to-be-tested design can be quickly carried out.

The embodiment of the invention provides a processor random verification program generation method and device, equipment and a storage medium, and the method comprises the steps: generating a target processing instruction for a target instruction which may generate an unpredictable execution result during loop execution in a loop instruction sequence; inserting the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used for processing an operand in a source register of the target instruction before the target instruction is executed in each cycle execution process, so that the target instruction generates a predictable execution result in the cycle process. Thus, the execution result of the target instruction in the loop instruction sequence can be predicted, it is not needed to avoid the instruction with the execution result unpredictable in the instruction sequence, the instruction types in the loop instruction sequence are enriched, the verification efficiency of the microprocessor is improved, and the verification efficiency of the microprocessor is improved. And the quality of the random verification program and the convergence speed of the function verification coverage rate are improved.

The invention provides a chip logic function verification method, computer equipment, a program product and a medium. The chip logic function verification method comprises the following steps: obtaining a division scheme of a back-end design for each sub-module of a chip, so that the chip is re-divided into a plurality of to-be-verified modules; obtaining an RTL design scheme corresponding to the to-be-verified module; keeping the port of the to-be-verified module unchanged, and obtaining a gate-level netlist corresponding to the RTL design scheme; physical implementation of the to-be-verified module is carried out through the gate-level netlist and an EDA tool, and a design netlist after physical implementation is obtained; according to the design netlist, obtaining the time sequence information of each to-be-verified module after the time sequence convergence and the first time delay from the port of each to-be-verified module to the target register, and respectively subtracting the first time delay from the preset time delay to mark the port of each to-be-verified module so as to perform logic function verification with the time sequence information on the to-be-verified module. According to the scheme, optimization of manpower and calculator resources in the whole design process can be achieved, and the efficiency of chip logic function verification is improved.

The invention relates to the field of function verification of digital integrated circuits, and discloses an atomic-scale computing chip verification method based on a UVM. The method comprises the following steps: firstly, building a UVM simulation verification platform comprising each core component; then, a software program is used for generating test excitation with physical significance, wherein the test excitation comprises information such as configuration, functional, pseudo potential and track files; then respectively inputting the test excitation into the established UVM verification platform and the software reference model; the UVM verification platform applies the test excitation to the to-be-tested design and outputs a calculation result; the reference model also correspondingly generates a reference result; and finally, comparing the output of the to-be-tested design with the output of the reference model, and verifying the correctness of the function of the atomic calculation chip through visual auxiliary analysis and quantitative error analysis. Through excitation generation based on physical constraints and an effective error evaluation method, the function verification problem of the atomic-scale computing chip can be solved.

The invention discloses a universal verification system, device and method suitable for the functional performance of an FPGA device, and relates to the technical field of FPGA device testing, the universal verification system comprises verification hardware, verification software, a verification auxiliary instrument and environment equipment, and the specific verification steps are as follows: step 1, on-chip logic function verification; step 2, common interface function verification; 3, software and hardware adaptability function verification; 4, comprehensive performance function verification; 5, dynamic power consumption testing; step 6, common IP function verification; 7, testing associated parameters; step 8, system adaptability; and step 9, environment adaptability. The universal verification system is suitable for verification of a serial interface function, a multi-path IO compatibility test function, development software platform adaptability, simulator adaptability, a configuration mode, configuration starting time, a signal processing function, official IP supportability and the like, and has functions of a high-speed interface protocol, an Aurora protocol, a DDR protocol, an IIC protocol, an SPI protocol and the like.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention discloses a chip functional security vulnerability detection method and system, and relates to the technical field of chip security vulnerability detection, and the method comprises the steps: collecting chip data, and carrying out the preliminary waveform analysis of the collected data; performing energy consumption feature analysis, preliminarily identifying vulnerabilities, and verifying functionality and task integrity; and carrying out vulnerability analysis, and carrying out processing decision. According to the chip functional security vulnerability detection method provided by the invention, energy consumption feature analysis and functional verification are combined, a multi-dimensional vulnerability detection method is provided, and two types of problems of side channel attacks and functional vulnerabilities can be covered. Through optimization of an orthogonal polynomial filter and an anomaly detection algorithm, the accuracy of vulnerability detection is remarkably improved; through an intelligent repair mechanism, dynamic repair and security startup enhancement of vulnerabilities are realized, and the method has better effects in the aspects of detection coverage, real-time performance and repair efficiency.

The embodiment of the invention provides a consistency verification method, system and equipment of a storage chip and a storage medium, and belongs to the technical field of memories. The method comprises the following steps: controlling a mechanical arm to respectively place a plurality of to-be-verified storage chips on a preset test fixture; loading a preset tuning test assembly to each storage chip placed on the test fixture through the first terminal equipment, issuing various different reset instructions to obtain execution results of the reset instructions, and obtaining consistency verification data according to the tuning logs and the execution results; the multiple storage chips can be sequentially fed to the test jig through the mechanical arm, and the storage chips are detachably installed on the first terminal equipment through the test jig to be tested. And meanwhile, by configuring the tuning test component, the consistency of the production process of the storage chip can be verified while function verification is performed through different reset instructions, so that the consistency verification efficiency of the storage chip is improved.

The invention provides a function verification method and device for hardware design, electronic equipment, a computer readable storage medium and a computer program product, which can be applied to the field of hardware verification, and the method comprises the following steps: building a test platform corresponding to the to-be-verified hardware design by using a meta-model; continuously sending the current excitation data packets to a test platform through a client socket; wherein the current excitation data packet is generated by performing behavior selection based on coverage rate data fed back by an emulator through an intelligent agent in an RL environment; the excitation data packet received by the test platform is utilized to continuously drive the hardware design to be tested; continuously collecting coverage rate data after the to-be-tested hardware is designed and driven by adopting a simulator, and continuously feeding back the current coverage rate data to the RL environment; and when the current coverage rate data meets the verification target condition, stopping driving the to-be-verified hardware design, and completing the function verification target. Therefore, the verification efficiency is improved, and the hardware design period is shortened.

The invention relates to a verification and repair method and device for creative database migration, and after target data of a source database is migrated to a creative database, the creative database is subjected to the following steps: data migration test, function verification test, performance evaluation test, security test, compatibility test and automatic repair. The stability and performance of the credential database in different scenes are verified by simulating different environments and configurations; the test efficiency and accuracy are improved; and the problem can be solved in time through an automatic repair means, and the risk in the replacement process is reduced.

The invention relates to the technical field of motorcycle hard key integration test, and discloses a test method of a key set test board, comprising the following steps: step 1, designing a test board, designing a special test board according to the number, arrangement mode and function requirements of motorcycle hard keys, the test board is provided with keys corresponding to motorcycle hard keys, a light simulation device, an interface used for being connected with a power supply and a power supply interface for an instrument host. 2, connecting a motorcycle instrument host, connecting the instrument host with the test board by using a special connecting line, and ensuring that the wiring definition is consistent with the interface of the instrument host; the invention provides a test method of a key set test board, and solves the problems that a traditional test method depends on connection of motorcycle hard keys with test equipment one by one, functional verification is carried out through tedious wiring and setting, the test mode is low in efficiency and needs a large amount of manpower and material resource investment, and the test cost is low. And the influence of human factors is easily caused.

The invention provides a verification system, a transaction-level modeling method, a verification method, a transaction-level modeling device and a computer readable storage medium. The verification system comprises a transaction-level modeling-based verification platform, the verification platform is used for verifying a chip with a plurality of cores, and the verification platform comprises a plurality of calculation modules used for simulating the plurality of cores; and the control module is in communication connection with the plurality of calculation modules through a transaction-level interface, and the control module is used for scheduling the plurality of calculation modules to execute the calculation task according to the sequential relationship among the plurality of cores. In the embodiment of the invention, the control module can schedule the plurality of calculation modules to execute the calculation task according to the time sequence relationship among the plurality of cores, and compared with a traditional function verification scheme in which each core independently serves as a verification object to perform function verification one by one, the time sequence relationship among the plurality of cores is favorably verified.