149 results about "Functional verification" patented technology

The invention discloses a verification method of an integrated circuit, electronic equipment, a program product and a storage medium, and is applied to the technical field of integrated circuits, and the verification method comprises the following steps: obtaining a time sequence description file used for reflecting a time sequence of a hardware interface protocol of the integrated circuit; analyzing the time sequence description file to generate a structured rule corresponding to the time sequence description file; converting the structured rule into an executable assertion; and integrating the executable assertion into a verification environment, and performing function verification on the integrated circuit by using the verification environment to obtain a verification result of the integrated circuit. By applying the scheme of the invention, end-to-end automatic generation from the time sequence description file to the verification environment is realized, manual coding requirements of workers are not needed, the development cycle is greatly shortened, the efficiency is improved, manual coding of the workers is not needed, and thus human errors can be effectively avoided.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention discloses an automatic driving test and evaluation method and device based on a large language model, and solves the problems that the pertinence of a test scene is insufficient, the result understanding depends on manpower, the evaluation interpretation is weak and the like in a traditional method. By means of semantic analysis, logical reasoning and domain knowledge support of a large language model and in combination with an automatic driving test domain knowledge graph, generation of a structured test portrait of a tested system, construction of a test demand list, generation of a semantic test scene description file, interpretable test result attribution, multi-dimensional comprehensive evaluation and report output are completed in sequence. And a test portrait is updated through report feedback to form a closed loop. The method is suitable for function verification and performance evaluation of an automatic driving simulation test, can also be used for post-processing analysis of real vehicle test data, realizes automation of a whole test process and interpretability of an evaluation result, and improves test precision and efficiency.

The invention belongs to the technical field of intelligent terminal mainboard testing, and discloses an intelligent terminal mainboard function verification system based on multi-protocol compatibility. Comprising a data acquisition module used for performing benchmark testing on each communication protocol supported by the intelligent terminal mainboard to obtain a benchmark data set of the intelligent terminal mainboard; the analysis and sequence generation module is used for acquiring a resource consumption portrait of the intelligent terminal mainboard; generating a concurrent test instruction sequence based on a pre-constructed test sequence generation engine; the concurrent test and diagnosis module is used for acquiring a concurrent test operation log by executing the concurrent test instruction sequence; identifying a causal relationship between a protocol performance degradation event and a resource state abnormal event based on the concurrent test operation log, and forming a resource protocol conflict event record; and the diagnosis and report generation module is used for acquiring diagnosis results of the resource protocol conflict events and further analyzing and generating a comprehensive verification report, so that a clear decision basis is provided.

The invention relates to the technical field of chips, and provides an interrupt module verification method and device, a medium and a program product, the method comprises the following steps: when it is monitored that an interrupt module generates an external observable behavior, comparing monitored behavior information with a reference value of the external observable behavior, and verifying the correctness of the external observable behavior; performing state calculation on the interrupt request input to the interrupt module, and determining an internal processing state of the interrupt request; an internal register state of the interrupt module is verified based on an internal processing state of the interrupt request. According to the invention, through a mode of combining black box verification of external observable behaviors with white box verification based on an internal processing state, comprehensive, deep and efficient function verification of a complex interrupt module is realized.

According to the technical scheme, the large-scale logic optimization multiplier verification method is characterized in that a four-stage pipeline processing mode is adopted, the first stage is a partial adder tree recovery stage, and the second stage is a partial adder tree recovery stage; the second stage is an architecture generation stage; the third stage is a function verification stage; and the fourth stage is an equivalence checking stage. The verification capability is improved in a breakthrough manner and is far better than that of an existing method; the innovative three-stage decomposition strategy significantly reduces the calculation complexity, the ILP algorithm optimizes resource allocation, the multi-stage scheduling balances the calculation load, and the QACO algorithm efficiently explores the design space, so that the RefSCAT-2.0 framework provided by the invention becomes the most effective solution for verifying a large-scale logic optimization multiplier at present. From the perspective of practice, the technical blank of large-scale logic optimization multiplier verification is filled up, and important tool support is provided for reliability guarantee of key computing systems such as artificial intelligence chips, high-performance CPUs and GPUs.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

The invention discloses an RoCEv2 protocol RC service type basic primitive function verification system based on a UVM. The system comprises a test case class used for configuring verification parameters, initializing a verification environment and driving a primitive execution process; the verification environment is used for packaging a plurality of agent components, a reference model, a register model and a scoreboard and carrying out data interaction through a TLM interface; the agent components are used for driving or monitoring an interface designed to be tested, comprise but are not limited to a register read-write agent, a work queue element WQE reading agent, a load data reading and receiving agent, a data packet sending and receiving agent, a complete queue element CQE receiving agent and a register model component, and are constructed based on a register abstraction layer RAL modeling method; and front-door and back-door access paths are supported. The method is high in automation degree, integrates constraint randomization, comparison verification and coverage rate analysis, and realizes full automation of the verification process.

The invention discloses an SRAM (Static Random Access Memory) verification method, system and equipment, relates to the technical field of integrated circuits, and is used for solving the problems of low code reuse rate, long verification period and difficulty in defect positioning in the existing SRAM verification method. The method comprises the following steps: setting a unified virtual shell program module for a to-be-verified SRAM memory module, and packaging key attribute information of the to-be-verified SRAM memory module through macro definition parameters; distributing a serial number for the SRAM type of each SRAM memory module to be verified, and establishing a mapping relation between the serial number and the interface module; calling a corresponding excitation signal from an excitation signal library according to the serial number, and determining a corresponding target interface module through a mapping relation; and connecting a virtual shell program module of the SRAM module to be verified through the target interface module, sending an excitation signal, and triggering function verification. According to the technical scheme provided by the invention, high efficiency, compatibility and expansibility of verification can be realized, and the accuracy of a verification result is improved.

The invention provides a system-level design generation method and system based on AI-Agent. The method provided by the invention comprises the following steps: receiving design demand information input by a user; carrying out system-level architecture design and system segmentation on the design demand information based on the AI-Agent, generating a system architecture scheme, design prompt information and a constraint file, and carrying out feasibility verification on the system architecture scheme by generating a rule checking mechanism to obtain the system architecture scheme, the design prompt information and the constraint file which pass verification; matching a corresponding path generation method based on the design prompt information passing verification or a Python algorithm code input by a user, and generating a hardware description language code based on the path generation method; and performing function verification on the hardware description language code, connecting the hardware description language code passing the function verification and the constraint file passing the verification with a back-end tool, performing layout wiring, and outputting a GDS-II layout file.

The application relates to the technical field of chip verification, and discloses an FPGA chip DSP module bit stream verification method and device. In the method, a bit stream file generation method is used to convert configurable parameters of a DSP module from abstract test intentions into specific physical configuration files, the low efficiency of configuring bit stream files for the functions of each DSP module is avoided, then a two-stage routing analysis method is used for function verification of the DSP module, a complete signal path mapping between an SWH port and core logic of the DSP module is accurately constructed, the correctness of the functions of the DSP module itself is ensured, and the interconnection correctness of the DSP module and adjacent modules is ensured, then an initial verification platform is reconstructed based on a port mapping table, and a high-abstraction-level behavior model is combined for result comparison, the verification efficiency and reliability of the DSP module are greatly improved, and the efficiency and accuracy of bit stream verification of the FPGA chip DSP module are ensured.

The application discloses a FLASH application verification system based on FPGA, which comprises a PC, an FPGA application verification board and a FLASH subboard. The FPGA application verification board is provided with two FPGA chips; each FPGA chip is connected with the FLASH and can independently access the FLASH to perform verification operation; each FPGA is externally connected with a large-capacity 160Mb SRAM; and the NOR_FLASH and the SPI_FLASH can be verified by replacing the FLASH subboard. The application also discloses a verification method based on the system, which comprises the following steps: determining power-on sequence, JTAG function verification, digital logic verification and read-write function verification. The application has comprehensive verification function, strong universality and important significance for application verification of a series of FLASH.

The embodiment of the application discloses a hardware accelerator whole system performance evaluation method and device facing high-level synthesis, which comprises the following steps: constructing a cycle-accurate and event-driven hardware accelerator simulation model based on the intermediate representation and static timing report generated by HLS; executing the hardware accelerator simulation model in the whole system simulator through the accelerator simulation object, so as to convert the timing and operation defined by the hardware accelerator simulation model into simulation events in the event queue of the whole system simulator and schedule and execute; collecting cycle-accurate simulation statistical data generated in the running process of the hardware accelerator simulation model in response to the scheduling and execution of the simulation events; and generating a performance evaluation report and a function verification result of the hardware accelerator based on the simulation statistical data and the function execution result of the hardware accelerator simulation model. The embodiment of the application can efficiently and accurately evaluate the performance of the hardware accelerator generated by HLS, so as to realize true hardware-software co-design and optimization.

The invention belongs to the technical field of semiconductor packaging, and relates to a design method for a substrate packaging box dam, an obtained packaging substrate and an electronic device.The method comprises the steps of substrate structure and stress pre-analysis, box dam structure design and parameter determination, substrate pre-forming and stress guiding, box dam manufacturing and pre-forming, and carrying out high-precision riveting and pressing on the box dam and the substrate, and carrying out stress balance and function verification. The stress of the guide substrate is analyzed in advance, and the high-rigidity box dam riveted with the substrate is designed, so that the stress is accurately counteracted, and the internal residual stress is balanced from the source; not only is the odd-number layer stacking structure design necessary for the radio frequency device successfully compatible, but also the two technological problems of non-uniform packaging glue flow and insufficient shearing force caused by warping are synchronously eliminated. Compared with a traditional scheme depending on an external jig or material optimization, the method has the advantages of root control, high efficiency and low cost, and provides key technical guarantee for miniaturization and high-reliability packaging of high-performance radio frequency products.

The invention discloses a method and a system for publishing and distributing information service, which realize full-process automatic management of application from developer submission and auditing to access party online through unified application uploading, mirror image construction, isolation environment auditing and multi-dimensional automatic verification. The system supports multi-tenant isolated deployment, and a built-in review rule engine completes compatibility, safety and functional verification; realizing cross-environment adaptation based on the standardized container mirror image and the reusable application assets; and dynamic resource scheduling and alarm rollback are supported through a multi-level elastic capacity expansion and contraction and abnormal instance processing mechanism. According to the method and the system, application version multiplexing and operation state visual monitoring can be realized, the delivery efficiency is improved, the operation and maintenance cost is reduced, and the cluster resource utilization rate and the system stability are improved.

The application provides a communication feature model driven relay protection device automatic test method and system, comprising the following steps: 1. Through active detection and response analysis, the communication protocol type, message format and function code mapping relationship of the relay protection device are identified, and a device communication feature model is constructed; 2. Based on the device communication feature model, test cases covering function verification, abnormal processing and boundary conditions are dynamically generated, and automatic mapping of the test cases and the device and execution sequence optimization are completed. The technical scheme can solve the problems of relay protection device test dependence on manual configuration, low efficiency and poor adaptability.

The embodiment of the invention provides a protocol testing method and device, electronic equipment and a storage medium. The method comprises the following steps: automatically acquiring protocol interaction data through a protocol recording tool, and determining a to-be-tested protocol; based on the protocol type classification, different model generation strategies are adopted to obtain test cases of the protocol to be tested; automatically executing the test case and recording response data; and obtaining a test result based on the response data. Protocol interaction data are automatically collected through a protocol recording tool, so that the cost of manual protocol combing and communication is reduced; different model generation strategies are adopted based on protocol type classification, diversified test cases can be efficiently generated, and conventional parameter verification and function verification requirements are met; manual intervention is further reduced through automatic execution and result analysis, the test efficiency and accuracy are improved, and meanwhile the data processing pressure of the server is relieved.

The invention relates to an off-line function verification system and method for a logic control board of an electric actuating mechanism. According to the system, a man-machine interaction module receives a function test scheme and sends the function test scheme to a host control module; the host control module instructs the direct current control module to output a direct current voltage signal to the logic control board to be tested through the output module according to the function test scheme; according to the function test scheme, the host control module controls the instruction simulation module to output valve control simulation signals corresponding to the valve control signal simulation instructions to the logic control board through the output module; the host control module controls the operation monitoring simulation module to output an operation monitoring simulation signal to the logic control board through the output module; and the host control module receives and verifies whether the first interface feedback information and the second interface feedback information meet function verification requirements in the function test scheme, and obtains an offline function verification result of the logic control board. The system is beneficial to improving the function verification accuracy of the logic control board.

According to the HIC function verification method and verification device, an EMC module with mature functions is arranged in a FLASH space of a CPU subsystem on an original SOC verification platform, and the EMC module is configured as an external host of an HIC module, so that a function verification platform of the HIC module is rapidly established, and no extra chip is needed. After grammar checking and instantiation are carried out on an HIC function verification platform by adopting a VCS command, a VCSrun command is executed to load a simulation file and a test routine to execute function simulation, and a verdei command is used for checking a simulation result, so that RTL codes of an HIC module can be modified, re-edited and re-simulated when BUG or other errors occur, the whole process is carried out in software simulation, and the simulation efficiency is improved. The time consumption of the FPGA process is avoided, and the interaction function of the HIC module and the external host and the function interaction of the HIC module and the internal resources of the SOC system are verified at the same time in the real and complete SOC environment.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

According to the test method for the high-low priority scheduling mechanism of the A664 switch, a minimum test environment is established, an A664 tester with four physical ports is used, and verification cases of high-priority data frame priority forwarding, priority data integrity and the number of high-low priority buffer areas in a congestion scene are designed. The integrity and accuracy of high-low priority transmission function verification are ensured, and the problem of verification test of the high-low priority working mechanism of the A664 network in the prior art is effectively solved. The method is high in universality and can be suitable for various A664 network devices and application scenes.

The application discloses a controller driver semi-physical simulation verification system for a space manipulator system, comprising: a real system and a simulation system; the real system comprises a space manipulator controller, joint drivers and joint units; the simulation system comprises a controller simulation module, joint driver simulation modules and a Vrep manipulator simulation module, which are used for simulating the related functions of the space manipulator controller, joint drivers and joint units respectively; the joint driver simulation modules are used for simulating the related functions of the joint drivers; and the Vrep manipulator simulation module is used for simulating the related functions of the joint units. The application aims at solving the difficulty in function verification caused by the high coupling degree of each subsystem of the space manipulator system, and designs simulation software of the subsystems and corresponding hardware and simulation models to build multiple semi-physical simulation subsystems, so that the function decoupling of the complete control system is completed, and each subsystem has the ability of independent debugging and joint debugging.

This application provides a functional verification method applicable to the fields of artificial intelligence or big data technology. The method includes: acquiring a preset knowledge graph, the knowledge graph including markers indicating differences between functional points in a first system and functional points in a second system, the differences including difference types; acquiring first system test cases corresponding to the differences; based on the difference types, executing a corresponding test case generation strategy on the first system test cases to obtain second system test cases; calculating the functional coverage of the second system with respect to the first system; and, if the functional coverage is greater than a preset coverage threshold, performing regression testing verification based on the second system test cases. This application also provides a functional verification device, equipment, storage medium, and program product.

The application provides a universal serial bus host controller function verification method and device, and relates to the technical field of computers.The method comprises the following steps: acquiring update log information of an enumeration log; the update log information comprises at least one standard type keyword; a plurality of type keywords are matched with the update log information respectively, a type keyword matched with the standard type keyword is determined as a target type keyword, and the type of an external universal serial bus device is determined according to the target type keyword; the target type keyword corresponds to the type of the external universal serial bus device; a target function verification strategy is determined from a plurality of preset function verification strategies based on the type of the external universal serial bus device, and the function verification strategy is used to perform function verification on the external universal serial bus device; the preset function verification strategy corresponds to the type of the external universal serial bus device in a one-to-one manner, and the function verification efficiency of the universal serial bus external device can be improved.

This invention discloses a functional verification system, method, device, and storage medium for a replacement TBOX. The system includes an OBD (On-Board Diagnostics) system, a cloud platform, and a TBOX. The OBD encapsulates TBOX replacement information, vehicle identification information, and operational status information into a standard information packet. The cloud extracts the vehicle VIN and TBOX-ICCID from the standard information packet, performs binding verification on the VIN and ICCID, and generates a session ID upon successful verification. The replacement type is determined using the session ID, and the corresponding diagnostic level instruction set is matched based on the replacement type. The diagnostic level instruction set is then broken down into functional instructions, and these fragments are sent to the OBD. After receiving the fragments, the OBD sequentially sends each functional instruction fragment to the TBOX for functional verification based on the session ID. This invention establishes a collaborative link between the OBD and the cloud, issuing dynamic diagnostic instructions to achieve accurate TBOX functional verification.

The invention discloses a busbar differential protection capacity expansion method and system and a storage medium, and belongs to the technical field of power system relay protection. The method is applied to a double-bus wiring system configured with two sets of redundant bus differential protection devices, and the core is a differential transformation scheme: firstly analyzing hardware configuration and branch distribution conditions of the two sets of devices, directly adding a branch to a device with spare resources, and accessing a newly-added main transformer interval; and for the device with the full branches, the access position is vacated by adjusting the branch distribution of the existing incoming line interval and the main transformer interval. In the construction process, short circuit is carried out first and then reconnection is carried out to guarantee the safety of a current loop, and hardware wiring optimization, protection program upgrading and function verification are matched to complete transformation. The corresponding system comprises the bus differential protection device transformed by the method, and a computer readable storage medium for storing a program upgrading step. The whole set of equipment does not need to be replaced, the existing hardware redundancy expansion function is utilized, the modification cost is low, the safety risk is small, and the flexibility is high.

The invention relates to the technical field of aviation electrical system design and verification, and provides an aircraft power distribution system controller rapid prototype design method and system based on multi-level hardware-in-loop verification, and the method comprises the steps: S1, an architectural offline simulation stage: carrying out the preliminary function verification and parameter setting of a control logic through a unified simulation model; s2, in a distributed real-time simulation and code generation stage, real-time closed-loop verification and iterative optimization are carried out on control logic; and S3, a hardware replacement type rapid prototype verification stage: performing performance verification and final setting on the control strategy under a highly approximate real working condition. The method provided by the invention not only can greatly reduce the safety risk in the physical test, but also has the remarkable advantages of short development period, low verification cost and support of multi-level integrated verification, thereby providing reliable experimental data support for the subsequent physical verification of the aircraft power distribution system control strategy.

The invention relates to an off-line function verification system and method for a power module of an electric actuating mechanism. According to the system, a man-machine interaction module receives function test information input by a user and sends the function test information to a host control module; the host control module respectively sends an AC voltage control instruction and a DC voltage control instruction to the AC control module and the DC control module according to the function test information, and controls the AC control module and the DC control module to output an AC voltage signal and a DC voltage signal to the output module; the output module outputs the signal to the power supply module of the to-be-tested electric actuating mechanism; the function detection module collects direct current voltage data corresponding to different interfaces of the power supply module and sends the direct current voltage data to the host control module. And the host control module verifies whether the direct-current voltage data meet the function verification requirements in the function test information to obtain a function verification result of the power supply module. The method is beneficial to improving the function verification efficiency of the power module of the electric actuating mechanism.

The invention relates to the technical field of chip design, and discloses a verification method and system for a memory, and the method comprises the steps: building a reference model array containing a data state tag through a test platform before an instruction sequence is sent, and predicting an access mode when the instruction sequence accesses the memory; the access mode comprises front door access and back door access; simulating an execution behavior of receiving the instruction sequence by the memory to obtain expected storage data; and comparing the expected storage data with the address data of the instruction sequence in the reference model array so as to verify the reliability of the memory. By optimizing the simulation process, the simulation execution efficiency of functional verification of the flash memory chip can be remarkably improved, and meanwhile, the reusability of a verification platform between different design iterations and projects is enhanced.

The invention discloses an all-digital verification method for a motor control system. The verification method comprises the following steps: S1, defining a verification object and control core parameters; s2, constructing a high-granularity processor digital model; s3, a DSP software operation environment is built, and DSP program zero-modification direct application is achieved; s4, designing to realize the universality and expansibility of the model, supporting the development and debugging of multiple types of DSP programs, and adapting to different control systems; s5, establishing real-time data interaction and system closed-loop control simulation; and S6, running the simulation system to carry out multi-dimensional function verification, and realizing automatic testing, limit testing and result output of the DSP program. According to the method, the zero-modification direct application and convenient development of the DSP program of the motor control system are realized, the pain points of traditional hardware tests such as complex program algorithm verification, sequential logic guarantee, limit scene test and the like are solved through the flexibility and the safety of a full-digital environment, and an efficient development closed loop is really formed.