57 results about "Hardware specification" patented technology

The invention discloses a large language model reasoning method based on an unloading pipeline, and the method comprises the steps: obtaining an optimal unloading reasoning strategy through calculation according to the obtained model structure information and model configuration information of a large language model, and the hardware specification information and system operation load information of reasoning equipment; and then tasks in the optimal unloading reasoning strategy are scheduled through a fine-grained pipeline to output an unloading reasoning result of the large language model. According to the method, reasoning tasks are automatically configured according to input large language model information and a system hardware environment, and hardware resource use and reasoning performance are optimized. For deployment of a large language model on local equipment, transmission optimization is carried out for unloading using a solid state disk, so that the data transmission speed is increased. Meanwhile, fine-grained assembly line task scheduling is carried out for unloading reasoning, and the reasoning concurrency and the model throughput can be remarkably improved through unloading reasoning of an assembly line model.

A method or system for implementing a machine learning pipeline on a chipset comprising a plurality of hardware compute elements. The system accesses a hardware-agnostic functional description of the machine learning pipeline, wherein the description specifies a plurality of functional modules, including at least one machine learning model. Hardware specifications of the chipset are accessed to identify the available hardware compute elements. Based on the hardware specifications, the functional modules are synthesized into a plurality of interconnected executable components configured to execute on at least two different hardware compute elements. An implementation package is generated, comprising the executable components and metadata describing interconnections between them. The implementation package is then deployed to the chipset, where the executable components are executed by the identified hardware compute elements.

The invention provides a mainboard power supply output voltage stability test method and system, and the method comprises the steps: generating a dynamic stepped load current based on a load demand parameter and a limit working condition defined by a hardware specification when a mainboard operates in a preset multi-mode switching state, and setting a first synchronization window before each step switching moment, setting a second synchronization window after the step switching time, collecting voltage waveform data, inputting the voltage waveform data into a preset filtering algorithm, extracting an overshoot amplitude and recovery time, constructing an asymmetric coupling model, and taking a difference value between the overshoot amplitude and a preset fluctuation range as a first stability index; the ratio of the recovery time to the response time threshold value is used as a second stability index, nonlinear weight distribution of the two indexes in multiple step intervals is calculated, a stability grade judgment result is generated in combination with a circuit board wiring impedance characteristic library, and the test compatibility of high-density mainboard multi-phase power supply and high-frequency devices is improved.

The invention discloses a system burning method of embedded equipment and electronic equipment, in a recovery mode, to-be-burnt equipment can receive an external instruction to carry out firmware updating, target specification types of multiple to-be-burnt equipment are determined according to a product identification code, and the to-be-burnt equipment is stored in the product identification code. And obtaining the flash script, the root file system and a differentiated configuration file corresponding to the target specification type. As the multiple to-be-burnt devices in the current batch have the same hardware specification, the target specification types of the multiple to-be-burnt devices are determined through the read product identification codes, so that the differentiated configuration files corresponding to the target specification types are obtained. Since the flash script and the root file system both support devices of various specifications and types, embedded devices of different specifications and types can be processed, and only specific differentiated configuration files need to be provided for the embedded devices of different specifications, so that the number of repeated mirror images is greatly reduced, and the resource reuse rate between embedded device modules is improved.

The invention provides a method and system for dispatching heterogeneous GPUs through cross-cluster management software, and relates to the technical field of GPU resource dispatching.The method comprises the steps that physical topology data, hardware specification data and historical task records of GPU nodes are obtained through the cross-cluster management software, an association degree matrix between GPU units is established, and a topology grouping set is generated; calculating a communication efficiency index based on topology detection analysis, constructing a topological graph model, and determining an optimal communication path of a multi-card task; generating a perception scheduling strategy in combination with a multi-objective optimization algorithm, and selecting an optimal GPU combination from the grouping set; in the task execution process, a scheduling strategy is dynamically adjusted according to the real-time cluster state and task efficiency data, continuous adaptation of a physical topological structure and task requirements is kept, and finally efficient collaborative scheduling of cross-cluster heterogeneous GPU resources is achieved. According to the method, the scheduling efficiency of heterogeneous GPU resources in a distributed computing scene and the overall performance of the system are improved.

The invention provides a hyper-parameter optimization system and a hyper-parameter optimization method, which comprise the following steps of: selecting a model-related hyper-parameter combination which conforms to hardware specification limitation and efficiency limitation from a hyper-parameter set by searching a model database; based on the model related hyper-parameter combination, searching the optimal hyper-parameter in each group of model non-closed hyper-parameters through a hyper-parameter adjuster to obtain an optimal hyper-parameter combination; and establishing a machine learning model based on the optimal hyper-parameter combination.

Network optimization and repair using Artificial Intelligence (AI) / Machine Learning (ML) is disclosed. More specifically, AI / ML models are trained to predict hardware and software failures of Radio Access Network (RAN) components by analyzing telemetry data and / or trained to extend battery life during power failures. The telemetry data may include performance logs from performance monitors, fault logs from fault monitors, and traffic information for traffic flowing through the RAN. Hardware specifications of the RAN equipment, operating temperatures, power consumption, etc. may also be stored and monitored. This data may be monitored across the infrastructure, platform, and application layers. One or more rApps in a Non-Real Time RAN Intelligent Controller (NRT RIC) may use the AI / ML models to predict failures, and potentially, provide an indication of an estimated time when failure is predicted to occur.

According to the chip system, the data transmission method and the related equipment provided by the embodiment of the invention, the chip system comprises IO core particles and a plurality of calculation core particles, each calculation core particle is configured with a corresponding core particle center, and each calculation core particle is connected with at least two physical interconnection ports in the IO core particles through the core particle center; the core grain center comprises a splitting unit and a merging unit, and the splitting unit is used for distributing data streams sent by the computing core grains to at least one physical interconnection port according to service types; the merging unit is used for recombining the data stream received from the physical interconnection port or directionally forwarding the data stream to the computing core grain, and the data throughput rate and the overall transmission efficiency in a large-scale parallel computing scene are remarkably improved on the premise that the hardware specification of the external IO core grain does not need to be modified.

The invention discloses a convolutional neural network performance prediction method and system based on hardware interaction features, and relates to the technical field of artificial intelligence and computer system performance optimization, and the method comprises the steps: obtaining hierarchical features of a convolutional neural network model; based on the hierarchical features, combined analysis is carried out in combination with the hardware specification of the target hardware platform, and interaction features are obtained through calculation; a Transform model with a bias matrix is adopted for prediction, interaction features are processed by a hardware perception attention bias module to generate a hardware perception bias matrix, and the hardware perception bias matrix is input to a Transform encoder; and after the hierarchical features are processed by an input encoder, a Transform encoder and a linear decoding layer in sequence, the running time of the convolutional neural network model is predicted. According to the method, the reasoning training time is predicted by statically analyzing the architecture of the convolutional neural network model and the specification of the target hardware.

This disclosure is directed to methods and systems that establish a secure data channel between a host and a disaggregated hardware device (“DHD”) of a data center. The system comprises an initiator host that runs objects, such as virtual machines and containers. The host includes an initiator smart network interface card (“SNIC”). The initiator SNIC includes a virtual device, a trust platform module (“TPM”) and a security engine. The system also comprises a target host equipped with a DHD and a target SNIC. The target SNIC includes a TPM and a security engine. The TPM and the security engine of the initiator SNIC and the TPM and the security engine of the target SNIC establish a secure data channel between an object running on the host and the DHD.

The invention provides a communication method and a communication device, and the method comprises the steps that a first device can obtain one or more first phase differences between downlink measurement channels of a first TRP and a second TRP through receiving a first channel state information report reported by a terminal; and then determining a second phase difference between the uplink measurement channels of the first TRP and the second TRP, and determining a phase calibration coefficient between the first TRP and the second TRP based on the first phase difference and the second phase difference, thereby adjusting the sending or receiving phase of the TRP based on the phase calibration coefficient when the TRP sends a downlink reference signal or receives an uplink reference signal next time. Realization of reciprocity correction between TRPs is facilitated under the condition that the TRP hardware specification is not limited, and improvement of data transmission performance is facilitated. Moreover, the first channel state information report reported by the terminal only needs to carry phase-related information (such as the first phase difference), so that the feedback overhead can be reduced.

Broadly speaking, the present techniques generally relate to a method for training a machine learning, ML, model to perform semantic image segmentation, and to a computer-implemented method and apparatus for performing semantic image segmentation using a trained machine learning, ML, model. The training method enables a semantic image segmentation ML model that is able to make predictions faster, without significant loss in accuracy. The training method also enables the ML model to be implemented on apparatus with different hardware specifications, i.e. different computational power and memory, for example.

The invention provides a flash memory data packet writing method and device, and relates to the field of flash memory data packet writing and garbage collection optimization. The method comprises the steps of obtaining file features, user behavior features and system metadata features of to-be-written data, and predicting a life cycle frequency band of the data based on multi-dimensional features; according to the predicted life cycle frequency band, aggregating data with similar failure characteristics into data groups, and matching the data groups to corresponding physical storage blocks; writing the data in the data group into the same physical storage block adaptive to the hardware specification so as to realize high synchronization of data failure time; and when the valid data volume in the data group is lower than a preset threshold value, triggering a garbage collection mechanism, and directly executing a whole block erasing operation on the physical storage block to avoid valid data migration. According to the method provided by the embodiment of the invention, write amplification and system delay can be effectively reduced, the service life of the flash memory storage system is prolonged, and the storage performance and the resource utilization rate are improved.

The invention provides a communication method and device for a GPU cluster, electronic equipment and a medium, and relates to the technical field of artificial intelligence, in particular to the technical field of distributed computing, GPU cluster communication optimization and the like. According to the implementation scheme, the method comprises the steps of obtaining network performance data among a plurality of GPU nodes in a GPU cluster and hardware specification data of each GPU node in the plurality of GPU nodes; generating a hybrid logic communication topology for the plurality of GPU nodes based on the network performance data and the hardware specification data, the hybrid logic communication topology being a combination of at least two of a tree topology, a ring topology and a bus topology; determining a communication protocol adopted by a communication link in the hybrid logic communication topology based on the network performance data; and communicating among the plurality of GPU nodes according to the generated hybrid logic communication topology and communication protocol.

An electronic device and a controlling method of an electronic device are provided. The electronic device includes identifying whether each of one or more neural network models included in a first external device is suitable for hardware of the electronic device and whether each of the one or more neural network models identified as suitable for the hardware of the electronic device is suitable to replace the neural network models included in the electronic device, based on first device information on a hardware specifications of the electronic device, second device information on a hardware specification of the first external device, first model information on the one or more neural network models included in the first external device, and second model information on the one or more neural network models included in the electronic device.

The invention discloses an efficient linkage method between equipment based on an open source gap, and relates to the field of industrial Internet of Things. The method comprises the following steps: determining a control instruction and a state reading instruction of a mechanism through a reference technical manual and a hardware specification; hardware drive adaptation of the open-source swan-monk system is completed, and system source codes are subjected to cross compiling and deployed to hardware development equipment; writing a bottom layer source code for reading and controlling the state of the mechanism; the bottom layer source code is packaged into an NAPI interface, so that an upper layer interface can conveniently call; developing an operation interface suitable for the swan monk system, calling an NAPI interface on an upper-layer interface, compiling corresponding task logic, and burning the task logic to two hardware devices respectively; codes for communication between the equipment in the gap are written by using the distributed soft bus characteristics of the gap. According to the method, efficient linkage between the devices can be achieved, the method has important practical value for achieving intelligentization, and development and innovation of the domestic Internet of Things technology are promoted.

The invention discloses a screen brightness adjusting method, the adjusting method is applied to a screen of an LED layer, the LED layer is divided into a plurality of LED blocks, and the adjusting method comprises the following steps: S1, obtaining hardware configuration parameters of the screen; s2, based on the maximum power value and the total number of the blocks, calculating the theoretical maximum number of the blocks which can be driven by the LED layer under the constraint of the maximum power; s3, current ambient light parameters are collected in real time; s4, dynamically generating a target window value through a pre-trained brightness compensation model according to the ambient light parameters and the theoretical maximum block number; and S5, generating a corresponding driving control parameter according to the target window value, and controlling a screen to display. By combining hardware power constraint modeling, ambient light intelligent perception, display content self-adaptive identification and closed-loop power consumption control, the problems that in the prior art, complex ambient light adaptability is poor, screen hardware specification compatibility is insufficient, and over-drive and non-over-drive screen management is not unified are effectively solved.

Mechanisms to transform a multimodal hardware specification document into register-transfer level (RTL) code by configuring a large language model into multiple agents to transform the hardware specification document into a structured implementation plan comprising a sequence of hardware functions, configuring the large language model to apply progressive coding and prompt optimization to sequentially transform the hardware functions into low-level program code through a plurality of progressively lower-level code generation stages, and transforming the low-level program code of the hardware functions into the RTL code through a code optimizer and high-level synthesis tool.

A digital engineering ecosystem may use artificial intelligence to generate a virtual hardware interface to emulate a hardware interface described in one or more hardware specifications. The virtual hardware interface may receive executable code configured to execute on the hardware interface. The virtual hardware interface may execute the received executable code, and, after being successfully executed, the execution of the executable code may be logged.

Relatively simple user input is used to build an entire application. Input data defines a set of specifications for an automated machine. The set of specifications includes one or more of hardware specifications, operating systems, software frameworks, runtime environments, network connectivity, and environmental considerations. The input data is analyzed to retrieve relevant information from a large corpus including a plurality of libraries. One or more prompts are generated based on the relevant information, and the one or more prompts are used to generate programmable logic controller (PLC) code including a sequence of operations for controlling the automated machine.

Embodiments of the present application provide a hardware specification test tool, a method and related equipment, wherein the hardware specification test tool comprises: a plurality of special test modules; one special test module tests one hardware specification of an acceleration computing chip; different special test modules are aimed at different hardware specifications to cover all hardware specifications of the acceleration computing chip; when testing the hardware specification, one or more special test modules are dispatched, and the dispatched special test module tests the hardware specification in at least one dimension; wherein one dimension corresponds to a quantifiable performance item of the hardware specification in a specific test direction, and multiple dimensions cooperatively cover the overall performance characteristics of the hardware specification. The technical scheme provided by the embodiments of the present application can perform integrated and complete hardware specification testing on the acceleration computing chip, and improve the test comprehensiveness of the hardware specification test tool.

The invention relates to a method for generating a task-specific adapted topology for hardware based on quantum electrodynamics (cQED), characterized in that it comprises the iterative steps of: - determining an error committed by a circuit initially obtained by transpilation of an M agnostic qubit generated using a client task; - comparing the transpiled circuit error with an error threshold corresponding to the circuit of M agnostic qubits; - if the transpiled circuit error is greater than the error threshold, modifying some of the hardware specifications to be processed in the transpilation step; - if the transpiled circuit error is less than the error threshold, supplying the transpiled circuit as a task-specific adapted topology to a chip design and nanofabrication unit.

A processor-implemented method for neural architecture search (NAS) begins by generating a over-parameterized hyper-network having a plurality of layers. The super network has a plurality of operator types. Each of the layers includes a maximum super kernel corresponding to the search space. The method also includes performing a gradient descent to evolve a maximum super kernel into a small kernel corresponding to the search space to generate a series of kernel codes. The method further includes identifying, for each layer of the hypernetwork, a subset of kernel codes from the series of kernel codes based on the gradient descent. The method determines a set of candidate architectures based on the kernel coding subset, each of the candidate architectures having a different model size. The method selects a target model from the set of architectures based on satisfying the hardware specifications, and then applies the target model.

The chip system, the data transmission method and the related equipment provided in the embodiments of the present application, the chip system comprises: an IO chip and a plurality of computing chips, each computing chip is configured with a corresponding chip hub, and each computing chip is connected with at least two physical interconnection ports in the IO chip through the chip hub; the chip hub comprises a splitting unit and a merging unit, the splitting unit is used for distributing the data stream sent by the computing chip to at least one physical interconnection port according to the service type; the merging unit is used for recombining or directionally forwarding the data stream received from the physical interconnection port to the computing chip, without modifying the external IO chip hardware specification, the data throughput rate and the overall transmission efficiency in the large-scale parallel computing scene are significantly improved.

The application relates to an application binary file standardization processing method and system, and the method comprises the following steps: establishing an application binary file standard library according to a system specification system file; obtaining a list of application binary files to be processed, identifying an application category according to a file attribute, and extracting a corresponding checking strategy; performing standard checking on the file according to the checking strategy; determining, by a user, whether to perform standardization processing on a non-standard list; packaging the processed application binary file to obtain a deb application package; recording process log information and test results, and archiving the deb application package. According to the application, a corresponding standard library is established according to a software and hardware specification system file, checking rules are automatically identified and extracted, standardization checking and processing of the binary file are completed, and a standard deb package is automatically generated. According to the application, a binary file standard library can be established according to core specifications which independently affect the compatibility of an operating system, the checking efficiency is improved, and the standardization and compatibility of the application on the operating system are ensured.

Various embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities, and / or the like for receiving pre-imaging data for a plurality of pre-imaged computing devices; generating, using the pre-imaging data, a plurality of data objects that respectively correspond to the plurality of pre-imaged computing devices, wherein a first data object of the plurality of data objects comprises a data construct that describes a first computing device of the plurality of pre-imaged computing devices; receiving a computing device provisioning request comprising one or more hardware specifications and application criteria; determining a computing device from the plurality of pre-imaged computing devices based at least in part on the one or more hardware specifications and the plurality of data objects; generating a custom build instruction identifying the application criteria; and transmitting the custom build instruction to the computing device.

The invention relates to a multi-equipment cooperative control method and device, an air conditioning system and a storage medium. The method comprises the following steps: identifying a first device and a second device which have the same device model and different device functions; only the first equipment has a target function; after a cooperative control instruction for the target function is received, a control action executed by the first equipment after the target function is started is determined; and controlling the second equipment to execute the same control action as the first equipment according to the control action executed by the first equipment after the target function is started. Due to the fact that the hardware specifications of the devices of the same device model are the same, under the condition that the first device has the target function and the second device does not have the target function, if the multiple devices need to cooperatively execute the target function, the second device can be controlled to execute the same control action as the first device; and the target function of the first equipment is multiplexed into the second equipment, so that the purpose that the first equipment and the second equipment uniformly execute the same function is achieved.

An electronic device and a control method of the electronic device are provided. The electronic device includes first device information based on a hardware specification of the electronic device, second device information on a hardware specification of a first external device, first model information on one or more neural network models included in the first external device, and identifying whether each of the one or more neural network models included in the first external device is suitable for hardware of the electronic device with respect to second model information of the one or more neural network models included in the electronic device, and whether each of the one or more neural network models identified as suitable for hardware of the electronic device is suitable for replacing a neural network included in the electronic device.

The invention discloses Internet of Things equipment and a smart home system. The Internet of Things equipment comprises a main control chip; the communication module is coupled to the main control chip, a processor core is arranged in the communication module, the communication module is used for receiving the data sent by the main control chip and carrying out logic data processing on the data, and the logic data processing at least comprises packet loss retransmission and / or flow control. In this way, the requirement for the hardware specification of the main control chip can be lowered.