29 results about "Hardware specification" patented technology

The invention provides a method and system for dispatching heterogeneous GPUs through cross-cluster management software, and relates to the technical field of GPU resource dispatching.The method comprises the steps that physical topology data, hardware specification data and historical task records of GPU nodes are obtained through the cross-cluster management software, an association degree matrix between GPU units is established, and a topology grouping set is generated; calculating a communication efficiency index based on topology detection analysis, constructing a topological graph model, and determining an optimal communication path of a multi-card task; generating a perception scheduling strategy in combination with a multi-objective optimization algorithm, and selecting an optimal GPU combination from the grouping set; in the task execution process, a scheduling strategy is dynamically adjusted according to the real-time cluster state and task efficiency data, continuous adaptation of a physical topological structure and task requirements is kept, and finally efficient collaborative scheduling of cross-cluster heterogeneous GPU resources is achieved. According to the method, the scheduling efficiency of heterogeneous GPU resources in a distributed computing scene and the overall performance of the system are improved.

According to the chip system, the data transmission method and the related equipment provided by the embodiment of the invention, the chip system comprises IO core particles and a plurality of calculation core particles, each calculation core particle is configured with a corresponding core particle center, and each calculation core particle is connected with at least two physical interconnection ports in the IO core particles through the core particle center; the core grain center comprises a splitting unit and a merging unit, and the splitting unit is used for distributing data streams sent by the computing core grains to at least one physical interconnection port according to service types; the merging unit is used for recombining the data stream received from the physical interconnection port or directionally forwarding the data stream to the computing core grain, and the data throughput rate and the overall transmission efficiency in a large-scale parallel computing scene are remarkably improved on the premise that the hardware specification of the external IO core grain does not need to be modified.

This disclosure is directed to methods and systems that establish a secure data channel between a host and a disaggregated hardware device (“DHD”) of a data center. The system comprises an initiator host that runs objects, such as virtual machines and containers. The host includes an initiator smart network interface card (“SNIC”). The initiator SNIC includes a virtual device, a trust platform module (“TPM”) and a security engine. The system also comprises a target host equipped with a DHD and a target SNIC. The target SNIC includes a TPM and a security engine. The TPM and the security engine of the initiator SNIC and the TPM and the security engine of the target SNIC establish a secure data channel between an object running on the host and the DHD.

Broadly speaking, the present techniques generally relate to a method for training a machine learning, ML, model to perform semantic image segmentation, and to a computer-implemented method and apparatus for performing semantic image segmentation using a trained machine learning, ML, model. The training method enables a semantic image segmentation ML model that is able to make predictions faster, without significant loss in accuracy. The training method also enables the ML model to be implemented on apparatus with different hardware specifications, i.e. different computational power and memory, for example.

Mechanisms to transform a multimodal hardware specification document into register-transfer level (RTL) code by configuring a large language model into multiple agents to transform the hardware specification document into a structured implementation plan comprising a sequence of hardware functions, configuring the large language model to apply progressive coding and prompt optimization to sequentially transform the hardware functions into low-level program code through a plurality of progressively lower-level code generation stages, and transforming the low-level program code of the hardware functions into the RTL code through a code optimizer and high-level synthesis tool.

Embodiments of the present application provide a hardware specification test tool, a method and related equipment, wherein the hardware specification test tool comprises: a plurality of special test modules; one special test module tests one hardware specification of an acceleration computing chip; different special test modules are aimed at different hardware specifications to cover all hardware specifications of the acceleration computing chip; when testing the hardware specification, one or more special test modules are dispatched, and the dispatched special test module tests the hardware specification in at least one dimension; wherein one dimension corresponds to a quantifiable performance item of the hardware specification in a specific test direction, and multiple dimensions cooperatively cover the overall performance characteristics of the hardware specification. The technical scheme provided by the embodiments of the present application can perform integrated and complete hardware specification testing on the acceleration computing chip, and improve the test comprehensiveness of the hardware specification test tool.

The invention relates to a method for generating a task-specific adapted topology for hardware based on quantum electrodynamics (cQED), characterized in that it comprises the iterative steps of: - determining an error committed by a circuit initially obtained by transpilation of an M agnostic qubit generated using a client task; - comparing the transpiled circuit error with an error threshold corresponding to the circuit of M agnostic qubits; - if the transpiled circuit error is greater than the error threshold, modifying some of the hardware specifications to be processed in the transpilation step; - if the transpiled circuit error is less than the error threshold, supplying the transpiled circuit as a task-specific adapted topology to a chip design and nanofabrication unit.

The chip system, the data transmission method and the related equipment provided in the embodiments of the present application, the chip system comprises: an IO chip and a plurality of computing chips, each computing chip is configured with a corresponding chip hub, and each computing chip is connected with at least two physical interconnection ports in the IO chip through the chip hub; the chip hub comprises a splitting unit and a merging unit, the splitting unit is used for distributing the data stream sent by the computing chip to at least one physical interconnection port according to the service type; the merging unit is used for recombining or directionally forwarding the data stream received from the physical interconnection port to the computing chip, without modifying the external IO chip hardware specification, the data throughput rate and the overall transmission efficiency in the large-scale parallel computing scene are significantly improved.

The application relates to an application binary file standardization processing method and system, and the method comprises the following steps: establishing an application binary file standard library according to a system specification system file; obtaining a list of application binary files to be processed, identifying an application category according to a file attribute, and extracting a corresponding checking strategy; performing standard checking on the file according to the checking strategy; determining, by a user, whether to perform standardization processing on a non-standard list; packaging the processed application binary file to obtain a deb application package; recording process log information and test results, and archiving the deb application package. According to the application, a corresponding standard library is established according to a software and hardware specification system file, checking rules are automatically identified and extracted, standardization checking and processing of the binary file are completed, and a standard deb package is automatically generated. According to the application, a binary file standard library can be established according to core specifications which independently affect the compatibility of an operating system, the checking efficiency is improved, and the standardization and compatibility of the application on the operating system are ensured.

Various embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities, and / or the like for receiving pre-imaging data for a plurality of pre-imaged computing devices; generating, using the pre-imaging data, a plurality of data objects that respectively correspond to the plurality of pre-imaged computing devices, wherein a first data object of the plurality of data objects comprises a data construct that describes a first computing device of the plurality of pre-imaged computing devices; receiving a computing device provisioning request comprising one or more hardware specifications and application criteria; determining a computing device from the plurality of pre-imaged computing devices based at least in part on the one or more hardware specifications and the plurality of data objects; generating a custom build instruction identifying the application criteria; and transmitting the custom build instruction to the computing device.

An electronic device and a control method of the electronic device are provided. The electronic device includes first device information based on a hardware specification of the electronic device, second device information on a hardware specification of a first external device, first model information on one or more neural network models included in the first external device, and identifying whether each of the one or more neural network models included in the first external device is suitable for hardware of the electronic device with respect to second model information of the one or more neural network models included in the electronic device, and whether each of the one or more neural network models identified as suitable for hardware of the electronic device is suitable for replacing a neural network included in the electronic device.

The application provides a method and system for scheduling heterogeneous GPUs by cross-cluster management software, and relates to the technical field of GPU resource scheduling, wherein the method comprises obtaining physical topology data, hardware specification data and historical task records of GPU nodes through cross-cluster management software, establishing an association matrix between GPU units and generating a topology grouping set; based on the topology detection analysis, calculating the communication performance index, constructing a topology graph model and determining the optimal communication path of the multi-card task; combining the multi-objective optimization algorithm to generate a perception scheduling strategy and selecting the optimal GPU combination from the grouping set; in the task execution process, dynamically adjusting the scheduling strategy according to the real-time cluster state and task performance data, maintaining the continuous adaptation of the physical topology structure and the task demand, and finally realizing the efficient collaborative scheduling of cross-cluster heterogeneous GPU resources. The application improves the scheduling efficiency of heterogeneous GPU resources and the overall performance of the system in the distributed computing scenario.

Device and environmental data are collected from user devices participating in communication sessions of a communications platform. The device and environmental data includes at least one of hardware specifications, firmware versions, processor utilization, memory utilization, ambient noise levels, or device statuses. A device-related or environmental issue is identified based on the device and environmental data. A notification is generated in response to identifying the device-related or environmental issue.

This invention discloses a method and system for predicting the performance of convolutional neural networks (CNNs) based on hardware interaction features, relating to the fields of artificial intelligence and computer system performance optimization. The method involves obtaining hierarchical features of a CNN model; calculating interaction features based on these hierarchical features and the hardware specifications of the target hardware platform; using a Transformer model with a bias matrix for prediction; generating a hardware-aware bias matrix after processing the interaction features by a hardware-aware attention bias module, and then inputting this matrix into the Transformer encoder; and finally, after sequential processing by an input encoder, a Transformer encoder, and a linear decoding layer, predicting the runtime of the CNN model. This invention predicts the inference and training time of a CNN model through static analysis of its architecture and target hardware specifications.

The application discloses a kind of high-efficiency automatic tuning methods for dynamic shape model reasoning, the tuning method includes: step one, one or more to be tuned tensor program is normalized and is processed, is converted into the standard form conforming to preset scheduling template;Step two, including standardization tensor program, program feature information and target hardware specification information is passed to tuning engine and optimization is started;Step three, tuning engine receives including the bucketing factor obtained by bucketing strategy and the TopK value indicating the optimal performance of the first K configuration parameters, allocates scheduling template and configuration parameter transmitter, cooperates, and optimizes each barrel corresponding subproblem, obtains the corresponding optimization kernel in each barrel range to complete automatic tuning.The application also discloses a tuning system for implementing the above method, which has a wide range of application scenarios.

The invention discloses a method for rapidly solving an optimal VCOM value, and relates to the technical field of display panel calibration, and the method comprises the following specific steps: parameter configuration and sampling point generation: obtaining a VCOM effective adjustment range defined by a panel driving IC hardware specification, recording the minimum value of the range as a minimum value, recording the maximum value as a maximum value, and generating a sampling point; uniformly dividing the obtained interval into five continuous sub-intervals according to a fixed step length rule, and generating six sampling points; according to the invention, the effective adjustment range of the VCOM is determined by acquiring the hardware specification file of the panel drive IC, and the intervals are uniformly divided according to the fixed step length to generate the sampling points, so that the number of the sampling points is greatly reduced, the operation steps are simplified, and the calibration efficiency is effectively improved.

In summary, this technology generally relates to a method for training a machine learning (ML) model to perform semantic image segmentation, and to a computer-based method and apparatus for performing semantic image segmentation using the trained ML model. The training method enables the semantic image segmentation ML model to make predictions faster without significant loss of accuracy. The training method also enables the ML model to be implemented on devices with different hardware specifications, such as different computing power and memory.

This disclosure proposes a hardware-based parameter tuning method, apparatus, electronic device, and storage medium. The method includes: obtaining a target kernel function to be optimized; automatically identifying at least one adjustable parameter in the target kernel function in response to the target kernel function; determining a candidate value range for each adjustable parameter based on the hardware specifications of the target hardware platform executing the target kernel function; pruning the candidate value range corresponding to each adjustable parameter based on the scale information of the data to be processed to generate a candidate configuration space; and performing a search in the candidate configuration space to determine the optimal execution configuration of the target kernel function. This disclosure can automatically construct an efficient and feasible tuning configuration space, reducing the threshold for tuning and improving tuning efficiency.

The invention relates to a method for generating a task-specific adapted topology for circuit quantum electrodynamics (cQED)-based hardware, characterized in that it comprises the iterative steps of: - determining an error made by a circuit initially obtained by transpiling an agnostic M qubit generated from a client task, - comparing said transpiled circuit error to an error threshold corresponding to said circuit of agnostic M qubits, - if said transpiled circuit error is greater than said error threshold, modifying certain of said hardware specifications to be addressed in the transpilation step, - if said transpiled circuit error is less than said error threshold, providing said transpiled circuit as a task-specific adapted topology to a chip design and nanofabrication unit. Figure to be published with the abstract: Fig. 1

Various embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities, and / or the like for receiving pre-imaging data for a plurality of pre-imaged computing devices; generating, using the pre-imaging data, a plurality of data objects that respectively correspond to the plurality of pre-imaged computing devices, wherein a first data object of the plurality of data objects comprises a data construct that describes a first computing device of the plurality of pre-imaged computing devices; receiving a computing device provisioning request comprising one or more hardware specifications and application criteria; determining a computing device from the plurality of pre-imaged computing devices based at least in part on the one or more hardware specifications and the plurality of data objects; generating a custom build instruction identifying the application criteria; and transmitting the custom build instruction to the computing device.

The invention discloses a method and equipment for generating a migration operator based on a heterogeneous architecture, and a medium, and relates to the technical field of artificial intelligence. The method comprises the following steps: obtaining operator target characteristics of a source end operator, and retrieving target end similar operators in an operator index database according to the operator target characteristics; according to the target end similar operator, the source end reference code and a hardware specification database, semantic migration and architecture adaptation are carried out, and a to-be-processed code is obtained; after the to-be-processed code is compiled, an optimization parameter space is determined according to the target end hardware parameters, and a plurality of operator variants are generated according to a Bayesian optimization algorithm, the to-be-processed code and the optimization parameter space; screening out a target operator from the plurality of operator variants; wherein the target end is a target processor, and the target operator runs in the target processor to execute the target calculation task. According to the technical scheme provided by the embodiment of the invention, the high-performance operator conforming to the target end architecture constraint can be automatically generated, and the task execution efficiency of the target end is improved.

The invention provides an order allocation method and device for a robot and a storage medium, and the method comprises the steps: querying industrial big data for industrial robots under a plurality of heterogeneous platforms when a new transportation order is received; calculating the transportation load rate of the industrial robot according to the undertaken transportation order; according to sensor parameters and hardware specifications, the uncertainty of faults occurring when the industrial robot executes the undertaken transportation order is analyzed; mining a bidding weight for the industrial robot according to the emergency degree, the transportation load rate and the uncertainty of the new transportation order; when the auction information is released according to the new transportation order, receiving the original bidding cost of the industrial robot for bidding; and distributing the new transportation order to the industrial robot according to the target bidding cost. According to the embodiment of the invention, the consistency among the industrial robots under the multi-heterogeneous platform is improved, and the overall performance of the industrial robots under the multi-heterogeneous platform is brought into full play.

A machine learning model can be optimized for deployment on a device based on hardware specifications of the device. An existing model is acquired and pruned to reduce hardware resource consumption of the model. The pruned model is then trained based on training data. The pruned model is also trained based on a collection of “teacher” models. Performance of the trained model is then evaluated and compared to performance requirements, which can be based on the hardware specifications of a device.

The application relates to the technical field of chip verification, in particular to a method for automatically generating a verification component of an arbiter. The method comprises the following steps: obtaining a template file of the verification component; the template file defines a parameterized verification component which is adapted to different hardware specifications of an arbiter to be tested through parameter configuration; the template file comprises codes of verification components of a plurality of preset types of arbiters, and branch execution selection is performed through condition judgment statements corresponding to the codes of the verification components of the different preset types of arbiters; obtaining a target information table; the target information table comprises information required for binding the verification component to the arbiter to be tested; generating a binding file according to the target information table; compiling the binding file, the template file of the verification component and design codes of the arbiter to be tested together to generate an executable simulation model; and the simulation model comprises the verification component bound to the arbiter to be tested. The application can improve the verification efficiency of the arbiter.

The invention relates to a computer-implemented method (100) for generating an individual artificial neural network, ANN, (10, 400), comprising the following: - loading (110): input data (11) comprising data elements (20), e.g. image, audio, sensor and / or tabular data; data to be predicted (12), which assign respective labels (30) to the data elements (20) of the input data (11); a target hardware specification (13) which specifies for which hardware configuration, for example a special FPGA chip, a maximum possible number of calculations per second, or a specific memory size, the ANN (10, 400) is to be generated; - determining (120) at least one network architecture (14), comprising: selecting / predicting (121) network parameter values (16) using the input data (11), the data to be predicted (12), and the target hardware specification (13); defining (122) the network architecture (17) using the network parameter values (16); training (130) the determined at least one network architecture (14) in order to generate a trained ANN (10, 400) using the input data (11) and the data to be predicted (12).

The application discloses a kind of generation method, equipment and medium based on migration operator under heterogeneous architecture, and is related to artificial intelligence technical field.The method comprises: obtaining the operator target feature of source end operator, and similar operator of target end is retrieved in operator index library according to operator target feature;According to the similar operator of target end, source end reference code and hardware specification database, semantic migration and architecture adaptation are carried out, and the code to be processed is obtained;After the code to be processed is compiled, the optimization parameter space is determined according to the hardware parameters of target end, and a plurality of operator variants are generated according to the bayesian optimization algorithm, the code to be processed and the optimization parameter space;Target operator is selected from a plurality of operator variants;Wherein, the target end is target processor, and the target operator runs in target processor to execute target computing task.The technical scheme of the embodiment of the application can automatically generate high-performance operator that meets the architecture constraints of target end, and improve the execution efficiency of target end task.

The invention relates to a computer-implemented method (100) for generating an individual artificial neural network, kNN, (10, 400) comprising the following: - Load (110) of: o Input data (11) comprising data elements (20), e.g. image, audio, sensor and / or tabular data; o predictable data (12) that assign labels (30) to the data elements (20) of the input data (11); o a target hardware specification (13) that specifies for which hardware configuration, e.g. a special FPGA chip, a maximum possible number of calculations per second, or a specific memory size, the kNN (10, 400) is to be generated; - Determining (120) a network architecture (14), including: o Selecting / predicting (121) network parameter values ​​(16) using the input (11), predicted data (12) and target hardware specification (13); o Defining (122) the network architecture (17) using the network parameter values ​​(16); Training (130) the specified network architecture (14) to generate a trained kNN (10, 400) using the input data (11) and the predicted data (12).

The application discloses an online generation method, device and equipment of a splitting strategy and a storage medium. The method comprises the following steps: acquiring a machine learning model currently loaded to an AI platform, and identifying a target operator in the machine learning model; determining a plurality of alternative splitting patterns matched with the target operator according to tensor dimensions of each operator parameter in the target operator and a hardware specification of the AI platform; acquiring a time cost model matched with the AI platform, and respectively evaluating time overheads of each alternative splitting pattern under at least one operation cycle mode by using the time cost model; determining a target splitting strategy obtained by combining a target splitting pattern and a target operation cycle mode according to the time overheads; and performing online calculation on the target operator according to the target splitting strategy in an execution process of the machine learning model. The technical scheme of the embodiment of the application can meet the business requirement of determining the operator splitting strategy online and instantly, and reduce the maintenance cost.