42 results about "Configurable hardware" patented technology

The invention discloses an FPGA (Field Programmable Gate Array) hardware system based on an intelligent sensing algorithm and a deployment method thereof, and relates to the technical field of intelligent video image processing, and the FPGA hardware system comprises a reconfigurable sensing module, a compatible FPGA module, an expandable external storage module and a customizable information processing module, through the technical means of a configurable hardware system scheme, a pipelined deployment process method, an extensible external storage module, a customized information processing module and the like, the efficient, flexible and extensible FPGA hardware system based on the intelligent sensing algorithm is provided. The system can meet the deployment requirements of different intelligent sensing algorithms, improves the performance and processing efficiency of the algorithms, and can be widely applied to the fields of industry, aerospace, deep space exploration and the like.

Technology for managing a distributed control system for a motor control switch is described. A request to implement a first controller for a motor control switch is received. An embodiment determines a plurality of function modules of the first controller. Each of the plurality of function modules includes an instance of computer logic configured to perform a corresponding function. A corresponding motor control function set (MCFS) for performing the corresponding function of each of the plurality of function modules is determined. One or more of a plurality of configurable hardware blocks are assigned to each of the plurality of function modules. An embodiment configures each of the plurality of configurable hardware blocks based on the MCFS of the function module to which the corresponding configurable hardware block is assigned. The configured plurality of configurable hardware blocks operate as a distributed system to control the motor control switch.

The application discloses a satellite communication baseband processing method with flexible configuration function, relates to the technical field of satellite communication, and specifically a baseband processing method process is as follows: S1, interface adaptive adaptation scheduling; S2, downlink receiving scheduling; S3, uplink sending scheduling; S4, configurable hardware acceleration scheduling.The application can greatly improve the adaptive flexibility of baseband processing and the hardware multiplexing rate by executing four-step cooperative scheduling of downlink receiving scheduling, uplink sending scheduling, configurable hardware acceleration scheduling and interface adaptive adaptation scheduling, and all signal data are uniformly stored and scheduled with the memory as the core, compared with the fixed hardware pipeline architecture in the prior art, and therefore the technical problems of the prior satellite communication baseband processing, such as the need of modifying hardware circuits when switching satellite constellations or replacing radio frequency devices, high adaptation cost and low efficiency, can be solved.

The invention discloses a method for generating a mapping relationship between an FPGA bit stream and configuration resources, which belongs to the technical field of hardware security, and comprises the following steps of: regarding the distribution of logic units of a Flash FPGA as a two-dimensional matrix, and extracting to obtain a logic unit set and a configuration set; constructing a column logic unit set, and calculating row address offset to obtain a row offset value and a row address hopping value set; constructing a row logic unit set, and calculating the column address offset to obtain a target column reference set and a target column address offset set; constructing a target column address offset subset, and calculating to obtain the length of an open interval, the size of a basic configuration block and the total number of the basic configuration blocks; and obtaining an initial address of the configuration data, and calculating to obtain a configuration resource mapping result of the logic units in combination with the total jump value of the first row of logic units. According to the invention, the problem that the accurate corresponding relation from the bit stream file to the configurable hardware resources in the FPGA is difficult to establish effectively is solved.

Systems and methods for a configurable hardware architecture for read operations of flash memories. In some embodiments, a flash memory system may include a non-volatile memory, a controller, a first processor, and a second processor. The first processor may generate a first configuration including a pointer to a first set of predefined configurations of the plurality of predefined configurations. In response to generating the first configuration, the circuitry may generate a first set of predefined configurations in the memory. The controller may perform a first operation according to a first set of predefined configurations generated in the memory. The second processor may generate a second configuration including a pointer to a second set of predefined configurations of the plurality of predefined configurations. In response to generating the second configuration, the controller may generate a second set of predefined configurations in the memory. The controller may perform a second operation according to a second set of predefined configurations generated in the memory.

The invention discloses a hardware acceleration system and method supporting a pulse-gated recurrent neural network, and relates to the technical field of neural network hardware acceleration, and the system comprises a PC terminal and an accelerator. The accelerator comprises a UART (Universal Asynchronous Receiver / Transmitter) module, a data composer, a storage module, a controller module, a calculation module and a gating calculation core, the PC terminal is connected with the UART module; the gating calculation core is connected with the data composer; and the controller module and the storage module are respectively connected with the UART module, the data composer, the calculation module and the gating calculation core. Based on the above scheme, different coding modes can be selected at a PC terminal to adapt to different data types, and a pulse neuron activation function and a logic gate are utilized to perform calculation heterogeneous design in a calculation module and a gating calculation core, so that a high-performance configurable hardware acceleration calculation architecture for the pulse gating recurrent neural network is realized.

An adaptive hardware safety disconnect system for a motorized traffic vehicle may utilize configurable hardware logic circuitry to selectively disable a traffic vehicle system, such as a high voltage contactor, an airbag, or a low voltage power supply, in a deterministic manner. The first disconnect mechanism may disable the first set of systems, while the second disconnect mechanism disables the additional system to fully power down the traffic vehicle. The system may be configured for different use cases, such as emergency response, service, and development testing, while using common hardware components.

An implantable medical device is disclosed. A housing includes a hollow body forming a first electrode on an outer surface with end caps affixed to opposite ends, one end cap forming a second electrode. A microcontroller circuit is provided and includes a microcontroller operable under program instructions stored within a non-volatile memory device. An analog front end is interfaced to the electrodes to sense electrocardiographic signals. A transceiver circuit is operable to wirelessly communicate with an external data device. The program instructions define instructions to continuously sample the electrocardiographic signals into the non-volatile memory device and to offload the non-volatile memory device to the external data device. A receiving coil and a charging circuit are operable to charge an onboard power source for the microcontroller circuit.

An adaptive hardware safety disconnect system for electric vehicles can use configurable hardware logic circuits to selectively and deterministically disable vehicle systems such as high-voltage contactors, airbags, or low-voltage current. A primary disconnect mechanism can disable an initial set of systems, while a secondary disconnect mechanism disables additional systems to completely shut down the vehicle. The system can be configured for various use cases, including emergency response, maintenance, and development testing, using common hardware components.

A system and method for updating configurable hardware components of electronic systems wherein each configurable hardware component has a discoverable common memory region that includes specific identification information for the associated hardware component. Each common memory region can be surveyed in connection with generating a survey report that can be communicated to an external hardware management system that is remote from, and / or external to, the product. Using the identification information provided by the survey report, the external hardware management system can determine customized, and compatible, updated firmware for the electronic system, thereby minimizing the amount of firmware stored on the product. A variety of security measures can be also utilized to prevent unauthorized changes to the hardware components of the system. The survey report can be compared by a controller of the electronic system to a stored hardware inventory in connection with detecting at least potential tampering with the product.

An Integrated Circuit (IC) device, and a method of utilizing thereof, may include: a plurality of Processing Elements (PEs), each comprising one or more configurable hardware logic blocks. The IC may further include a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain two or more configuration settings of the respective PE. The IC may further include a configuration manager circuit, configured to: receive a reconfiguration instruction, dictating a required function of the IC device; based on the reconfiguration instruction, identify at least one target PE of the plurality of PEs as a target for reconfiguration; based on the required function, select a specific configuration setting in the configuration memory element associated with the at least one target PE; and reconfigure at least one hardware logic block of the at least one target PE, according to the selected configuration setting.

In some embodiments, a flash memory system may include a non-volatile memory, a controller, a first processor, and a second processor. The first processor may generate a first configuration including a pointer to a first set of predefined configurations among a plurality of predefined configurations. In response to generating the first configuration, the circuit may generate, in a memory, the first set of predefined configurations. The controller may execute a first operation according to the first set of predefined configurations generated in the memory. The second processor may generate a second configuration comprising a pointer to a second set of predefined configurations among the plurality of predefined configurations. In response to generating the second configuration, the controller may generate, in the memory, the second set of predefined configurations. The controller may execute a second operation according to the second set of predefined configurations generated in the memory.

Software tools, tools flows and software infrastructure to extract content and execute extracted content in hardware (termed content-computing) from a high-level language description of an application software program is disclosed. A software program for content-computing comprises: a high-level logic synthesis software to convert an identified content in an application program to a synthesized hardware image; and a language compiler software to instantiate the content customized instruction to execute in a configurable hardware unit programmed to the synthesized hardware image. A software tools flow to generate executable instructions in an application software program comprises a combined high level logic synthesis software and language compiler software to: identify an application software program content that is targeted for hardware implementation as a hardware function in a configurable hardware unit that comprises configuration memory; generate a synthesized gate-level netlist of the targeted hardware function; generate a bit-stream of configuration memory to program the targeted hardware function in the configurable hardware unit; and generate a compiled hardware instruction for a processor unit to execute the instruction in the configured hardware function.

User configurable hardware settings for overclocking are described. In accordance with the described techniques, a user input is received to adjust a hardware setting for operating a processing unit in an overclocked mode. The user input adjusts, for example, at least one of a voltage droop threshold or a frequency adjustment of a clock rate. A voltage droop is detected while operating the processing unit in the overclocked mode. In response to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware setting.

The invention discloses a high-performance and configurable Diithium hardware coprocessor. According to the optimal design of an arithmetic unit, the arithmetic unit comprises the following structures: a modular multiplication high parallel NTT structure, a reconfigurable SHA-3 unit supporting SHAKE-128 and SHAKE-256, a multi-channel sampler and a data storage unit. Compared with the prior art, the method has the advantages that the implementation scheme of the design carries out optimization design on arithmetic unit optimization, hardware overhead is lower, performance is improved while resource consumption is kept, and area efficiency is high.

Monitor and control the incoming and outgoing communication of a hardware-application component (HAG) during its operation. In this way, a firewall (NBF, SBF) is provided to ensure the secure and unchanged operation of a hardware-application (HA) that executes security-critical functions on a field-programmable gate array (CHM). The hardware-application component can interact directly and / or via an on-chip bus with other components. Monitoring the incoming and / or outgoing communication is particularly advantageous when using third-party hardware-applications or software-applications (i.e., applications developed by untrusted parties). Another advantage is the possibility of monitoring and controlling all communication between a hardware-application, between a hardware-application and a software-application, between a hardware-application and a peripheral device (PD), an IO controller, etc. This is particularly beneficial in cases where the hardware-application is compromised and attempts to compromise the rest of the embedded device (ED), or where a damaged software-application attempts to compromise the associated hardware-application during runtime.

A neural network accelerator that has a configurable hardware pipeline includes a plurality of hardware processing units, each hardware processing unit comprising hardware to accelerate performing one or more neural network operations on a tensor of data; and a crossbar coupled to each hardware processing unit of the plurality of hardware processing units, the crossbar configured to selectively form, from a plurality of selectable pipelines, a pipeline from one or more of the hardware processing units of the plurality of hardware processing units to process input data to the neural network accelerator. At least one of the hardware processing units is configurable to transmit or receive a tensor via the crossbar in a selected processing order of a plurality of selectable processing orders, and the selected processing order is based on the pipeline formed by the crossbar.

Various embodiments described herein dynamically control circuitry in a tensor processing unit (TPU) to efficiently cause arithmetic logic units (ALUs) to perform artificial intelligence (AI)-based operations, such as those involving matrix-matrix operations. Circuitry in the TPU is controlled based on a determination that ALUs are arranged to perform certain dot product operations over a plurality of clock cycles and that a subset of ALUs do not perform a dot product operation during a first clock cycle of the plurality of clock cycles. Controlling the circuitry in the TPU causes the TPU to repurpose the ALUs to cause at least a portion of the subset of ALUs to perform, during the first clock cycle, at least one dot product operation of the plurality of dot product operations. In this manner, more neural network operations can be performed per clock cycle, thereby improving computational efficiency, speed, and throughput using TPUs.

Responsive to detection of a personal device, a closest one of a plurality of HMIs to the personal device is identified. Responsive to an address store including a hardware address of the personal device, the configurable hardware address of the closest one of the plurality of HMIs is updated to be a HMI hardware address mapped to the personal device hardware address. The personal device is then able to reconnect to the closest one of the plurality of HMIs.

Incoming and outgoing communication of a hardware-application component is monitored and controlled at runtime of the hardware-application component. In this way, a kind of firewall is provided for ensuring secure and un-altered operation of a hardware-application performing security-critical functionalities on a field-programmable gate array. The hardware-application component may interact with other components directly and / or via an on-chip bus. The monitoring of incoming and / or outgoing communication is particularly advantageous when using third party hardware-applications or software applications, i.e., applications developed by untrusted parties. Another advantage is the possibility of monitoring and controlling all the communication between hardware-applications, hardware- and software applications, hardware-applications and peripherals, IO controllers, etc. It is beneficial especially in case a hardware-application is compromised and tries to compromise the rest of the embedded device, or in case a corrupted software application tries to compromise the associated hardware-application at runtime.

The invention discloses a power distribution Internet of Things DTU micro-application cooperative processing device based on container isolation, and relates to the technical field of power distribution automation. The device comprises a hardware platform and a software platform; the hardware platform adopts a blade type configurable architecture and comprises a base module, an acquisition module and a calculation module, and all the modules realize plug and play through a uniform interface; according to the software platform, based on the container technology, control-related services and non-control-related services are deployed in different containers respectively, logic isolation is achieved, parallel operation of at least six containers is supported, and a plurality of micro-application modules can be deployed in a single container; through combination of a blade type configurable hardware architecture and a containerized software platform, the efficient cooperative processing capability of the DTU device of the power distribution Internet of Things is realized, the hardware platform adopts a plug-and-play design of a base, an acquisition module and a calculation module, rapid deployment and dynamic expansion are supported, and the field maintenance cost is reduced.

Various embodiments described herein dynamically control circuitry in a tensor processing unit (TPU) to efficiently cause arithmetic logic units (ALUs) to perform artificial intelligence (AI)-based operations, such as those involving matrix-matrix operations. Circuitry in the TPU is controlled based on a determination that ALUs are arranged to perform certain dot product operations over a plurality of clock cycles and that a subset of ALUs do not perform a dot product operation during a first clock cycle of the plurality of clock cycles. Controlling the circuitry in the TPU causes the TPU to repurpose the ALUs to cause at least a portion of the subset of ALUs to perform, during the first clock cycle, at least one dot product operation of the plurality of dot product operations. In this manner, more neural network operations can be performed per clock cycle, thereby improving computational efficiency, speed, and throughput using TPUs.

The invention discloses a unified airborne network short message receiving system and method based on an annular virtual queue. The system comprises a management register set, a receiving management unit, a shunt controller, a receiving buffer area and the annular virtual queue. The plurality of annular virtual queues and the management register group are connected to a receiving management unit, and the receiving management unit is connected to a plurality of receiving buffer areas through a shunt controller; the general receiving management work of the event message, the emergency message and the sampling message is realized based on the annular virtual queue and a configurable hardware mode. According to the method, efficient storage management based on the annular virtual queue is high in generalization and adaptability, software interfaces are unified, resources can be dynamically optimized, and universal receiving management of different types of messages can be met.

The invention discloses an edge hardware high-energy-efficiency hybrid floating point neural network reasoning acceleration method and device, and the method comprises the steps: generating a DAG matrix for calculating and transmitting a load through analyzing the structure of a to-be-processed DNN model; a configurable hardware accelerator circuit is generated by configuring a target edge platform mixed precision pipeline floating point arithmetic unit template, meanwhile, hardware feature parameters are extracted, and hardware parameters for hardware deployment modeling are provided; joint optimization of hardware perception is carried out based on a deep reinforcement learning strategy gradient algorithm; and generating a multi-target deployment scheme oriented to the energy efficiency delay product, the operation speed or the power consumption according to the optimized operation unit configuration parameters, the cache strategy and the data flow scheduling scheme. According to the method, the technical problems of low hardware resource utilization efficiency, single optimization target and high manual tuning dependency degree in hybrid precision DNN deployment in the prior art are solved, and the technical effect of automatically generating a high-energy-efficiency complex DNN deployment scheme on a resource limited edge platform is achieved.

The invention belongs to the technical field of software radio systems, and particularly relates to a configurable MOCB hardware abstraction layer packaging design method. The MOCB hardware comprises three types, namely a general purpose processor GPP, a digital signal processor DSP and a programmable logic gate array FPGA; each hardware can generate events to other hardware; each piece of hardware accesses the FPGA by generating an address access signal, wherein the address access signal is a signal which contains a specified memory address and an access mode and is used for describing operation on address pointing memory content; each hardware can access the shared memory of the DSP and the GPP; each piece of hardware is provided with an MOCB layer and a bus adaptation layer; the MOCB layer is used for logic mapping management and interaction time sequence control; and the bus adaptation layer is used for realizing a read-write interface of a memory and receiving and sending of events, and providing a local operable address for a bus with a local mapping requirement.

The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

This invention provides a configurable hardware architecture and bit manipulation method based on Banyan networks, belonging to the fields of digital logic circuits and high-performance computing technology. The invention aims to solve the problems of high hardware overhead, high power consumption, and long latency caused by the need for separate hardware modules—a Banyan network and a barrel shifter—to achieve combined bit-gathering and cyclic shifting operations in existing technologies. The architecture of this invention includes a Banyan network switching module and a control signal generation module. The control signal generation module generates an offset prefix count by superimposing the cyclic shift amount *r* with the original prefix count based on a bit mask, and uses this count to generate control signals for each stage of the Banyan network via an LROTC circuit. Through innovative modifications to the Banyan network control logic, this invention enables a single network to simultaneously perform both advanced bit operations, bit-gathering and cyclic shifting. This invention offers significant advantages such as hardware resource savings, reduced power consumption, improved performance, flexible design, and easy expansion, and can be widely applied in processor design, cryptographic acceleration, digital signal processing, and other fields.

The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.