141 results about "Decimation" patented technology

The invention relates to a method for constructing a fully-digital GNSS compatible navigation receiver, which comprises four steps: I, constructing a receiving link in accordance with actual needs by taking the characteristics of satellite signals, performance indexes and current device level into comprehensive consideration; II, choosing a proper A/D chip and a proper time clock source to complete direct radio frequency sampling and constructing a sampling rate in accordance with bandwidth sampling requirements; III, constructing a filter decimation network to reduce the sampling rate, completing the down-conversion of the radio frequency, converting the frequency of the bandwidth satellite navigation signals near 1.2G and 1.5G two frequency points down to a low medium frequency under a condition of a high sampling rate, and finally outputting a sampling time clock and a GNSS medium frequency signal; and IV, constructing digital radio frequency front end and rear end medium frequencyreceiver interfaces for making the receiver compatible with other medium frequency receiver. The thought of using software radio realizes the collective receiving of full-range GNSS satellite navigation signals; and the medium frequency receivers can complete navigation solution and output measurement values, so multi-system and multi-frequency point compatible navigation is realized. The method has an application and development prospect in the technical field of communication.

A programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in either interpolation mode or decimation mode and of switching between those modes at run time. The FIR filter structure can be mapped onto a specialized processing block of the programmable logic device that includes multipliers and adders for adding the products of the multipliers. The FIR filter structure minimizes the number of multipliers used by reusing various calculations that are repeated as a result of the interpolation or decimation operation, using multiplexers or other run-time-controllable selectors to select which current or stored multiplier outputs to use.

A continuous-time sigma-delta analog-to-digital converter (CV) comprises i) a signal path (SP) comprising at least one combiner (C1) for combining analog signals to convert with feedback analog signals, at least two integrators (H1, H5), mounted in series, to integrate the combined analog signals, a quantizer (Q) for converting the integrated signals into digital signals, and a decimation filter (DF) for filtering digital signals, and ii) a feedback path (FP) comprising at least a digital-to-analog converter (DAC) for converting the digital signals output by the quantizer (Q) into feedback analog signals intended for the combiner (C1). Each integrator (H1, H5) comprises variable capacitance means arranged to be set in chosen states define by the values of a digital word, to present chosen capacitances. The converter (CV) also comprises a self-calibration control means (CCM) arranged a) to generate a digital word with a chosen first value, b) to estimate an in-band noise IBN(n) from the filtered digital signals and to compare this IBN(n) to the preceding IBN(n-1), c) to modify the digital word value to decrease the capacitance of each integrator from a chosen decrement when IBN(n) is smaller than IBN(n-1), d) to iterate steps b) and c) till IBN(n) be greater than IBN(n-1), and to choose as calibration digital word value the value corresponding to IBN(n-1) to set the calibration state of the variable capacitance means.

The invention relates to a method for implementing a multistage FIR filter in the field of an integrated circuit. The method for implementing the multistage FIR filter relates to an arithmetic unit, a control unit and a software environment for conducting programming configuration on the control unit. The arithmetic unit comprises a pretreatment unit, an ALU and a storage unit RAM, a transfer function of the filter is calculated through time division multiplexing, the mode that data in the RAM are flexibly read by changing addresses is adopted, and therefore a large quantity of data transfer power consumption in a typical filter implementation method is saved. The control unit comprises a storage unit ROM and a plurality of counters and summing units, commands and coefficients in the transfer function of the filter are provided for the arithmetic unit, therefore, filtering arithmetic of the arithmetic unit is finished in specific control step-by-step numbers, and a filtering result is acquired. The software environment conducts the programming configuration on the control unit according to performance parameters of the filter, and therefore a custom-made FIR filter suitable for application requirements is acquired. The method for implementing the multistage FIR filter can be mainly used for achieving a multistage FIR decimation filter, a multistage FIR interpolation filter and a multistage FIR same-speed filter, the function that the area can reach the minimum level of documents which have been published internationally can be achieved, and the method for implementing the multistage FIR filter has the advantages of greatly reducing the power consumption and customizing products according to the application requirements.

The invention relates to the field of radar engineering and a radar system of intermediate frequency coherent, in particular to an FPGA (field programmable gate array) based digital intermediate frequency coherent marine radar receiving and processing system. The system comprises an intermediate frequency amplifier module connected with the output end of a receiver radio-frequency front-end, and is characterized by further comprising an A/D (analog/digital) sampling chip and an under-digital frequency conversion module, the under-digital frequency conversion module comprises digital-controlled oscillator, a low-pass filter and a digital decimation filter which are based on FPGA and are arranged in sequence; intermediate frequency power signals outputted by the receiver radio-frequency front-end are converted into voltage signals via the intermediate frequency amplifier module and then transmitted to the A/D sampling chip, and the voltage signals are acquired and transmitted to the under-digital frequency conversion module. The system is simple in structure and high in flexibility, image-frequency rejection ratio of I/Q signals is increased as compared with I/Q baseband signals respectively acquired with a simulation conversion method, and the system has the advantages of low drift, low distortion and the like, and useful information in return signals can be extracted to the greatest extent to be used for subsequent radar signal processing operations.

The invention discloses a fruit three-dimensional digitization method based on point cloud, which comprises the following steps: 1) acquiring fruit point cloud data by using a portable laser three-dimensional scanner; 2) adopting non-local classification, interactive threshold denoising and decimation; 3) Using point-octree, MLS fitting to simplify the fruit point model; 4) extracting fruit slicesof that point cloud model through PCA attribute calculation and recursive increment of geometrical similarity; 5) Registering fruit point cloud models by oriented-splat team registration and hierarchical global registration;; 6) performing texture synthesis of fruit point cloud based on texton sub-sampling weighted template. This method reconstructs the real fruits in the growing process, and proposes some methods and algorithms such as denoising, extraction, registration and direct texture synthesis, which make up for the shortcomings of rough effect, low coding efficiency and large storagespace of direct texture synthesis on the current point model.

A stereo composite signal including a pilot signal is demodulated by processing input samples to obtain internal samples having variable sampling timings, synchronizing these sampling timings with the pilot signal, and digitally processing the internal samples to obtain stereo audio data. The internal samples may be obtained from the input samples by decimation or interpolation. Since the sampling frequency and sampling timing of the input samples do not have to be precisely controlled, no voltage-controlled oscillator is needed, and the demodulator can easily be incorporated into a monolithic integrated circuit.

The disclosure concerns a data acquisition apparatus and method. According to the disclosure,

• • a first means providing a series of first digital sampled data (X) at an imperfect sampling frequency (F_E) provided by a local clock (2) comprises sigma-delta modulation means (3) arranged to produce said series of first digital sigma-delta modulated data (X),
  • a second gauging means (50) for measuring the frequency error of the local clock (2) in view of a reference clock (6),
  • a third means for correcting the first data based at least on the measured frequency error, which comprises at least an interpolation means (4) to produce second digital data (Y) based on at least an interpolation of said first series (X) and compensating the measured frequency error (FD), and at least a decimation filter (7) for producing third digital data (A) based on said second digital data (Y),
  • are provided.

A decimation filtering apparatus using interpolated second order polynomials compensates for a droop caused by a CIC (Cascaded Integrator-Comb) filter (51). The decimation filter includes a CIC decimation filter (51) for decimation filtering the sampling signal to downconvert a sampling signal; an ISOP filter (53) for monotonically increasing an output of the CIC decimation filter (51) to compensate for a passband droop caused by the CIC decimation filter (51); a multistage halfband filter (55) including at least one modified halfband filter for 1/2 decimating a signal output from the ISOP filter (53), the multistage halfband filter (55) decimating the signal output from the ISOP filter (53) to downconvert the signal; and a programmable FIR (Finite Impulse Response) filter (57) for compensating for a passband droop of a signal output from the multistage halfband filter (55).

The invention relates to the field of radar against active jamming and particularly relates to a cascade digital filter anti-communication jamming method based on P band radio frequency sampling. Direct bandpass sampling digitalization is carried out on radio frequency echo signals received by the radar through an ADC chip, the sampled digital signals are subjected to digital down conversion, after digital mixing and multilevel decimation filter, needed baseband signals are obtained, and besides, spectrum aliasing is not introduced, high performance digital filter out-of-band rejection abilityis achieved, communication jamming outside an operating frequency point can be filtered out, and requirements of target detection display are met. Same frequency band communication jamming by radar sidelobe entering can be effectively restrained, the radar against jamming ability is enhanced, and a detected and extracted picture is improved.

A digital signal processor receives samples of a first digital signal which is to be decimated and samples of a second digital signal which is to be interpolated. A digital signal processing engine performs a decimation function on samples of the first digital signal and an interpolation function on samples of the second digital signal on a time-shared basis. The digital signal processor has a first dual memory space for storing the samples of the first digital signal and a second dual memory space for storing the samples of the second digital signal. Outputs retrieved from a dual memory space are pre-added and applied to a multiplication and accumulation stage which operates on the pre-added outputs and a filter coefficient of a digital filter.

Method and apparatus using at least one process to reduce a data set using a data adaptive down-sampling scheme comprising a plurality of non-uniform down-sampling factors. The method may include separating the data set into a plurality of data windows, where each of the plurality of data windows corresponds to one of the plurality of non-uniform data-sampling factors; applying the down-sampling factors, and transmitting the reduced data set from a downhole location to the surface. The data set may include an NMR echo train. The apparatus may include an NMR tool configured to acquire NMR data and at least one processor configured to perform the method.

The spectrum analyzer includes an input (115) adapted to receive an input signal and a mixer (30), coupled to the input. The mixer is adapted to produce a down converted signal from the input signal. The spectrum analyzer further includes an adjustable decimation circuit (112), coupled to the mixer, that selectively decimates the down converted signal, a decoder (108), coupled to the mixer, that selectively controls the frequency of the down converted signals from the mixer to measure power over a frequency spectrum of the input signal.

The invention discloses a two-stage threshold constant false alarm detection algorithm under strong ground clutters. Radar receiving echoes are subjected to down-conversion, decimation filtering, pulse compression and phase-coherent accumulation to form distance-Doppler two-dimensional data; and a two-stage threshold deletion average CFAR detection algorithm is adopted to determine the position ofthe target in the two-dimensional data, namely distance and Doppler information. Aiming at the problems of the ground reconnaissance radar CFAR detection technology, a two-stage threshold deletion average CFAR detection algorithm is designed, the discovery probability is improved, the false alarm probability is reduced, the calculation time is shortened, and the real-time requirement of a radar system is met.

A neural network device includes a decimation unit configured to convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal on the basis of a predetermined threshold value to generate a decimation signal a modulation unit configured to modulate a discrete value of the decimation signal generated by the decimation unit to generate a modulation signal indicating the discrete value of the decimation signal, and a weighting unit including a neuromorphic element configured to output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal generated by the modulation unit by a weight according to a value of a variable characteristic.

The invention discloses an MIL (Military)_STD(Standard)_1553 bus analysis and triggering method, which comprises the following steps: S1) setting a level generated when a bus is under an idle state as an intermediate level; S2) under the cooperation of a sampling clock, carrying out decimation processing on a bus signal subjected to analog-digital conversion by a decimation module; S3) independently comparing a snapshot signal with a high trigger threshold value signal greater than the intermediate level and a low trigger threshold value signal smaller than the intermediate level to independently obtain a signal H and a signal L (the same below); S4) carrying out positive phase or negative phase extraction on the signal H and the signal L; S5) detecting an initial condition of frame data; S6) extracting a frame synchronization segment through a frame synchronization segment extraction module to obtain the frame synchronization segment; S7) identifying the frame synchronization segment by a state machine, and determining the type of the frame data; S8) extracting a frame field via a frame field extraction module; and S9) identifying the frame data by a comparison triggering module according to the state machine to generate a trigger signal, wherein the trigger signal is stored to an acquisition control module for calling.

The present invention discloses a digital decimation filter, a filtering method and an analog-to-digital converter, the digital decimation filter comprising: a first integrator for integrating an input signal on the basis of a first sampling clock signal to obtain a first signal; a second integrator which is used for integrating the first signal based on the first sampling clock signal to obtain asecond signal; a first temporary memory which is used for storing the first signal based on the second sampling clock signal to obtain a third signal; a second temporary memory which is used for storing the second signal based on the second sampling clock signal to obtain a fourth signal; and an arithmetic unit which is used for operating the second signal, the third signal and the fourth signalbased on a second sampling clock signal to obtain a fifth signal as the output of the digital decimation filter, wherein the period of the second sampling clock signal is 1/N of the period of the first sampling clock signal, and N is a positive integer. The digital decimation filter has fewer registers while realizing digital decimation filtering.

The invention relates to an intra-pulse modulation type parameter extraction system and a use method, and belongs to the technical field of radar signal parameter calibration, and the system comprises a digital channelization module, an instantaneous frequency measurement module, an intra-pulse modulation type parameter extraction module and a radiation source information module; the intra-pulse modulation type parameter extraction system is based on a joint algorithm of digital channelization and instantaneous frequency measurement, the number of channels is D, a digital channelization module comprises D-time decimation filtering and over-threshold detection, and an instantaneous frequency measurement module comprises instantaneous frequency measurement, basic parameter measurement and PDW. Signals output after intermediate frequency data are subjected to D-time decimation filtering are subjected to over-threshold detection screening to obtain a frequency range of the signals, instantaneous frequency measurement is performed in the instantaneous frequency measurement module to obtain an accurate frequency value, basic parameter measurement is performed to obtain arrival time, arrival angle, amplitude and pulse width parameters, and complete pulse description word output is formed through encoding; therefore, the problems of high signal-to-noise ratio, high measurement precision and large operand required in the prior art are solved.

A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.