67 results about "Decimation" patented technology

The invention relates to the technical field of digital demodulation, in particular to a digital demodulation method suitable for deep ultraviolet light communication, which comprises the following steps of: adopting multiple delay processing with half code element width, and respectively carrying out double extraction processing on a discrete sampling signal which is not subjected to delay processing and a plurality of delay sampling signals to obtain a plurality of delay extraction signals; in this way, the key sampling time in the coverage code element period can be ensured, and a basis is provided for subsequent accurate synchronization; a plurality of delay extraction signals are respectively input into corresponding equalization processing units, a preset local training sequence is loaded to each equalization processing unit to obtain a plurality of equalization filtering signals, and the plurality of equalization filtering signals and the preset local training sequence are respectively subjected to related judgment processing, so that the inter-symbol interference is inhibited, and meanwhile, the equalization processing efficiency is improved. The synchronization signal can be quickly screened out, so that the problem that inter-symbol interference and synchronization are difficult to consider in a traditional demodulation method is solved, and the demodulation efficiency and reliability are remarkably improved.

The invention relates to the technical field of broadband signal synthesis and high-speed digital-to-analog conversion, in particular to an oversampling-based real-time frequency interleaving digital-to-analog conversion system aliasing suppression method and system, and aims to solve the problem of spectrum aliasing caused by non-ideal characteristics of a digital sub-band decomposition filter and an analog filter under a real-time architecture of the system. In the invention, the sub-band decomposition is completed by adopting the linear phase complementary filter bank, so that distortion introduced by a transition band of a digital filter is avoided; by restraining system parameters such as passband and stopband frequencies and local oscillation frequency of a sub-band decomposition filter, a protection band is set by an oversampling mechanism, a frequency margin is reserved for a transition band of the filter, and aliasing components are suppressed. According to the method, extraction aliasing of a digital domain and mirror image aliasing of an analog domain are avoided at the same time from the system architecture, the frequency spectrum purity of output signals is improved, the method is suitable for a real-time system for processing continuous data streams, and technical support is provided for achieving a high-performance broadband signal source.

This video encoding device includes: a decimation means for decimating pictures in a video; an encoding means for encoding a video signal resulting from the decimation of the pictures; and an auxiliary information generation means for generating auxiliary information for deriving a maximum latency picture quantity.

The invention discloses an ADC50Hz or 60Hz noise filtering method based on a software algorithm, and the method comprises the steps: carrying out the initialization configuration, and collecting original data; preprocessing and acquiring detection data; an improved Goertzel algorithm is used to acquire frequency spectrum parameters; calculating a three-level extraction factor, and sampling the data output by the ADC to obtain sample data; after forward and reverse compensation is carried out on the sample data, pulse noise suppression of a two-dimensional window is carried out on pulse noise; calculating a transmission quality index, and adjusting the size of a filtering window according to the transmission quality index; and carrying out amplitude calibration on the filtering result by using an improved comb algorithm, and outputting a standard signal after noise reduction processing. On one hand, the noise reduction processing scheme does not need to additionally add a filter circuit, so that the circuit size and the hardware cost are reduced; and on the other hand, the parameters in the method can be adaptively adjusted according to the frequency spectrum parameters, so that the adaptability is improved.

Techniques are provided for reduced latency look-ahead for signal detection. An example methodology implementing the techniques according to an embodiment includes down converting a digitized signal to a first baseband signal at a first decimation rate such that the first baseband signal is provided at a first latency with a first signal to noise ratio (SNR) based on the first decimation rate. The method also includes down converting the digitized signal to a second baseband signal at a second decimation rate, greater than the first decimation rate, such that the second baseband signal is provided at a second latency with a second SNR based on the second decimation rate, the second latency greater than the first latency and the second SNR greater than the first SNR. The method continues with generating a detection threshold based on the first baseband signal prior to completion of the second baseband signal generation.

A procedure for overcurrent shutdown is proposed, comprising the following steps: - Capturing and providing a current value as an analog output signal; - a conversion of the analog output signal by means of an analog-to-digital converter, which converts the analog output signal by means of sigma-delta modulation and provides it as a bitstream, characterized in that - the bitstream is converted using a first decimation filter and provided as a first data stream; and - Evaluating the first data stream, wherein a threshold value for a current is compared with the current value from the first data stream, and if at least one threshold value is exceeded, the overcurrent shutdown is triggered by means of a shutdown signal, wherein the shutdown signal is transmitted to at least one signal output and is used for opening a power switch. Furthermore, the invention relates to a device.

The application discloses a spectrum analyzer-based amplitude compensation method and device. The method comprises the following steps: before frequency sweeping starts, determining the starting frequency, stopping frequency and calibration frequency step of the current scanning frequency range, and determining the corresponding shift bit number according to the calibration frequency step, wherein the calibration frequency step is a power of 2; generating calibration data of a plurality of calibration points according to the starting frequency, stopping frequency and calibration frequency step, and storing the calibration data in a storage space accessible by an FPGA in the order of corresponding frequencies; obtaining the frequency value corresponding to the current data during frequency sweeping, and determining the calibration data index according to the frequency value corresponding to the current data and the calibration frequency step according to the upward rounding rule; reading the corresponding calibration data according to the calibration data index; and performing amplitude compensation on the current data by using the calibration data after digital down-conversion and before decimation filtering. The method can reduce the calibration data storage amount and FPGA operation resource consumption, and improve the real-time amplitude compensation accuracy during frequency sweeping of the spectrum analyzer.

This invention provides a broadband signal analyzer, comprising: at least one superheterodyne frequency conversion receiving unit, at least one filtering unit, an ADC, a digital down-conversion and decimation filtering unit, an adaptive filtering unit, a data processing and display unit, and a scan controller, connected in sequence; the superheterodyne frequency conversion receiving unit includes: an attenuator, a mixer, and a local oscillator signal, the attenuator, mixer, and filtering unit being connected in sequence, the output terminal of the local oscillator signal being connected to the input terminal of the mixer, the input terminal of the local oscillator signal being connected to the output terminal of the scan controller, and the input terminal of the scan controller being connected to the output terminal of the ADC. This invention overcomes the problems of high filter order and excessive processing resource consumption caused by existing broadband signal in-band flatness compensation methods.

Three-dimensional sensing data is transferred efficiently by applying compressed sensing using dictionary learning. Conventional image-based lossy compression improves a feature according to which power is concentrated on low-frequency components and deterioration of three-dimensional information increases. By changing the decimation rates for the depth information and the color information and using a dictionary vector created from the other restoration result for restoration, the original result is reconstructed using a small data volume.

The application discloses a power frequency suppression filter suitable for a Sigma-delta ADC, comprising SINC1 filters SINC1_1-SINC1_6, FIR filters F1 and F2, decimation modules M1-M6, data selectors MUX1 and MUX2, mean filters MF1 and MF2; the power frequency suppression filter circuit suitable for the Sigma-delta ADC can simultaneously suppress 50Hz and 60Hz power frequency interference; the application adopts a multistage SINC1 filter and a FIR cascade structure, and can complete power frequency suppression under a set output sampling frequency; the application adopts a SINC1 filter multiplexing structure, reduces circuit area and power consumption; the application adopts a FIR filter multiplexing structure, maximally reduces multiplier use resources, and optimizes circuit area and power consumption.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The application discloses a low-resource-overhead super-high-speed modulation and demodulation method. In view of the signal processing demand faced by high-frequency bands and large bandwidths in millimeter wave and terahertz communication, the application adopts a parallel architecture to meet the high-speed signal processing demand and correct non-ideal characteristics of a channel; and adopts a fusion processing method to fuse interpolation, anti-aliasing, timing interpolation, matched filtering, time domain equalization and decimation into a multi-phase filter, so that the signal overhead caused by high-speed demodulation is greatly reduced. The application can be applied to a millimeter wave / terahertz super-high-speed transmission system, and provides low-complexity super-high-speed modulation and demodulation to meet the performance and resource demand of super-high-speed transmission.

Techniques for number theoretic transform (NTT) and inverse number theoretic transform (iNTT) are described. In some examples, an NTT circuit is to use a decimation-in-frequency (DIF) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order. In some examples, an iNTT circuit is to use a decimation-in-time (DIT) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order.

The application discloses a signal processing system of FPGA high sampling rate signal, comprising: a multi-phase local oscillator generation module configured to generate a plurality of high sampling rate local oscillator signals; a plurality of complex mixing modules corresponding to the plurality of high sampling rate local oscillator signals; the complex mixing module is configured to receive the corresponding high sampling rate local oscillator signal and the high sampling rate signal, and to complexly mix the corresponding high sampling rate local oscillator signal and the high sampling rate signal to obtain a plurality of intermediate frequency signals; a filtering and decimation module configured to receive the plurality of intermediate frequency signals and to filter and decimate the intermediate frequency signals to obtain a low sampling rate signal. The signal processing of the high sampling rate signal is completed, and finally the low sampling rate signal capable of being directly processed by the FPGA is obtained. The multiplexing of the multi-phase local oscillator generation module greatly saves the logic resources of the FPGA, and the phase control mode is more flexible and has higher applicability.

This invention provides a reference-free background calibration method for ultra-high-speed TIADCs based on minimum mean square (RMS) calibration. It employs a decimation-calibration-interpolation calibration mode. The original quantized data is decimated using a specific decimation rate to obtain multiple quantization code sets. A step-by-step grouping calibration algorithm is used based on the number of interleaved channels, selecting the first quantization code set for step-by-step calibration. Each step involves grouping the data and using a dual-channel synchronous detection method based on a binary search to search for the clock jitter value of each channel in the grouped quantized data. Other quantization code sets are then compensated using a first-order Taylor approximation in the digital domain based on the clock jitter value of the first quantization code set. Finally, the compensated multiple quantization code sets are re-interpolated to obtain the calibrated result of the original data. This invention eliminates the need for a reference channel, minimizing the RMS of the detected clock jitter value and thus improving compensation accuracy.

The application relates to a symmetric coefficient polyphase decimation filter design method, and belongs to the technical field of signal processing. The method can be used for high-speed signal sampling and down-conversion filtering processing. The method comprises the following steps: configuring a basic operation unit; arranging an operation unit matrix; inputting a signal delay; connecting input data; setting a filter coefficient; and outputting a result. The method adopts symmetric filter coefficients, and can effectively reduce hardware multiplier resource consumption. The method process is simple and convenient to operate, and half of the multiplier resources can be reduced by utilizing the coefficient symmetry.

The application discloses a FIR filter applied to a digital decimation filter, and a digital decimation filter in a cascade form can realize higher order. By using a down-sampling module of pure combination logic circuit, timing problems can be avoided, and the workload of the back end can be reduced; meanwhile, a time division multiplexing form of a multiplier is realized by using a storage RAM and a ROM, so that the multiplier module in the circuit is reduced, the area required by multiplication operation is reduced, and a CSD multiplier is formed by using CSD coding for each multiplier, so that the number of '1' in the multiplier in the multiplication operation is reduced, and operation consumption is further reduced and operation speed is accelerated.

A multi-stage digital down converter (DDC) 600a comprising a series of receiving stages 602a - 602n each having a decimation filter 504a - 504n that has a corresponding decimation ratio to progressive

This invention discloses a long-delay channel simulation method under hardware resource constraints. The channel simulation method includes a signal input / output module, a decimation filter module, a delay simulation module, and an interpolation filter module. The input signal of the signal input / output module is processed by the decimation filter module, the delay simulation module, and the interpolation filter module before outputting the signal. The decimation filter module is used to filter and fractionally sample the signal. The delay simulation module is used to simulate large delays. The interpolation filter module is used to fractionally interpolate the delayed signal. This invention's long-delay channel simulation method uses a decimation filter to decimate the input signal, uses the decimated output signal as the input to the delay system for large-delay simulation, and then inputs the delayed signal into an interpolation filter to improve its accuracy before outputting the signal. This ensures the accuracy of the delayed signal while reducing the complexity of the delay system.

The application provides a method and device for arbitrary sampling rate conversion of a communication receiver, comprising: performing down-rounding operation according to a sampling frequency of a sampling signal and a sampling frequency of the sampling signal required by a signal processor to determine an integral result; performing integral times down-sampling on the sampling signal according to the integral result to obtain a sampling result corresponding to the integral times down-sampling; performing curve fitting based on the sampling result corresponding to the integral times down-sampling to obtain a continuous signal; calculating a sampling time interval after decimal times decimation according to the sampling frequency of the sampling signal required by the signal processor; and performing decimal times decimation on the continuous signal based on the sampling time interval after the decimal times decimation to complete the arbitrary sampling rate conversion. The application has good decimation effect on any decimal times sampling frequency, has wide application range, and is more suitable for practical application.

Circuits and methods for computing an order N polynomial include V decimation stages, each stage including respective multiply-and-accumulate circuitry. The multiply-and-accumulate circuitry in each stage k, in response to an input r-term and a plurality of input z-terms 0 through (Nk−1), generates output z-terms 0 through (Nk / 2−1) and an output r-term as a square of the input r-term. Each output z-term i is a sum of input z-term (2i+1) of the input z-terms and a product of input z-term 2i and the input r-term. The multiply-and-accumulate circuitry in decimation stages k for k≤(V−1) provides the output r-term and one or more output z-terms from decimation stage k as the input r-term and one or more input z-terms to the respective multiply-and-accumulate circuitry of decimation stage k+1. A recursive stage inputs from decimation stage V, the output r-term as a recursive r-term and the output z-terms as a-terms, and generates a polynomial output value z by a recursive evaluation of the recursive r-term, the a-terms, and a modulus, p.

This invention discloses a method and system for calculating the ultra-fine spectrum of a sampled signal, belonging to the field of weak signal detection technology. Calculating the spectrum of signals with extremely long sampling times presents problems such as large data volume and high computer memory requirements. This method divides the sampled data sequence of an ultra-low bandwidth modulated signal into segments of equal duration. Each segment is then subjected to quadrature demodulation, filtering, and decimation concatenation. The processed segments are then sequentially concatenated, and finally, a time-frequency transformation is performed to obtain the signal spectrum with ultra-fine frequency resolution. This calculation method significantly reduces the amount of data required for time-frequency transformation, allowing the processing of massive amounts of sampled data to be completed on a conventionally configured computer, yielding signal spectra with frequency resolution at the millihertz or even microhertz level. This allows for the observation and understanding of the extremely low-frequency spectral structure or near-end phase noise of the signal. This calculation method has strong versatility.

The application discloses a kind of extraction and error correction methods for evaluating the sampling rate of pulse waveform measurement system, to sample rate f0 The output waveform of detector is sampled, and high sampling rate original waveform is obtained;According to the target sampling rate set, select multiple extraction ratios, based on different starting points, perform multiple sets of extraction operations with the same ratio on the original waveform, and expand to obtain multiple sets of waveforms with uniformly distributed sampling phases;According to the application scenario, select and calculate the evaluation parameter σ;According to the amplitude distribution estimation error caused by the correlation between waveforms during the extraction process, introduce the correction factor p To modify the evaluation parameter;The contribution ratio of the error caused by the correlation between waveforms to the evaluation parameter is further modified to the evaluation parameter σ, to realize the accurate evaluation of waveform measurement system.The method can greatly reduce the research and development cost and cycle of multi-channel readout electronics, and the uniform sampling phase can effectively avoid random error.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The invention relates to a method and an apparatus for overcurrent switch-off The method comprises the following steps: • detecting and providing a current intensity value as an analogue output signal (9); • converting the analogue output signal by means of an analogue-to-digital converter (2) which converts the analogue output signal by means of sigma-delta modulation and provides it as a bit stream (10); • the bit stream is converted by means of a first decimation filter (3) and provided as a first data stream (11); • evaluating the first data stream, wherein a threshold value for a current intensity is compared with the current intensity value from the first data stream and, if the threshold value is exceeded at least once, the overcurrent switch-off is triggered by means of a switch-off signal (21), wherein the switch-off signal is transmitted to at least one signal output (14) and used for opening a circuit breaker (7).

Methods and systems of processing audio data with a multi-stage audio front end model is provided. A one-dimensional audio waveform is received as input and processed using a multi-stage audio frontend model to convert the one-dimensional waveform into a two-dimensional matrix representing features of the audio waveform. The multi-stage learnable audio frontend model is configured to apply a first filterbank to the audio waveform to generate a first time-frequency representation of the audio waveform; apply a first decimation filter to the audio waveform to generate a first decimated audio input; apply a second filterbank to the first decimated audio input to generate a second time-frequency representation of the audio waveform; and stack the first time-frequency representation and the second time-frequency representation together to generate the two-dimensional matrix.

The application relates to a digital Dechirp engineering implementation method, device and equipment. The method comprises the following steps: obtaining a radar echo signal, performing digital mixing on the radar echo signal and a reference signal to obtain a difference frequency signal sequence. The maximum bandwidth of the difference frequency signal sequence is used to determine a data decimation multiple of the difference frequency signal sequence, and an anti-aliasing low-pass filter is constructed by selecting an integer multiple of the data decimation multiple. The difference frequency signal sequence is segmented in layers according to the number of segments generated according to the data decimation multiple to obtain a layered segmented signal sequence. The layered segmented signal sequence is subjected to windowing recombination and FFT operation processing of the anti-aliasing low-pass filter to obtain an equivalent filtering sequence. The equivalent filtering sequence is decimated according to the order of the anti-aliasing low-pass filter and the data decimation multiple to obtain an equivalent filtering decimation sequence, and the equivalent filtering decimation sequence is recombined and subjected to FFT operation to generate a digital Dechirp processing sequence. The method can effectively reduce the hardware resource consumption of digital Dechirp in engineering implementation.

The embodiment of the invention provides a sequence processing method, electronic equipment, a storage medium and a program product. The method comprises the following steps: determining a frequency domain adaptive length, a frequency domain initial position and a time domain segmentation length corresponding to a synchronization signal block SSB; according to the frequency domain adaptive length and the frequency domain initial position corresponding to the SSB, a first frequency domain sequence corresponding to an original primary synchronization sequence PSS is generated, and the sequence length of the first frequency domain sequence is the frequency domain adaptive length; determining a second frequency domain sequence corresponding to the first frequency domain sequence based on the time domain segmentation length; and performing extraction processing on the second frequency domain sequence to obtain a target PSS corresponding to the original PSS, the target PSS being a locally stored pre-processing sequence. The method is used for achieving the effect of reducing the occupancy rate of the storage space.

The invention provides a convolution beam space DOA estimation method based on hole filling, so as to solve challenges faced by a traditional convolution beam space method. According to the algorithm, differential common array holes are filled through low-rank matrix recovery, a solving framework is constructed through an alternating direction multiplier method, and a multi-phase component averaging strategy based on a sliding window is designed for the extraction process. Simulation results show that the method solves the problem that the precision of a traditional convolution beam space method is reduced, and only negligible extra time overhead is introduced. Through comparison, the performance of the provided method is better than that of a traditional convolution beam space method and a method based on atom norm minimization and CVX toolbox solving, and the advantages are crucial for realizing real-time and high-precision DOA estimation in a large-scale extended co-prime array scene.

The embodiment of the invention discloses an efficient signal sampling rate transformation method and device based on discrete Fourier transform. According to one specific embodiment, the method comprises the steps that a target signal is acquired, and the target signal is a signal to be subjected to signal sampling rate conversion; discrete Fourier transform is carried out on the target signal to obtain a first signal frequency spectrum, and the first signal frequency spectrum is a signal frequency spectrum corresponding to the target signal; according to the interpolation multiplying power, the extraction multiplying power and the first signal frequency spectrum, a second signal frequency spectrum is generated, and the second signal frequency spectrum is a signal frequency spectrum corresponding to the output signal; and performing inverse discrete Fourier transform on the second signal spectrum to obtain an output signal. According to the embodiment, efficient sampling rate conversion is realized.