113 results about "Decimation" patented technology

The invention relates to the technical field of digital demodulation, in particular to a digital demodulation method suitable for deep ultraviolet light communication, which comprises the following steps of: adopting multiple delay processing with half code element width, and respectively carrying out double extraction processing on a discrete sampling signal which is not subjected to delay processing and a plurality of delay sampling signals to obtain a plurality of delay extraction signals; in this way, the key sampling time in the coverage code element period can be ensured, and a basis is provided for subsequent accurate synchronization; a plurality of delay extraction signals are respectively input into corresponding equalization processing units, a preset local training sequence is loaded to each equalization processing unit to obtain a plurality of equalization filtering signals, and the plurality of equalization filtering signals and the preset local training sequence are respectively subjected to related judgment processing, so that the inter-symbol interference is inhibited, and meanwhile, the equalization processing efficiency is improved. The synchronization signal can be quickly screened out, so that the problem that inter-symbol interference and synchronization are difficult to consider in a traditional demodulation method is solved, and the demodulation efficiency and reliability are remarkably improved.

The invention relates to a full-dynamic exponential increment type low-delay high-precision analog-to-digital converter, which comprises a loop integrator used for receiving an ith-round input signal, and sequentially performing addition processing and integration processing on the ith-round input signal and a feedback signal calibrated by an (i-1) th round to obtain an ith-round integration signal; the first-order exponential increment error feedback noise shaping SAR quantizer is used for carrying out addition processing and multi-bit quantization on the ith round integral signal and the double (i-1) th round residual signal to obtain an ith round quantization signal; the digital-to-analog conversion module is used for sequentially performing format conversion, mismatch calibration and digital-to-analog conversion on the (i-1) th round of quantized signals in the process of processing the ith round of input signals to obtain feedback signals after the (i-1) th round of calibration; and the digital decimation filter module is used for carrying out digital filtering and down-sampling processing on the ith-round quantized signal to obtain an ith-round Nyquist rate output signal. The system can realize higher significant digits in shorter conversion time.

An apparatus for calibrating a digital filter to replicate a transfer function of a signal processing device comprising a detector with a first input to receive a first signal; a second input to receive a response signal of the signal processing device to the first signal; a signal modification block; a comparison block and a decimation block; wherein the comparison-block compares a phase and amplitude of the first signal after a correction has been applied by the signal modification block and decimation has been applied by the decimation block; and a feedback loop; wherein detector is configured to determine at least a feedback control signal at a first frequency and a second frequency, different to the first frequency and determine calibration information for programming of the transfer function of said digital filter.

A device may encode a first set of pictures of the video data to generate first encoded video data; generate first error correction data based on the first encoded video data; transmit the first error correction data and the first encoded video data to a receiving device; receive, from the receiving device, a decimation pattern indication that indicates a decimation pattern determined based on the first set of pictures, the decimation pattern being a pattern of encoded video data non-transmission; encode a second set of pictures of the video data to generate second encoded video data; generate second error correction data based on the second encoded video data; apply the decimation pattern to the second encoded video data to generate decimated video data; and transmit the second error correction data and the decimated video data to the receiving device.

The invention relates to the technical field of broadband signal synthesis and high-speed digital-to-analog conversion, in particular to an oversampling-based real-time frequency interleaving digital-to-analog conversion system aliasing suppression method and system, and aims to solve the problem of spectrum aliasing caused by non-ideal characteristics of a digital sub-band decomposition filter and an analog filter under a real-time architecture of the system. In the invention, the sub-band decomposition is completed by adopting the linear phase complementary filter bank, so that distortion introduced by a transition band of a digital filter is avoided; by restraining system parameters such as passband and stopband frequencies and local oscillation frequency of a sub-band decomposition filter, a protection band is set by an oversampling mechanism, a frequency margin is reserved for a transition band of the filter, and aliasing components are suppressed. According to the method, extraction aliasing of a digital domain and mirror image aliasing of an analog domain are avoided at the same time from the system architecture, the frequency spectrum purity of output signals is improved, the method is suitable for a real-time system for processing continuous data streams, and technical support is provided for achieving a high-performance broadband signal source.

Systems and methods for compensating a transmit signal for charge trapping effects of a power amplifier are provided. In certain embodiments, a non-linear filter is trained based on time aligning a first set of observations taken from digital transmit data prior to conversion to a radio frequency transmit signal, and a second set of observations taken from an output of a power amplifier that amplifies the radio frequency transmit signal. In certain implementations, the first set of observations and the second set of observations are obtained without decimation. Rather, decimation is provided after timing alignment. By implementing the DPD system in this manner, signal data is not lost by decimation and more accurate timing alignment between the sets of observations is achieved.

The invention discloses a high-order digital decimation filter with a variable decimation multiple, which comprises a cascade comb filter used for downsampling and anti-aliasing filtering, filtering high-frequency components and obtaining low-frequency density signals, and a compensation filter connected to the output end of the cascade comb filter and used for compensating passband attenuation and performing double decimation on the signals, and the output end of the compensation filter is connected with a half-band filter for realizing third-stage signal extraction. The invention further discloses a filtering method of the high-order digital decimation filter with the variable decimation multiple. Aiming at the defects that a traditional single-stage FIR filter is high in hardware requirement, complex in design, high in filter order and not easy to implement and the like, and aiming at the defect that a CIC filter is insufficient in passband flatness, a CFIR compensation filter is used for compensation, and finally a half-band filter is used for frequency reduction.

This invention provides a phase code digital low-pass filter circuit and a re-timer based on a PI-based architecture. The phase code digital low-pass filter circuit includes a first accumulation unit and a downsampling decimation module. The first accumulation unit accumulates the initial frequency control information generated by the clock data recovery module of the re-timer to generate a phase signal. The downsampling decimation module downsamples the phase signal to generate a filtered phase code. The filtered phase code is used to generate the transmit channel clock. This invention effectively solves the problems of high implementation cost, large footprint, and easy introduction of additional analog non-ideal factors in existing digital filtering solutions.

The invention discloses a piecewise linear quantization mixed structure analog-to-digital converter with a noise shaping function, and belongs to the field of analog-to-digital converters, the analog-to-digital converter comprises an input control circuit, a nonlinear quantization circuit, a noise shaping modulation circuit, an output control circuit and a digital decimation filter circuit, the control circuit samples an input signal; the non-linear quantization circuit determines a non-linear section where an input signal is located and provides reference voltage for the noise shaping modulation circuit; the noise shaping modulation circuit is used for performing noise shaping and fine quantization on an input signal; the output control circuit combines the two parts of quantization output and generates a high-speed low bit code stream; the digital decimation filter circuit receives a high-speed code stream and generates a high-precision digital code through decimation filtering; according to the technology provided by the invention, suitable nonlinear quantization characteristics are provided according to different signal characteristics, and meanwhile, higher quantization precision and a wider dynamic range can be realized.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

The application discloses a high-speed sampling data real-time extraction method based on parallel digital filters, which comprises the following steps: collecting a measured signal through a collection system of a mixed domain oscilloscope to obtain parallel multi-channel signals; realizing large-multiple real-time extraction filtering through a parallel CIC filter and a cascaded parallel half-band filter to obtain serial data; and finally performing serial extraction on the serial data to obtain output data, so that the frequency resolution of the spectrum analysis function of the oscilloscope can be significantly improved without increasing the FFT length.

Embodiments of the present disclosure disclose processing of Narrow Band-Internet of Things (NB-IoT) Physical Resource Block (PRB). The method comprises aligning center of Physical Resource Block (PRB) in received time domain samples of Long-Term Evolution (LTE) channel bandwidth to center of LTE channel bandwidth; upon aligning center of PRB with center of LTE channel bandwidth, performing decimation on received time domain samples at predefined number of decimation stages sequentially to obtain decimated time domain samples of predefined sample rate; performing Fast Fourier Transform (FFT) operation on decimated time domain samples using FFT of predefined point to obtain corresponding frequency domain samples related to decimated time domain samples; and extracting valid tones from frequency domain samples based on valid tone indices to obtain modified PRB. The modified PRB is transmitted to processing unit for decoding data from modified PRB.

A method and system for bandwidth extension of a critical sampling circuit, belonging to the field of signal sampling technology. The implementation method is as follows: S1, estimating the model coefficients of the squared amplitude response of the simulated channel of the critical sampling circuit through ultra-relaxed primordial duality, constructing the simulated channel response matrix, and obtaining the system response matrix by row decimation; S2, establishing the high-dimensional response matrix of the critical sampling circuit and completing parameter initialization; S3, performing iterative calculation of the extension features through elastic network regression, checking the convergence of the extension residual or the number of iterations, if satisfied, proceeding to S4, otherwise continuing iteration; S4, reconstructing the high-dimensional signal using the extension features calculated in S3, and obtaining the reconstructed signal after bandwidth extension of the critical sampling circuit through sampling rate conversion. This invention, by iteratively calculating the spectral characteristics within the target extended bandwidth of the critical sampling circuit, can recover out-of-band lost spectral information without increasing the sampling clock frequency and analog input bandwidth, achieving low-cost high-frequency signal sampling.

This video encoding device includes: a decimation means for decimating pictures in a video; an encoding means for encoding a video signal resulting from the decimation of the pictures; and an auxiliary information generation means for generating auxiliary information for deriving a maximum latency picture quantity.

A device may: encode a first set of pictures of video data to generate first encoded video data; generating first error correction data based on the first encoded video data; sending the first error correction data and the first coded video data to a receiving device; receiving, from the receiving device, an extraction mode indication indicating an extraction mode determined based on the first picture set, the extraction mode being a mode in which the encoded video data is not transmitted; encoding a second set of pictures of the video data to generate second encoded video data; generating second error correction data based on the second encoded video data; applying an extraction pattern to the second encoded video data to generate extracted video data; and sending the second error correction data and the extracted video data to the receiving device.

The invention discloses an ADC50Hz or 60Hz noise filtering method based on a software algorithm, and the method comprises the steps: carrying out the initialization configuration, and collecting original data; preprocessing and acquiring detection data; an improved Goertzel algorithm is used to acquire frequency spectrum parameters; calculating a three-level extraction factor, and sampling the data output by the ADC to obtain sample data; after forward and reverse compensation is carried out on the sample data, pulse noise suppression of a two-dimensional window is carried out on pulse noise; calculating a transmission quality index, and adjusting the size of a filtering window according to the transmission quality index; and carrying out amplitude calibration on the filtering result by using an improved comb algorithm, and outputting a standard signal after noise reduction processing. On one hand, the noise reduction processing scheme does not need to additionally add a filter circuit, so that the circuit size and the hardware cost are reduced; and on the other hand, the parameters in the method can be adaptively adjusted according to the frequency spectrum parameters, so that the adaptability is improved.

The embodiment of the application provides a data processing method and device of a filter, electronic equipment and medium, the method comprises the following steps: obtaining input data; according to a pre-configured filtering parameter, searching a pre-stored lookup table to find a target output bit width corresponding to the input data; according to the target output bit width, using a cascade integrator to perform integral processing on the input data to obtain integral data; according to the target output bit width, using a decimator to perform decimation sampling on the integral data to obtain sampling data; and according to the target output bit width, using a cascade differentiator to perform differential processing on the sampling data to obtain filtered data corresponding to the input data. In the embodiment of the application, a bit width adaptive control unit is added to realize bit width selection and effective data bit control under different decimation rates and orders, which can effectively avoid the generation of burrs in the filtering process.

Techniques are provided for reduced latency look-ahead for signal detection. An example methodology implementing the techniques according to an embodiment includes down converting a digitized signal to a first baseband signal at a first decimation rate such that the first baseband signal is provided at a first latency with a first signal to noise ratio (SNR) based on the first decimation rate. The method also includes down converting the digitized signal to a second baseband signal at a second decimation rate, greater than the first decimation rate, such that the second baseband signal is provided at a second latency with a second SNR based on the second decimation rate, the second latency greater than the first latency and the second SNR greater than the first SNR. The method continues with generating a detection threshold based on the first baseband signal prior to completion of the second baseband signal generation.

The present invention provides an active noise control device. The active noise control device (10) controls a speaker (18) to output a canceling sound in order to cancel out noise transmitted from a vibration source. The active noise control device comprises a control signal generating unit (68), a secondary path filter updating unit (84), and a feedback filter setting unit (23). The control signal generating unit (68) processes a reference signal corresponding to a specified frequency through a feedback filter and an adaptive notch filter as a decimation filter to generate a control signal for controlling the speaker (18); the secondary path filter updating unit (84) adaptively updates the secondary path filter in sequence; and the feedback filter setting unit (23) sets the feedback filter according to the secondary path filter. Thus, noise can be reduced even if the transmission characteristics change.

A procedure for overcurrent shutdown is proposed, comprising the following steps: - Capturing and providing a current value as an analog output signal; - a conversion of the analog output signal by means of an analog-to-digital converter, which converts the analog output signal by means of sigma-delta modulation and provides it as a bitstream, characterized in that - the bitstream is converted using a first decimation filter and provided as a first data stream; and - Evaluating the first data stream, wherein a threshold value for a current is compared with the current value from the first data stream, and if at least one threshold value is exceeded, the overcurrent shutdown is triggered by means of a shutdown signal, wherein the shutdown signal is transmitted to at least one signal output and is used for opening a power switch. Furthermore, the invention relates to a device.

The application discloses a spectrum analyzer-based amplitude compensation method and device. The method comprises the following steps: before frequency sweeping starts, determining the starting frequency, stopping frequency and calibration frequency step of the current scanning frequency range, and determining the corresponding shift bit number according to the calibration frequency step, wherein the calibration frequency step is a power of 2; generating calibration data of a plurality of calibration points according to the starting frequency, stopping frequency and calibration frequency step, and storing the calibration data in a storage space accessible by an FPGA in the order of corresponding frequencies; obtaining the frequency value corresponding to the current data during frequency sweeping, and determining the calibration data index according to the frequency value corresponding to the current data and the calibration frequency step according to the upward rounding rule; reading the corresponding calibration data according to the calibration data index; and performing amplitude compensation on the current data by using the calibration data after digital down-conversion and before decimation filtering. The method can reduce the calibration data storage amount and FPGA operation resource consumption, and improve the real-time amplitude compensation accuracy during frequency sweeping of the spectrum analyzer.

The present invention discloses a high-precision power measurement method for digitally modulated communication signals, belonging to the field of communication reconnaissance technology. The method comprises: collecting an intermediate frequency (IF) signal, guiding down-conversion decimation filtering of a single signal according to the IF signal frequency bandwidth, and obtaining baseband IQ data of the single signal; identifying the IF signal modulation pattern according to the baseband IQ data, and determining the category to which the IF signal belongs; completing multi-dimensional spectrum calculation of the IF signal according to the category to which the IF signal belongs; performing signal energy statistics on the multi-dimensional spectrum maximum points of the IF signal to obtain relative signal power; and accurately calculating signal power based on the multi-dimensional spectrum maximum points and the relative signal power. The present invention can achieve high-precision measurement of communication signal power within a large signal-to-noise ratio range.

This invention provides a broadband signal analyzer, comprising: at least one superheterodyne frequency conversion receiving unit, at least one filtering unit, an ADC, a digital down-conversion and decimation filtering unit, an adaptive filtering unit, a data processing and display unit, and a scan controller, connected in sequence; the superheterodyne frequency conversion receiving unit includes: an attenuator, a mixer, and a local oscillator signal, the attenuator, mixer, and filtering unit being connected in sequence, the output terminal of the local oscillator signal being connected to the input terminal of the mixer, the input terminal of the local oscillator signal being connected to the output terminal of the scan controller, and the input terminal of the scan controller being connected to the output terminal of the ADC. This invention overcomes the problems of high filter order and excessive processing resource consumption caused by existing broadband signal in-band flatness compensation methods.

Three-dimensional sensing data is transferred efficiently by applying compressed sensing using dictionary learning. Conventional image-based lossy compression improves a feature according to which power is concentrated on low-frequency components and deterioration of three-dimensional information increases. By changing the decimation rates for the depth information and the color information and using a dictionary vector created from the other restoration result for restoration, the original result is reconstructed using a small data volume.

The application discloses a power frequency suppression filter suitable for a Sigma-delta ADC, comprising SINC1 filters SINC1_1-SINC1_6, FIR filters F1 and F2, decimation modules M1-M6, data selectors MUX1 and MUX2, mean filters MF1 and MF2; the power frequency suppression filter circuit suitable for the Sigma-delta ADC can simultaneously suppress 50Hz and 60Hz power frequency interference; the application adopts a multistage SINC1 filter and a FIR cascade structure, and can complete power frequency suppression under a set output sampling frequency; the application adopts a SINC1 filter multiplexing structure, reduces circuit area and power consumption; the application adopts a FIR filter multiplexing structure, maximally reduces multiplier use resources, and optimizes circuit area and power consumption.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The application discloses a low-resource-overhead super-high-speed modulation and demodulation method. In view of the signal processing demand faced by high-frequency bands and large bandwidths in millimeter wave and terahertz communication, the application adopts a parallel architecture to meet the high-speed signal processing demand and correct non-ideal characteristics of a channel; and adopts a fusion processing method to fuse interpolation, anti-aliasing, timing interpolation, matched filtering, time domain equalization and decimation into a multi-phase filter, so that the signal overhead caused by high-speed demodulation is greatly reduced. The application can be applied to a millimeter wave / terahertz super-high-speed transmission system, and provides low-complexity super-high-speed modulation and demodulation to meet the performance and resource demand of super-high-speed transmission.

Techniques for number theoretic transform (NTT) and inverse number theoretic transform (iNTT) are described. In some examples, an NTT circuit is to use a decimation-in-frequency (DIF) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order. In some examples, an iNTT circuit is to use a decimation-in-time (DIT) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order.

The present invention provides a spectrum splicing method, apparatus, device, storage medium, and program product, which are applied to the field of signal processing technology. The method comprises: determining a target number of analog-to-digital converters based on a target sampling bandwidth and a sampling rate of a single analog-to-digital converter, and using the target number of analog-to-digital converters to collect an initial broadband signal in frequency bands; dividing the spectrum of the initial broadband signal into multiple subbands, and performing target processing on the sampling rate of each of the multiple subbands to obtain a target sampling rate; performing fast Fourier transform processing on the target sampling rate based on the number of fast Fourier transform points to obtain frequency domain data; and performing spectrum splicing on the frequency domain data to obtain a target spectrum; wherein the target processing includes sequentially performing time domain filtering processing and adjusting the sampling rate through decimation filtering or interpolation filtering according to the target frequency resolution.

The application discloses a signal processing system of FPGA high sampling rate signal, comprising: a multi-phase local oscillator generation module configured to generate a plurality of high sampling rate local oscillator signals; a plurality of complex mixing modules corresponding to the plurality of high sampling rate local oscillator signals; the complex mixing module is configured to receive the corresponding high sampling rate local oscillator signal and the high sampling rate signal, and to complexly mix the corresponding high sampling rate local oscillator signal and the high sampling rate signal to obtain a plurality of intermediate frequency signals; a filtering and decimation module configured to receive the plurality of intermediate frequency signals and to filter and decimate the intermediate frequency signals to obtain a low sampling rate signal. The signal processing of the high sampling rate signal is completed, and finally the low sampling rate signal capable of being directly processed by the FPGA is obtained. The multiplexing of the multi-phase local oscillator generation module greatly saves the logic resources of the FPGA, and the phase control mode is more flexible and has higher applicability.