142 results about "Digital down conversion" patented technology

The invention discloses an interference suppression method for a random phase modulation electromagnetic metasurface. The interference suppression method comprises the following steps: constructing a mathematical model for a modulated radar echo signal; wherein a random phase modulation electromagnetic metasurface is installed on the surface of a target, a radar transmitting signal enters the random phase modulation electromagnetic metasurface, and after random time domain phase modulation, a radar echo signal is generated; discrete sampling processing is carried out after digital down-conversion and dechirping are carried out on radar echo signals, and then additional phase information is estimated after self-mixing processing is carried out. Phase compensation is carried out on the radar echo signal after discrete sampling processing under the condition that noise is considered, and then time domain differential transformation and discrete Fourier transformation are carried out; estimating a phase mutation moment by using a subspace algorithm, and reconstructing an interference modulation sequence based on an estimation result; and demodulating random phase interference by using the reconstructed interference modulation sequence, and performing matched filtering processing to obtain an output signal.

The invention discloses an RFSOC-based FAST core array distributed collaborative observation and data fusion method and system, and the method comprises the steps: S1, system initialization: a master node RFSOC generates a global clock, achieves the phase synchronization of multiple board cards through an SYSREF differential signal, and completes the calibration of a three-stage clock tree; s2, signal acquisition and preprocessing: directly sampling a 3-8GHz radio frequency signal through an ADC (Analog to Digital Converter), and performing digital down-conversion to obtain a baseband signal; s3, intelligent resource scheduling: identifying a signal type based on an ESN (Echo State Neural Network), and dynamically allocating FPGA logic resources through an improved ant colony algorithm; s4, heterogeneous calculation acceleration: executing a 128-channel digital beam forming pipeline on the FPGA; s5, cross-domain data fusion; s6, collaborative observation planning; and S7, outputting data. The method is suitable for multi-beam synthesis, cross-region joint observation and mass data real-time processing scenes, and provides key technical support for solving the frontier scientific problems such as rapid radio storm origin and black hole activity monitoring.

The invention discloses a frequency hopping signal real-time detection method and system based on FPGA + DSP. The system comprises a time frequency analysis module, a data communication module and a frequency hopping signal detection module. The method comprises the following steps: a time frequency analysis module performs analog-to-digital conversion and digital down-conversion on an intermediate frequency signal received from a radio frequency end, and performs short-time Fourier transform on a zero intermediate frequency signal by adopting a four-pipeline processing mode; the data communication module transmits the frequency spectrum information from the FPGA to the DSP through an SRIO protocol; the frequency hopping signal detection module calculates a dynamic threshold of a current frame signal according to the received frequency spectrum information, and completes preliminary detection of the signal according to a threshold value; and carrying out binarization processing and connected domain marking on the detected frequency spectrum, screening non-frequency hopping signals according to time-frequency information of a connected domain, and packaging and uploading parameter information of the detected frequency hopping signals to an upper computer. The method is simple in algorithm, low in hardware resource requirement and high in detection efficiency, and the feasibility of engineering implementation is improved.

The invention discloses a signal identification method based on broadband spectrum detection, and the method comprises the steps: carrying out the power spectrum estimation and signal detection of broadband IQ data through an FPGA, obtaining a signal frequency point parameter, and configuring a DDC module to complete digital down conversion; performing power spectrum density estimation and noise floor estimation on the narrowband IQ signal on the upper computer; preliminary classification is carried out by calculating a ratio parameter C1 of a maximum value and a second maximum value of a frequency spectrum, and when C1 is greater than a threshold, AM and a single carrier signal are discriminated by combining a frequency spectrum characteristic parameter C2 and an amplitude spectrum characteristic parameter C3; when C1 is smaller than or equal to a threshold, signal detection is carried out by adopting a double-threshold algorithm, and merging and screening in a multi-signal scene are completed; classifying based on a normalized zero center instantaneous amplitude spectrum density maximum value parameter C4, judging FM, MSK and FSK signals when the C4 is less than a threshold, and judging BPSK, QPSK, 8PSK and 16QAM signals when the C4 is greater than or equal to the threshold; according to the method, a multi-parameter joint judgment strategy is adopted, and the accuracy and the real-time performance of signal recognition are remarkably improved.

The invention relates to a method for realizing multi-channel ADC (Analog to Digital Converter) data synchronization processing based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: the FPGA receives a clock frequency generated by an external clock generator and takes the clock frequency as a working clock of the FPGA; a plurality of groups of same-frequency clocks and same-phase clocks are generated in the FPGA and are respectively used as working clocks of the ADC chips; the FPGA receives sampling data of each ADC, an enable signal is set, and when the enable signal is effective, digital down-conversion, decimation filtering and FIR filtering are carried out on each sampling data; and after FIR filtering is completed, another enable signal ENend is generated, and data are further stored or transmitted to an upper computer. According to the method and the device for realizing the multi-channel ADC data synchronous processing based on the FPGA, the processor and the computer readable storage medium thereof, synchronous start and stop of the processing flow are controlled through the enable signals ENstart and ENend, synchronous processing of the multi-channel ADC data is ensured, accuracy and effectiveness are improved, and the method and the device have a wide application range.

The invention relates to a low-orbit satellite short burst signal high-precision capturing method and device, equipment and a medium. The method comprises the following steps: sequentially carrying out digital down-conversion and L-time signal pseudo code rate down-sampling on a low earth orbit satellite short burst signal sequence sampled by an ADC (Analog to Digital Converter) to obtain a down-sampled signal sequence; performing pre-accumulation processing on the down-sampling signals of every adjacent L points in the down-sampling signal sequence, and performing coarse capture on the pre-accumulated signal sequence by adopting a PMF-FFT algorithm to obtain a coarse pseudo code phase and a coarse frequency offset value; and performing serial code phase search on the down-sampling signal sequence based on the coarse pseudo code phase and the coarse frequency offset value, optimizing to obtain a fine pseudo code phase, and optimizing the estimation precision of the coarse frequency offset value according to the fine pseudo code phase and a frequency offset estimation algorithm based on a phase relation to obtain a fine frequency offset value. By adopting the method, the acquisition precision and speed of the short burst signal of the low-orbit satellite can be improved.

The invention relates to the field of digital signal processing, in particular to a miniature digital transceiver module which comprises a signal processing board and a power clock board. The signal processing board and the power supply clock board are stacked and interconnected through a high-speed connector; the signal processing board integrates multiple ADC acquisition channels and DAC output channels, and is internally provided with an RFSOC chip to realize multichannel digital down-conversion, waveform generation and signal processing functions. The power supply clock board integrates a power supply conversion module and a clock frequency synthesizer, provides various power supply varieties for the module, and generates a time sequence, a sampling clock and a reference clock. The stacking design of the two board cards forms a high-integration digital transceiver module, thereby saving a large amount of space and improving the system integration. The scheme is obviously superior to a traditional design method in the aspects of volume, power consumption, performance and the like, and is particularly suitable for equipment sensitive to an outer envelope.

The invention discloses a control chip of an underwater sonar system and underwater sonar equipment, the sonar system comprises a plurality of receiving array elements, the control chip comprises a processor system core and a programmable logic core, and the processor system core is used for controlling the programmable logic core to operate; the programmable logic core comprises a plurality of intellectual property cores, and each intellectual property core comprises a digital down-conversion module, an FFT (Fast Fourier Transform) module and a beam forming module; wherein the digital down-conversion module is used for obtaining a first frequency conversion signal based on an echo signal received by a receiving array element in response to a first instruction; the FFT module is used for responding to a second instruction and obtaining sub-band data based on the first frequency conversion signal; the beam forming module is used for responding to a third instruction and obtaining total output in a preset direction based on the sub-band data; and the detection module is used for obtaining target object information based on the total output in the preset direction.

The invention particularly relates to a method for converting pseudo code capture into tracking phase compensation under clock frequency offset. The method comprises the steps of band-pass sampling and digital down-conversion, local pseudo code sequence generation, twice pseudo code capture and phase compensation. Selecting a sampling frequency and processing a signal through a band-pass sampling theorem, and generating a local pseudo code based on a Gold code; a PMF-FFT method of a mobile pseudo code is adopted to complete first-time pseudo code capture, a multiplexing capture module executes second-time full-range capture, and pseudo code phase offset is accurately calculated; and finally, adjusting the local pseudo code phase through the total phase compensation value, so that the phase difference between the input signal and the local pseudo code is controlled within a half chip. According to the method, hardware cost does not need to be increased, the problem of inaccurate phase compensation under clock frequency offset, large frequency offset and low carrier-to-noise ratio scenes is effectively solved, it is guaranteed that pseudo code capture is smoothly converted into tracking, and the tracking reliability of a receiver is improved.

The invention relates to a system for realizing power trigger control in burst communication based on an FPGA (Field Programmable Gate Array), which comprises a digital down-conversion module, a trigger judgment module and a trigger data storage module, and is characterized in that the digital down-conversion module is used for carrying out digital down-conversion, generating IQ data with different sampling rates through a half-band filter and transmitting the IQ data into the trigger judgment module; after the trigger judgment module receives the IQ data, a power value is calculated through modulo operation, a moving average algorithm is achieved, and a Trigger signal is obtained; and the trigger data storage module is used for judging the received signal and storing required IQ data. The invention also relates to a method and a device for realizing power trigger control in burst communication based on the FPGA, a processor and a computer readable storage medium thereof. By adopting the system, the method, the device, the processor and the computer readable storage medium for realizing the power trigger control in the burst communication based on the FPGA, the effective initial position of a required signal can be quickly captured, the processing time of a signal tracking synchronization algorithm is reduced, the hardware cost is low, and the application is wider.

The invention relates to the technical field of communication, in particular to a method for enhancing spurious frequency suppression in short-wave multi-channel reception, which comprises the following steps of: after converting a collected short-wave radio-frequency signal into a digital signal, respectively processing the digital signal through a first channel and a second channel, the first channel carries out filtering preprocessing on the digital signal to obtain a preprocessed signal, and then carries out down-conversion processing on the preprocessed signal to obtain a first baseband signal; the second channel performs down-conversion processing on the digital signal to obtain a second baseband signal; multichannel processing is carried out on digital signals at the same time, the application scene of short-wave broadband high-data-rate multi-channel down-conversion processing can be supported, the requirement for simultaneous receiving of short-wave multi-channel frequency points is met, each far-end interference source can be filtered through multi-channel digital resonance processing, and the receiving efficiency is improved. And the spurious suppression capability during digital down-conversion processing is enhanced.

The invention discloses a software radio digital signal frequency conversion method and system and a medium. Relates to the technical field of digital signal processing. Comprises: acquiring an input signal; performing complex multiplication on the input signal and the carrier signal to obtain a frequency conversion signal; based on an adjustable filtering extraction module, performing integral multiple or rational multiple filtering extraction on the frequency conversion signal to obtain an output signal; wherein rational multiple filtering extraction is realized by a numerical control oscillator and an interpolation unit; according to the scheme, on the basis of the traditional technology of realizing the digital down converter on the FPGA, the method and the structure are improved, and on the basis of an adjustable filtering extraction module, integral multiple or rational multiple filtering extraction is carried out on a frequency conversion signal to obtain an output signal; free adjustment of the digital down-conversion multiple is achieved, and rational number multiple configuration of digital down-conversion is achieved based on the numerically controlled oscillator and the interpolation unit.

A method for identifying a drone based on deep learning radio frequency fingerprints belongs to the field of signal recognition and drone identification. The RF front end collects the radio frequency signal of the drone during flight, performs signal preprocessing through a low noise amplifier, a bandpass filter and a pre-amplifier, and then obtains an IQ signal through digital down-conversion. The amplitude of the IQ signal is calculated, and the amplitude sequence is further divided and spliced ​​to obtain the final input data of the deep learning network. If it is a model training process, data annotation is required, and a unique hot encoding is generated according to the drone category. The deep learning network model is composed of ViT blocks of different patch sizes, and each ViT block contains a multi-head attention mechanism and a multi-layer perceptron. By weighted summing the outputs of all ViT blocks, a vector consistent with the label dimension for predicting the drone category can be obtained. The present invention has the characteristics of fast calculation speed, high accuracy of drone identity recognition, and no information leakage.

The invention discloses a digital down-conversion and anti-mirror-interference method for the Internet of Things, and the method comprises the following steps: S1, constructing a receiving path, carrying out the down-conversion of a radio-frequency signal, and carrying out the analog-to-digital conversion of the radio-frequency signal into a low-intermediate-frequency I / Q orthogonal digital signal; s2, inputting the I / Q signal into a notch filter, suppressing harmonic interference of a crystal oscillator, and outputting an interference weakening signal; s3, looking up the table to generate an orthogonal local oscillator signal; s4, performing compound frequency mixing on the filtered I / Q signal and a local oscillator signal; s5, inputting the frequency mixing signal into a mirror image rejection module, and executing weighting operation to filter mirror image interference; s6, inputting the signal into a low-pass filter, suppressing sideband and mirror image residue, and outputting a target baseband signal; s7, performing normalization and compression processing on the signals; and S8, inputting into a post-stage processing module, and dynamically adjusting parameters according to feedback to enhance the anti-interference capability. According to the method, a low-power-consumption digital down-conversion link is constructed, image rejection and a self-adaptive mechanism are fused, and robust receiving processing of interference is achieved.

The application discloses a handheld spectrum analyzer real-time spectrum signal processing system and processing method, the system comprises a pre-processing unit, an ADC unit, an FPGA and an ARM which are connected in sequence, the FPGA comprises a digital down conversion unit, a multi-rate decimation filter unit, a real-time FFT operation unit and a real-time detection unit which are connected in sequence, and a grid mapping unit, a vector connection unit and a fluorescence statistical unit which are connected with the real-time FFT operation unit in sequence, the ARM comprises a real-time spectrum diagram and waterfall diagram unit which is connected with the real-time detection unit, and a fluorescence display unit which is connected with the fluorescence statistical unit. The application adopts parallel frame real-time detection and vector connection-based digital fluorescence statistical method to compress multiple spectrum data, reduces the requirement of a large number of spectrum data on screen refreshing, adopts vector connection to make fluorescence statistics, so that the measured signal is easier to distinguish, and the application meets the test requirement of a handheld instrument.

The invention provides a vehicle-mounted SDR monitoring method and device for mobile monitoring of an urban electromagnetic environment, and the method comprises the steps: receiving and down-converting a radio frequency signal through a radio frequency front-end module, carrying out the analog-to-digital conversion and digital down-conversion of a signal processing module, and carrying out the spectrum analysis through a main control and analysis module; when the monitoring bandwidth exceeds the single sampling capability of hardware, a step tuning strategy is adopted to carry out segmented scanning and frequency spectrum splicing; performing standardization processing on the data through a power calibration model, and finally uploading the standardized spectrum data through an MQTT protocol; according to the invention, a reconfigurable SDR platform is adopted, and step tuning, power calibration and lightweight transmission mechanisms are combined, so that the technical problems of limited bandwidth, hardware rigidity, unreliable data transmission, uncomparable measurement results and the like of traditional monitoring equipment are solved, and broadband, high-precision and high-efficiency urban electromagnetic environment mobile monitoring is realized.

The invention discloses a bandwidth adaptive coverage system comprising a digital attenuator, an ADC module, a gain fine tuning module, a DC calibration module, a mirror image calibration module, a digital down-conversion DDC module, a variable broadband filter, a digital domain switch, a digital up-conversion DUC module, a PLAGC module and a DAC module which are connected in sequence. The DDS generation module is connected between the digital down conversion DDC module and the PLAGC module, and the AGC module is connected between the gain fine tuning module and the DC calibration module. According to the invention, the problem of source bandwidth change can be well solved, and signal detection and bandwidth self-adaption can be realized at low cost, so that the system performance is not influenced, and the signal does not need to be disconnected.

The invention discloses a multi-stage all-digital adaptive equalization device suitable for echo high-speed data transmission signals, and belongs to the field of communication and data transmission. The device comprises an ADC (Analog to Digital Converter), a digital down-conversion module, a digital resampling module, a matched filtering module, a self-adaptive multipath offset equalization module, a carrier synchronization module, a timing synchronization module and a self-adaptive inter-symbol crosstalk offset equalization module. Compared with a traditional self-adaptive equalization device, pilot frequency transmission is not needed, an all-digital implementation scheme is adopted, the equalization process is reasonably decomposed into a two-stage equalization processing process, and the flexibility and stability of the equalization device are improved. Hardware logic resources required for realizing the device are relatively small, the realization complexity is low, and the device is convenient to realize and popularize.

The invention provides a WiFi network digital down-conversion system which comprises a multi-phase mixer and a resampling filter. The multi-phase mixer is used for converting a high-speed digital band-pass signal into a low-speed mode so as to realize digital down-conversion (DDC) on an FPGA (Field Programmable Gate Array) platform; and the resampling filter is used for reducing the sampling rate and removing unwanted frequency spectrum components to generate a complex baseband frequency spectrum. The multi-phase mixer PM of the present invention employs a parallel coordinate rotation digital computer (CORDIC) processor and a low pass filter array to reduce high speed data rates while minimizing resource utilization. The resampling filter comprises a cascade integral combination (CIC) filter and a multi-channel pulse finite impulse response (FIR) filter, optimal hardware cost is achieved, a floating point data type is converted into a fixed point data type, and resources are remarkably saved.

The present invention provides a Ka-band DBF-SAR real-time processing system and method, including: a data acquisition module: using different AD acquisition sub-boards to sample multi-channel intermediate frequency signals and perform framing and caching; a digital processing module: digitally down-converting the cached multi-channel intermediate frequency signals to obtain multi-channel baseband signals, and sequentially filtering, decimating and processing with an improved DBF SCORE algorithm, and synthesizing multi-channel echo data; the improved DBF-SCORE algorithm performs range-oriented multi-channel DBF after channel equalization and pulse compression, thereby reducing the amount of data downlink. The present invention has the advantages of real-time processing, multi-channel and high integration, and is expected to play an important role in the field of millimeter-wave SAR.

The application relates to the technical field of data processing, and discloses a receiving multi-channel phase fast calibration compensation method, which comprises the following steps: sending original sampled data into a digital down-conversion module, sending filtered data into a peak value searching module, calculating a signal phase, calculating corresponding sine and cosine values, and outputting calibrated data after the down-converted data are multiplied with the sine and cosine values calculated in step S4 through a phase compensation module; the receiving multi-channel phase fast calibration compensation method can perform real-time phase calibration compensation, can perform phase calibration compensation on multiple different frequency points respectively, and greatly improves the calibration precision and the calibrated performance; the method can enable a large phased array system to be quickly deployed, greatly saves the time spent in calibrating the phase, can also reduce the uncertainty caused by human measurement errors, and greatly improves the stability of the system.

The invention particularly relates to a multi-dimensional suppressing interference rapid interception response signal processing method, which comprises the following steps of: setting energy and frequency detection after echo sampling, setting energy and frequency detection after digital down-conversion, setting signal feature detection after pulse compression and moving target indication, and setting statistical detection after CFAR (Constant False Alarm Rate) detection. Signal feature detection is set after moving target detection and SAR imaging. And based on the score of each detection module, control enabling of different priorities on the anti-interference function of the system, including an immediate dimension, a short-time dimension and a long-time dimension, is generated, so that the aim of rapidness is fulfilled. According to the method, the suppression interference is accurately and quickly identified in combination with the judgment standards of multiple dimensions, the anti-interference response is carried out at the fastest speed, and the anti-interference response is carried out at the fastest speed. The application can be well embedded into a conventional radar signal processing system, has the characteristics of strong universality, good real-time performance and high accuracy, and can be widely applied to the field of digital signal processing products.

The invention discloses a terahertz frequency modulation continuous wave radar signal processing system and method based on an FPGA. The system comprises an A / D acquisition control module, a digital down-conversion module, a fast two-dimensional Fourier transform module, a non-coherent accumulation module and a constant false alarm detection module. The method comprises the following steps that: the A / D acquisition control module samples an analog echo signal; the digital down-conversion module performs digital down-conversion processing on the sampling signal to obtain baseband echo I and Q data; the fast two-dimensional Fourier transform module is used for carrying out FFT (Fast Fourier Transform) on baseband echo I and Q data to obtain a range profile of a target, and the non-coherent accumulation module is used for carrying out amplitude accumulation and averaging on a plurality of target range profiles in different periods in the same wave beam; and the constant false alarm detection module compares and judges the signal amplitude of the detection unit with a set threshold to obtain a false alarm detection result. The method has the advantages of being high in real-time performance, high in reliability, simple in design, high in adaptive capacity and wide in application range.

This invention addresses the problem that the direct zeroing method used in existing satellite navigation signal processing frequency domain FFT notch filtering easily leads to power loss near interference frequencies, affecting signal integrity. It proposes a narrowband interference suppression system and method for BeiDou navigation. The narrowband interference suppression system includes a BeiDou RF front-end module, a high-speed ADC sampling module, a digital down-conversion (DDC) module, a signal distributor and buffer module, an interference detection and parameter estimation unit, an interference suppression execution unit, a baseband correlation and demodulation module, and a navigation and positioning result output module. A cascaded array of IIR notch filters is constructed using a cascaded array module. A steep transition band is achieved through small-order serial units, and the stopband width of the notch filters can be flexibly adjusted via a convergence factor. This enables precise suppression of extremely narrow stopband interference at different bandwidths, filtering out signals only at interference frequencies, effectively avoiding impact on surrounding useful BeiDou signals and preventing spectrum leakage.

The invention discloses a voice signal silencing device based on joint detection. A received intermediate frequency voice signal is subjected to analog-to-digital conversion and digital down-conversion through an AD module and a down-conversion module; after digital automatic gain control is completed by the AGC module, the voice signal is divided into two paths; the carrier detection processing module carries out carrier detection processing on one path of voice signals to obtain power spectrum characteristics; the voice squelch detection module demodulates the other path of voice signal, on one hand, demodulated voice is output when the squelch gate is in an open state, and on the other hand, voice feature detection processing is performed on the demodulated voice to obtain voice features; and the joint judgment module performs joint judgment on the power spectrum characteristics and the voice characteristics calculated by the carrier wave squelch detection module and the voice squelch detection module, and controls the opening and closing states of a squelch door. According to the invention, the carrier squelch technology and the voice squelch technology are jointly used, so that the false alarm probability and the missed alarm probability are effectively reduced.

The application provides a general radar array element level multi-target simulation method. After target echo signals received by a radar array surface are converted by an analog-to-digital converter, the target echo signals are usually digital intermediate frequency echo signals. The application can simultaneously simulate digital intermediate frequency signals of multiple targets under the condition that a radar array front end or an external test environment is not provided, and the digital intermediate frequency signals are subjected to digital down-conversion processing to obtain baseband signals. The baseband signals are multiplied by a steering vector of the targets on different array elements to obtain radar array element level multi-target simulation signals. The number of targets, amplitudes, angles, distances, speeds and array element information can be parameterized and configured, the verification and development efficiency of subsequent algorithms is greatly improved, the research and development cost is reduced, and the application has the characteristics of strong universality, high flexibility, fast development efficiency and wide adaptation to scenarios.

The application discloses a spectrum analyzer-based amplitude compensation method and device. The method comprises the following steps: before frequency sweeping starts, determining the starting frequency, stopping frequency and calibration frequency step of the current scanning frequency range, and determining the corresponding shift bit number according to the calibration frequency step, wherein the calibration frequency step is a power of 2; generating calibration data of a plurality of calibration points according to the starting frequency, stopping frequency and calibration frequency step, and storing the calibration data in a storage space accessible by an FPGA in the order of corresponding frequencies; obtaining the frequency value corresponding to the current data during frequency sweeping, and determining the calibration data index according to the frequency value corresponding to the current data and the calibration frequency step according to the upward rounding rule; reading the corresponding calibration data according to the calibration data index; and performing amplitude compensation on the current data by using the calibration data after digital down-conversion and before decimation filtering. The method can reduce the calibration data storage amount and FPGA operation resource consumption, and improve the real-time amplitude compensation accuracy during frequency sweeping of the spectrum analyzer.

This invention provides a broadband signal analyzer, comprising: at least one superheterodyne frequency conversion receiving unit, at least one filtering unit, an ADC, a digital down-conversion and decimation filtering unit, an adaptive filtering unit, a data processing and display unit, and a scan controller, connected in sequence; the superheterodyne frequency conversion receiving unit includes: an attenuator, a mixer, and a local oscillator signal, the attenuator, mixer, and filtering unit being connected in sequence, the output terminal of the local oscillator signal being connected to the input terminal of the mixer, the input terminal of the local oscillator signal being connected to the output terminal of the scan controller, and the input terminal of the scan controller being connected to the output terminal of the ADC. This invention overcomes the problems of high filter order and excessive processing resource consumption caused by existing broadband signal in-band flatness compensation methods.

The invention provides a data processing device, which belongs to the technical field of wireless communication, and comprises an FPGA (Field Programmable Gate Array) chip and a data memory for storing air interface IQ (Intelligence Quotient) data, the FPGA chip further comprises a storage interface module; the frequency band digital down-conversion module is used for performing sampling rate conversion on the digital signal input into the FPGA chip to obtain air interface IQ data and storing the air interface IQ data to the data memory; the frequency point digital down-conversion module is used for responding to the starting instruction of the central processing unit, extracting target air interface IQ data according to pre-configured data reading parameters, and performing sampling rate recovery on the target air interface IQ data to obtain output IQ data; and the post-stage processing module is used for processing the output IQ data and returning a processing result to the central processing unit. On the whole, on the basis of a collaborative architecture combining FPGA hardware acceleration and CPU non-real-time scheduling, multi-system multi-cell data unified storage and dynamic processing which are flexible in expansion and easy to maintain are supported.

The invention discloses a method for realizing digital signal processing of a VOR receiver based on an FPGA (Field Programmable Gate Array) technology, which relates to the technical field of radio navigation and digital signal processing and comprises the following steps of: constructing a VOR full-digital simulation signal source, and simulating signal input in a VOR system; performing digital down-conversion and filtering processing on the received radio frequency signal, and separating a variable phase signal and a reference phase signal through a digital filter; calculating a phase difference by adopting a zero-cross detection method; all the modules are integrated into an FPGA system, and performance testing is carried out. According to the invention, not only can the angle measurement precision, real-time performance and anti-interference capability of the VOR receiver be improved, but also the defects of large temperature drift and large size of the traditional analog receiver can be overcome, the characteristics of reconfigurability and parallel processing of the FPGA are utilized, the requirements of miniaturization and high reliability of modern aviation navigation equipment are met, the upgrading and updating of the full-digital VOR technology in the aviation field are promoted, and the application prospect is wide. And powerful technical support is provided for safe aviation flight.