11 results about "Digital down conversion" patented technology

This invention addresses the problem that the direct zeroing method used in existing satellite navigation signal processing frequency domain FFT notch filtering easily leads to power loss near interference frequencies, affecting signal integrity. It proposes a narrowband interference suppression system and method for BeiDou navigation. The narrowband interference suppression system includes a BeiDou RF front-end module, a high-speed ADC sampling module, a digital down-conversion (DDC) module, a signal distributor and buffer module, an interference detection and parameter estimation unit, an interference suppression execution unit, a baseband correlation and demodulation module, and a navigation and positioning result output module. A cascaded array of IIR notch filters is constructed using a cascaded array module. A steep transition band is achieved through small-order serial units, and the stopband width of the notch filters can be flexibly adjusted via a convergence factor. This enables precise suppression of extremely narrow stopband interference at different bandwidths, filtering out signals only at interference frequencies, effectively avoiding impact on surrounding useful BeiDou signals and preventing spectrum leakage.

The application discloses a spectrum analyzer-based amplitude compensation method and device. The method comprises the following steps: before frequency sweeping starts, determining the starting frequency, stopping frequency and calibration frequency step of the current scanning frequency range, and determining the corresponding shift bit number according to the calibration frequency step, wherein the calibration frequency step is a power of 2; generating calibration data of a plurality of calibration points according to the starting frequency, stopping frequency and calibration frequency step, and storing the calibration data in a storage space accessible by an FPGA in the order of corresponding frequencies; obtaining the frequency value corresponding to the current data during frequency sweeping, and determining the calibration data index according to the frequency value corresponding to the current data and the calibration frequency step according to the upward rounding rule; reading the corresponding calibration data according to the calibration data index; and performing amplitude compensation on the current data by using the calibration data after digital down-conversion and before decimation filtering. The method can reduce the calibration data storage amount and FPGA operation resource consumption, and improve the real-time amplitude compensation accuracy during frequency sweeping of the spectrum analyzer.

This invention relates to the field of communication technology, specifically to a frequency offset estimation method based on compressed sensing and frequency doubling joint estimation. The method includes the following steps: S1, establishing a sparse representation model of the signal frequency offset, constructing a sparse dictionary of the signal frequency offset matching the frequency offset characteristics of short-time burst signals based on the sparse representation model, performing a coarse frequency offset estimation using a compressed sensing algorithm, and outputting a coarse frequency offset estimate; S2: based on the coarse frequency offset estimate obtained in step S1, performing digital down-conversion (DDC) processing on the received short-time burst signal to obtain a baseband signal that eliminates the principal components of the coarse frequency offset estimate and retains only the residual small frequency offset; S3: performing a frequency doubling joint estimation on the baseband signal obtained in step S2 using the four-fold relationship of the signal frequency offset to achieve a fine estimation of the frequency offset of the short-time burst signal, and outputting the final accurate frequency offset estimate. This invention solves the technical problems of high sample size requirements and lack of effective connection between coarse and fine estimation in short-time burst signal frequency offset estimation.

The application belongs to the field of communication measurement and control, and particularly relates to a measurement and control transponder system and equipment for quickly and reliably capturing a mixed spread spectrum signal, and aims to solve the problem of insufficient system precision and weak reliability. The application comprises a digital down-conversion module for receiving a signal and performing digital down-conversion processing on the signal; a direct spread code capture module for capturing the zero intermediate frequency signal and performing modulation to obtain a spread spectrum signal; a frequency hopping interval division module for dividing the bandwidth of the spread spectrum signal into N parallel frequency hopping intervals according to a frequency hopping pattern; a matched filter module for filtering the signal and performing N-point Fourier operation; a capture decision module for comparing the code phase with a threshold value, and if the threshold value is exceeded, determining that capture is successful; and a synchronization refresh module for performing dynamic refresh through a synchronization refresh algorithm. The application improves the capture speed and reliability of the measurement and control transponder.

This invention discloses an adaptive link transmission method for airborne missile swarm networks, comprising: receiving a signal and then digitally down-converting it to obtain sampled data; passing the sampled data through a correlator to obtain a coherently demodulated data sequence; performing an N-point FFT spectral analysis on the obtained coherently demodulated data sequence to obtain the carrier frequency offset; after the FFT spectral analysis, detecting whether spectral peaks appear in the spectral analysis results, making an acquisition decision, and thus completing coarse synchronization; after the signal is acquired, calculating the peak values ​​of the corresponding power spectrum of the acquired signal, and finding the maximum value of these peaks, with the sampling point corresponding to this maximum peak value being the fine synchronization point; through the above steps, fast frame synchronization, precise symbol synchronization, and initial frequency offset estimation are performed on the signal. This invention achieves efficient and reliable communication of airborne missile swarms in complex electromagnetic environments by combining correlation-based FFT fast acquisition and synchronization technology and spatial diversity reception technology.

The application provides a kind of heterogeneous platform radar control and signal processing device and radar system, it is related to radar system technical field, the device includes: control and processing unit, including ZYNQ, FPGA and DSP three heterogeneous processors;ZYNQ processor includes PS end and PL end, PS end runs main control software, for whole machine state control, resource scheduling, instruction forwarding and echo data processing and forwarding;PL end is configured to realize timing, wave control, signal generation and data interface driving function;FPGA processor is configured to realize signal acquisition, digital down-conversion filtering, digital beam forming, pulse compression, coherent accumulation and moving target detection function;DSP processor is configured to realize constant false alarm detection function, and segmented processing is carried out to the data of different distance sections using multi-core parallel processing architecture;Signal interface unit is used to realize the signal and data interaction between overall device and external radar subsystem. The application realizes the high integration of radar system while improving signal transmission, processing performance.

A kind of mobile phone signal shielding system using first detection after shielding, including the multiple detection receiving link of independent uplink signal power statistics and detection to each communication frequency band multiple sub-bands;For sending targeted downlink interference signal in corresponding sub-band and time slice multiple shielding sending link;For dividing large bandwidth signal into multiple small bandwidth sub-bands digital down-conversion frequency selection module;For the real-time power of each sub-band is counted and compared with preset power threshold sub-band power statistics module;Shielding control module for controlling the working state of shielding sending link according to power statistics result, compared with prior art, the utility model discloses in the detection shielding range has uplink signal frequency band sub-band and time slice only sends downlink interference signal, greatly reduces the bandwidth of sending interference signal and the time of sending interference signal, improves the utilization efficiency of interference signal, greatly reduces the power consumption and electromagnetic radiation of system.

The application provides a sliding ping-pong signal processing system for improving radar data rate, which comprises: a high-speed AD sampling module for collecting target echo signals; a signal preprocessing FPGA module connected with the high-speed AD sampling module, including a digital down-conversion unit, a pulse compression unit and a coherent accumulation unit, for carrying out digital down-conversion, pulse compression and coherent accumulation processing on the collected target echo signals, generating subdivided pulse group accumulation data, carrying out FFT transformation on the subdivided pulse group accumulation data, and obtaining coherent accumulation results; a data cache module with an input end connected with the signal preprocessing FPGA module and an output end connected with a DSP data stream operation processing module; the data cache module includes a second SRAM storage unit and a third SRAM storage unit, which are respectively connected with the DSP data stream operation processing module, so as to realize sliding ping-pong processing of the coherent accumulation results. The application improves radar data rate and data processing real-time performance.

The application provides a data processing device, belonging to the technical field of wireless communication, and the device comprises: an FPGA chip and a data storage for storing air interface IQ data; the FPGA chip further comprises: a storage interface module; a frequency point digital down conversion module, which is used for sampling rate conversion on a digital signal input into the FPGA chip, obtaining the air interface IQ data, and storing the air interface IQ data into the data storage; a frequency point digital down conversion module, which is used for responding to a starting instruction of a central processing unit, extracting target air interface IQ data according to pre-configured data reading parameters, and performing sampling rate recovery on the target air interface IQ data to obtain output IQ data; and a post-processing module, which is used for processing the output IQ data and returning a processing result to the central processing unit. The application is based on a combined FPGA hardware acceleration and CPU non-real-time scheduling cooperative architecture as a whole, supports flexible expansion, simple maintenance, and unified storage and dynamic processing of multi-mode and multi-cell data.

This invention belongs to the field of data converter technology, specifically an ADC chip suitable for 128-beam direct sampling phased array receivers. This chip adopts a multi-channel parallel architecture, integrating 128 analog-to-digital conversion channels, each with a sampling rate ≥5 GSPS and a resolution of 12 bits. It includes a sample-and-hold circuit, a quantizer, a digital down-conversion module, and a high-speed serial interface. The clock distribution network uses an H-tree structure to provide a low-jitter sampling clock. The digital down-conversion module down-converts the sampled signal to baseband, and the high-speed serial interface enables high-speed data output. This chip supports direct sampling in the S / Ku / Ka bands, integrating 128 channels on a single chip, significantly simplifying the phased array receiver structure, reducing system complexity and power consumption, and adapting to the application requirements of fully digital phased array receivers.

This invention discloses a high-efficiency orthogonal demodulation method and apparatus based on envelope signals. The method, applied at a receiving end, includes: recovering the amplitude and phase based on the envelope information of the orthogonal modulation signal; subtracting the recovered phase from the phase of the low-frequency local oscillator signal used for digital down-conversion to obtain the phase of the baseband signal, thereby achieving equivalent digital down-conversion; and reconstructing the I and Q components of the baseband signal based on the recovered amplitude and the baseband signal phase. This invention significantly simplifies the calculation process and improves processing speed and efficiency.