25 results about "Numerically controlled oscillator" patented technology

The application discloses a numerically controlled oscillator based on double modulus accumulation and a method for improving frequency resolution, and the numerically controlled oscillator comprises a parameter configuration module, a carry processing module and a main phase accumulator. The parameter configuration module is used for configuring an integer part and a fractional part of a frequency control word based on a target output frequency, and the fractional part comprises a numerator modulus and a denominator modulus. The carry processing module is used for accumulating the fractional part of the frequency control word. On the basis of expanding an arithmetic logic bit width, a parallel pre-judgment architecture is adopted to generate a carry signal to the main phase accumulator according to the numerator modulus and the denominator modulus. The main phase accumulator is used for accumulating the integer part of the frequency control word and simultaneously updating a phase value according to the carry signal, so that a high-resolution frequency output is realized. The application decomposes the frequency control word into the integer part and the fractional part through the double modulus accumulation architecture, dynamically corrects the integer phase by using an accumulation carry mechanism of the fractional part, and realizes a frequency resolution much higher than that of a traditional structure without significantly increasing the bit width of the main phase accumulator.

A Costas ring utilizing pilot frequency self-adaptive sensitivity comprises a frequency mixer which carries out frequency mixing processing on an input base band to obtain an in-phase component and an orthogonal component; the phase discriminator is used for calculating the in-phase component and the quadrature component, generating a phase error and providing the phase error to the loop filter; the loop filter is used for carrying out filtering and frequency phase calculation on the phase error so as to control the phase increment of the numerical control oscillator; the numerically-controlled oscillator generates local carriers according to the phase increment and sends the local carriers to the mixer; the combiner is used for combining the in-phase component and the orthogonal component into an output base band, and the output base band is the final output of the Costas ring; the correlator is used for calculating the cross-correlation between the output baseband and the local pilot frequency, and sending the calculated cross-correlation to the power estimator; the delayer is used for providing delay of a pilot symbol length and carrying out symbol alignment before an output baseband and a local pilot are input into the power estimator; a power estimator that estimates and outputs a signal-to-noise ratio based on the cross-correlation; according to the method, the dynamic characteristic and the anti-noise capability of the Costas ring on carrier tracking are improved.

Apparatus and methods are disclosed. The apparatus includes a port to interface with a coaxial cable, the coaxial cable configured to transmit a signal; an impedance matching component configured to sufficiently match the signal; a diplexer configured to separate the signal into a separated signal; an RF analog to digital converter that is configured to convert the digital, separated signal into an analog signal; a numerically controlled oscillator (NCO) connected to a frequency translation block (FTB), wherein the FTB comprises a frequency selector module that is configured to translate the analog signal into four separated paths and configured to convert the frequency of each of the separated paths based on a modem center frequency to a frequency selected signal; and a modem configured to transmit the frequency selected signal to one or more user equipment.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

This invention discloses a gain-variable numerically controlled oscillator, comprising a current-controlled oscillator, a coarse-tuning control circuit, a mid-tuning control circuit, a fine-tuning control circuit, and a gain-adjustable circuit. The coarse-tuning, mid-tuning, and fine-tuning control circuits control the current flowing into the current-controlled oscillator to control its oscillation frequency. The gain-adjustable circuit controls the current in the fine-tuning control circuit to control the frequency gain of the numerically controlled oscillator. By controlling the current in the fine-tuning control circuit through the gain-adjustable circuit to control the frequency gain of the numerically controlled oscillator, the flexibility of the system is improved.

A digital signal generator includes a numerically controlled oscillator (NCO) configured to generate a modulated phase signal, and to convert the modulated phase signal into a sinusoidal output signal, and a pre-distortion module configured to adjust a phase of the phase-modulated signal prior to conversion to the sinusoidal output signal, and to adjust an amplitude of the sinusoidal output signal to obtain a pre-distorted digital output signal. The phase and amplitude adjustments are frequency dependent, and the pre-distortion module is configured to determine an instantaneous frequency of the NCO by computing a derivative of the modulated phase signal, and to address a memory table correlating the determined instantaneous frequency with the phase and amplitude adjustments.

The invention discloses a carrier tracking method, system, equipment and medium for a second-order frequency-locked loop assisted third-order phase-locked loop, and the method comprises the steps: receiving an in-phase integral value and a quadrature integral value outputted by a correlator, and carrying out the second-order frequency-locked loop tracking and the third-order phase-locked loop tracking based on the in-phase integral value and the quadrature integral value, the control quantity of the frequency-locked loop and the phase-locked loop is obtained; estimating a carrier-to-noise ratio and a carrier wave attitude of the received signal corresponding to the in-phase integral value and the orthogonal integral value in real time, and determining a first gain coefficient and a second gain coefficient according to the carrier-to-noise ratio and the carrier wave attitude; and generating a final control quantity of the carrier numerical control oscillator based on the control quantities of the frequency-locked loop and the phase-locked loop, the first gain coefficient and the second gain coefficient. By introducing a real-time sensing and dynamic gain control mechanism based on the carrier-to-noise ratio and the carrier wave fluctuation attitude, weighted fusion of contribution of the frequency-locked loop and the phase-locked loop is realized, and the robustness, the precision and the adaptive capacity of the carrier tracking loop under all working conditions can be improved.

A fractional divider, a digitally controlled oscillator, a phase-locked loop circuit are provided. The fractional divider includes a multi-modulus divider configured to generate a first divided clock based on an input clock and a sequence of division coefficients; a first flip-flop configured to generate a second divided clock based on the first divided clock; a second flip-flop configured to generate a third divided clock based on the first divided clock; a first multiplexer configured to select one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer configured to select one of the second divided clock and the third divided clock as a second output divided clock.

The invention provides a digital clock recovery system and method, and relates to the technical field of digital signal processing. The system comprises an interpolator, a timing error detector, a loop filter and a numerically controlled oscillator which form a feedback loop. Wherein the interpolator is a polynomial interpolator and is used for obtaining an interpolation result or an intermediate value by inquiring a pre-calculation module so as to reduce the operation complexity; a digitally controlled oscillator determines a base point and a fractional interval for interpolation by operating bits on an internal phase accumulator value to avoid division operations. The method comprises the following steps: performing polynomial interpolation by querying a pre-calculation module; detecting a timing error; filtering the error; and updating the timing information by performing a bit operation on the phase accumulator value. By means of the scheme, unification of high precision and low delay is achieved, loop performance is improved, and system resource consumption is reduced.

The present disclosure provides a method and an apparatus for tracking a direct sequence spread spectrum (DSSS) signal in a fractional Fourier domain (FRFD). The method includes the steps of: receiving an intermediate frequency (IF) DSSS signal; removing a Doppler frequency component by mixing with local sine and cosine waveforms generated by a carrier numerically controlled oscillator (NCO) to obtain in-phase (I) and quadra-phase (Q) carrier-stripped samples; performing code tracking and integration / dumping operations in the FRFD using chirp-signal modulation; discriminating carrier phase errors via I and Q prompt correlations and code chip errors via I and Q early / late correlations through carrier and code discriminators; filtering the discriminated errors through low-pass loop filters; and using filter outputs to generate carrier and code measurements while adjusting carrier and code NCOs for real-time tracking in subsequent epochs.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The present disclosure relates to electronic devices with a quadratic phase generation circuit. An electronic device can include wireless circuitry. The wireless circuitry can include a quadratic phase generator for an outputting a full interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator can include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator can receive a chirp count and a word length as inputs. The switch can be configured to switchably feed back one of two input values as a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator can output a full bandwidth chirp or a reduced bandwidth chirp. Bandwidth reduction can be achieved by scaling the two input values of the switch.

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities pl = ml / L and p2 = (L-ml) / L for selecting the first and second delay settings, where ml represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.

This application relates to the field of resolver technology and discloses an apparatus for recovering a carrier signal. A phase detector compares the phase error between the carrier signal and the first feedback signal output by a numerically controlled oscillator in the carrier signal to be recovered, obtaining a phase difference signal corresponding to the phase error. Then, a loop filter is used to filter the phase difference signal. The numerically controlled oscillator obtains the first feedback signal corresponding to the oscillation frequency. With the phase error between the first feedback signal and the carrier signal within a set range, the recovered carrier signal is determined based on the first feedback signal at the carrier signal output terminal, and this carrier signal is output. This avoids phase delay in the recovered carrier signal, improving the subsequent tracking effect of the envelope signal, thereby improving the accuracy of obtaining the position and speed information of the motor rotor. This application also discloses a method for recovering a carrier signal.

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities p1=m1 / L and p2=(L−m1) / L for selecting the first and second delay settings, where m1 represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.

The invention provides a clock data recovery method based on assistance of a lightweight equalizer, and a clock data recovery (CDR) process in digital signal processing of a receiving end comprises the following steps: carrying out interpolation on an input digital signal by using an interpolation filter, and outputting a resampling signal according to interpolation phase information provided by a numerically controlled oscillator; a feed-forward equalizer (FFE) is adopted to equalize the resampled signal, channel damage is preliminarily compensated, an output signal of the FFE is input to a single-tap noise eliminator, noise enhancement introduced by the FFE is suppressed by subtracting weighted adjacent symbol judgment errors, and a signal after noise elimination is obtained; the signal after noise elimination is input to a Mueller-Muller time sequence error detector (MM-TED), and time sequence error information is extracted; and the time sequence error information is filtered by the loop filter and then controls the numerical control oscillator, and the interpolation phase of the interpolation filter is adjusted to complete the CDR closed loop. According to the invention, noise enhancement caused by FFE in the CDR loop can be effectively suppressed, the time sequence error detection precision is significantly improved, and the transmission performance of the system is improved.

The application provides a satellite broadcast audio clock synchronization method, device, medium and product, relates to the technical field of digital clock synchronization, and the method comprises the steps of extracting a PCR time stamp from a satellite TS stream and decoding PCM audio data; calculating the difference between the PCR time stamp and a local numerical control oscillator counter as a time error value; inputting the time error value into a PI controller for proportional integral operation, and performing smoothing processing on the output of the PI controller through an IIR low-pass filter to obtain a frequency adjustment amount; writing the frequency adjustment amount into the local numerical control oscillator to adjust the frequency, so that the restored PCR clock signal is obtained through convergence; phase-locked frequency division of the restored PCR clock signal to generate an audio output clock signal, and synchronization output of the PCM audio data is realized based on the audio output clock signal. The problem that loud noise and broken noise are prone to occurring during master-backup switching due to large clock restoration jitter when the existing satellite broadcast receiving device operates independently without external synchronization source is solved.

Systems and techniques that facilitate amplitude-driven at-speed control of digital-to-analog converters are provided. In various embodiments, a system can comprise a digital-to-analog converter that is configured to generate an analog waveform based on a digital amplitude indicator sequence. In various aspects, the system can comprise a processor that is configured to reset an operating characteristic of the digital-to-analog converter in response to detection of a defined digital amplitude indicator subsequence in the digital amplitude indicator sequence. In various instances, the operating characteristic can be operation of a numerically controlled oscillator of the digital-to-analog converter.

The invention discloses a carrier loop based on integral discrete bilinear transformation of a loop filter and a tracking method, belongs to the technical field of satellite navigation receiver signal processing, and designs a loop filter core architecture in which a third-order frequency-locked loop and a third-order phase-locked loop are connected in parallel and cooperatively work. The filter receives a frequency error and a phase error which are obtained by calculating baseband I and Q signals, the frequency-locked loop branch circuit integrates the frequency error through a discrete integrator realized based on a bilinear transformation method and then converts the frequency error into a phase auxiliary quantity, and the phase auxiliary quantity and the output of the phase-locked loop branch circuit are added to jointly control the numerically-controlled oscillator. According to the invention, the high dynamic stress tolerance capability of the frequency-locked loop and the high-precision tracking advantage of the phase-locked loop are combined, so that the carrier loop can quickly and stably track high dynamic signals while keeping high tracking precision, and the reliability and performance of a receiver in a complex environment are remarkably improved.

This invention belongs to the field of signal synchronization technology in digital communication systems. It discloses a high-speed parallel bit synchronization loop design method based on FPGA. This invention adopts a collaborative design of parallel Farrow filter banks and grouped Gardner error detectors to significantly improve the throughput of bit synchronization loop calculation and overcome the limitation of FPGA clock rate on data processing. Through mean aggregation and k-fold phase error amortization mechanism, the multiple errors generated by parallel calculation are converged to a unified control word, which not only retains the efficiency of parallel architecture but also ensures loop stability. A parallel shift memory space and address pointer linkage mechanism is adopted, and the initial read position pointer is dynamically adjusted through feedback from a numerically controlled oscillator to achieve symbol phase deviation compensation without large-scale data copying. A 3*k depth parallel memory space is implemented through a shift register chain. With the multiplier multiplexing strategy, it is more friendly to hardware resources and easier to deploy in mainstream FPGA hardware.

A system and a method are disclosed for compensating a global navigation satellite system (GNSS) signal, including obtaining, by a correlation module, sample data which corresponds to a GNSS signal obtained based on an oscillator frequency of a crystal oscillator; obtaining, by the correlation module, aiding information which is determined based on information about the crystal oscillator; performing, by the correlation module, compensation processing on numerically-controlled oscillator (NCO) state data based on the aiding information, to obtain compensated NCO state data; performing, by the correlation module, correlation processing on the sample data based on the compensated NCO data; storing the compensated NCO state data in an NCO memory; and determining location information about a location of an electronic device corresponding to the correlation module based on the compensated sample data.

Apparatus and methods are disclosed. The apparatus includes a port to interface with a coaxial cable, the coaxial cable configured to transmit a signal; an impedance matching component configured to sufficiently match the signal; a diplexer configured to separate the signal into a separated signal; an RF analog to digital converter that is configured to convert the digital, separated signal into an analog signal; a numerically controlled oscillator (NCO) connected to a frequency translation block (FTB), wherein the FTB comprises a frequency selector module that is configured to translate the analog signal into four separated paths and configured to convert the frequency of each of the separated paths based on a modem center frequency to a frequency selected signal; and a modem configured to transmit the frequency selected signal to one or more user equipment.

This application relates to the field of satellite signal processing technology and discloses a method and system for intelligent identification and adaptive acquisition of multi-constellation satellite signals. The method includes: extracting the frequency trajectory matrix by performing a short-time Fourier transform on the received signal and calculating the Doppler frequency shift rate and acceleration; combining modulation domain features with the input of a multi-task neural network to output constellation category and interference type identification results; when a low-Earth orbit satellite is identified, predicting the carrier frequency offset trajectory and uncertainty through a long short-time memory network; adjusting the frequency of the numerically controlled oscillator in advance based on the prediction results and dynamically setting the search window and integration time; implementing corresponding anti-interference strategies for different interference types; and periodically monitoring signal quality indicators, triggering strategy upgrades when the performance improvement rate falls below a threshold. This application improves the signal acquisition success rate and tracking stability in a multi-constellation mixed environment.

The invention discloses an all-digital clock recovery method and system under a Baud rate sampling rate, and belongs to the technical field of optical fiber communication and digital signal processing. The method comprises the following steps: in a main path, sequentially carrying out overlapping blocking, finite field forward transformation, finite field filtering with a tap coefficient vector, finite field inverse transformation and point loss operation on an input baud rate sampling signal sequence, and generating a clock recovery output signal; and in the bypass, a timing phase error is calculated through a high-nonlinearity timing phase error detector according to the output signal, a phase control word is generated after loop filtering and numerical control oscillator processing, and then a corresponding tap coefficient vector is obtained through a lookup table and fed back to the main path. According to the full-digital clock recovery method, high-nonlinearity detection and finite field fast convolution filtering are combined, dependence on an analog-digital hybrid architecture is eliminated, and full-digital clock recovery with high precision, low jitter and low calculation complexity is achieved under Baud rate sampling.