51 results about "Numerically controlled oscillator" patented technology

The invention discloses a chirp signal-based timing synchronization system and method, belongs to the field of wireless communication, and can be used for large-scale timing drift compensation in a low-noise scene. The system comprises a timing error detection module, a numerical control oscillator module and an interpolation filter module which are cascaded, the timing error detection module is used for removing chirp single-tone spectrum peak positioning and timing errors, and the numerical control oscillator module is used for mapping the timing errors to stepping factors, updating phase register values and determining integer and decimal interpolation sampling points; the interpolation filter module resamples the chirp symbols by using interpolation sampling points to realize timing synchronization; the method comprises the steps of firstly initializing parameters, then calculating a timing error value of an upper chirp leading signal through a timing error detection module, then calculating a resampling parameter through a numerical control oscillator, and finally obtaining a timing synchronization result after the upper chirp signal is resampled through an interpolation filter module. According to the invention, the timing synchronization anti-noise performance and the estimation precision of the timing error value are improved.

The invention relates to the technical field of signal processing, and discloses a broadband receiving digital beam former. The broadband receiving digital beam former comprises a plurality of receiving channels and an accumulation module. Wherein each receiving channel comprises an analog-to-digital converter which is used for sampling an input analog signal and outputting a plurality of parallel first digital signals according to a time sequence; the digital mixer is used for multiplying the plurality of paths of first digital signals with two paths of orthogonal local oscillation signals on carrier frequency generated by the numerical control oscillator to obtain a plurality of paths of second digital signals; the digital time delayer module is used for carrying out time delay on the plurality of paths of second digital signals to obtain a plurality of paths of third digital signals; and the accumulation module is used for adding the plurality of paths of third digital signals to obtain two paths of output signals after beam forming. According to the scheme, the resource utilization rate in the broadband digital beam forming system can be effectively reduced.

The application discloses a numerically controlled oscillator based on double modulus accumulation and a method for improving frequency resolution, and the numerically controlled oscillator comprises a parameter configuration module, a carry processing module and a main phase accumulator. The parameter configuration module is used for configuring an integer part and a fractional part of a frequency control word based on a target output frequency, and the fractional part comprises a numerator modulus and a denominator modulus. The carry processing module is used for accumulating the fractional part of the frequency control word. On the basis of expanding an arithmetic logic bit width, a parallel pre-judgment architecture is adopted to generate a carry signal to the main phase accumulator according to the numerator modulus and the denominator modulus. The main phase accumulator is used for accumulating the integer part of the frequency control word and simultaneously updating a phase value according to the carry signal, so that a high-resolution frequency output is realized. The application decomposes the frequency control word into the integer part and the fractional part through the double modulus accumulation architecture, dynamically corrects the integer phase by using an accumulation carry mechanism of the fractional part, and realizes a frequency resolution much higher than that of a traditional structure without significantly increasing the bit width of the main phase accumulator.

A global navigation satellite system (GNSS) receiver for improving accuracy of a GNSS position estimation using a sigma-delta based fractional interpolation in a delay-locked loop is provided. The GNSS receiver includes a correlator, a code phase discriminator, a first loop filter, a code numerically controlled oscillator, and a sigma-delta modulator. The correlator correlates a GNSS C / A signal received from a satellite with a locally generated GNSS C / A code by multiplying the locally generated GNSS C / A code with incoming data samples. The code phase discriminator determines a delay between the locally generated GNSS C / A code and the GNSS C / A signal received from the satellite. The first loop filter averages the delay measured by the code phase discriminator. The code numerically controlled oscillator generates the local GNSS C / A code based on a unique CA code that corresponds to the satellite. The sigma-delta modulator imparts a fractional delay to the locally generated GNSS C / A code based on an output of the first loop filter.

A Costas ring utilizing pilot frequency self-adaptive sensitivity comprises a frequency mixer which carries out frequency mixing processing on an input base band to obtain an in-phase component and an orthogonal component; the phase discriminator is used for calculating the in-phase component and the quadrature component, generating a phase error and providing the phase error to the loop filter; the loop filter is used for carrying out filtering and frequency phase calculation on the phase error so as to control the phase increment of the numerical control oscillator; the numerically-controlled oscillator generates local carriers according to the phase increment and sends the local carriers to the mixer; the combiner is used for combining the in-phase component and the orthogonal component into an output base band, and the output base band is the final output of the Costas ring; the correlator is used for calculating the cross-correlation between the output baseband and the local pilot frequency, and sending the calculated cross-correlation to the power estimator; the delayer is used for providing delay of a pilot symbol length and carrying out symbol alignment before an output baseband and a local pilot are input into the power estimator; a power estimator that estimates and outputs a signal-to-noise ratio based on the cross-correlation; according to the method, the dynamic characteristic and the anti-noise capability of the Costas ring on carrier tracking are improved.

Apparatus and methods are disclosed. The apparatus includes a port to interface with a coaxial cable, the coaxial cable configured to transmit a signal; an impedance matching component configured to sufficiently match the signal; a diplexer configured to separate the signal into a separated signal; an RF analog to digital converter that is configured to convert the digital, separated signal into an analog signal; a numerically controlled oscillator (NCO) connected to a frequency translation block (FTB), wherein the FTB comprises a frequency selector module that is configured to translate the analog signal into four separated paths and configured to convert the frequency of each of the separated paths based on a modem center frequency to a frequency selected signal; and a modem configured to transmit the frequency selected signal to one or more user equipment.

A Signal-Agnostic Apparatus, System, and Method for Doppler Correction. In one embodiment, for the correction of significant Doppler shifts such as those present in signal transmissions involving satellites in low-earth orbit. The frequency locked loop apparatus and system for correcting Doppler frequency offset comprising an amplitude normalizer, a positive, a negative frequency band edge filter having a plurality of negative band edge coefficients, a positive or negative frequency content filter output for calculating a raw Doppler frequency offset, a leaky integrator, a zero-crossing counter, a plurality of locking filters, a plurality of tracking filters, an array, and a numerically controlled oscillator.

The present invention relates to the field of satellite navigation anti-jamming technology, and particularly relates to a method for implementing a tracking channel for GNSS anti-repeat-spoofing interference, including: preprocessing the radio frequency front-end signal to obtain an intermediate frequency signal; after successful acquisition, entering the tracking channel for normal tracking processing, and at the same time delaying the intermediate frequency signal by multiple preset steps to obtain multiple delayed signals; determining whether the carrier phase and code phase of the tracking channel are synchronized, and after the carrier phase and code phase are synchronized, performing a correlation operation on the replicated carrier sequence and pseudo-code sequence in the tracking channel to obtain a mixed sequence, and performing a correlation accumulation on the mixed sequence and the multiple delayed signals to obtain an energy sequence; obtaining the peak value in the energy sequence and comparing it with a threshold value, and when the peak value is greater than the threshold value, recording the position where the peak value is located, and accordingly adjusting the code numerically controlled oscillator in the tracking channel so that the tracking channel tracks the real signal. The present invention improves the effectiveness of the tracking channel in rejecting spoofing signals.

A method for all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratios belongs to the field of communication signal processing. The received signal sampling points are transformed into the frequency domain through DFT; the signal is matched filtered by point-by-point multiplication in the frequency domain; the symbol timing deviation of the signal is estimated using the Godard method, and the estimation result drives a numerically controlled oscillator after passing through a loop filter; the sliding of the sampling point and the frequency domain compensation of the timing deviation are determined by the phase accumulation and overflow of the numerically controlled oscillator, the frequency domain aliasing area and the length of the IDFT are calculated according to the oversampling ratio, and the signal sampling points are converted to the time domain through the IDFT to obtain the recovered symbols, thereby realizing all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratios and adapting to arbitrary oversampling ratios. The present invention is applicable to the field of communication signal processing and is used to expand the scope of application of single-carrier systems.

The invention provides a communication antenna steering control system and method, and relates to the technical field of antenna control, and the system comprises a parameter configuration module which is used for obtaining the initial state of a communication antenna, and collecting hardware state information in real time; the signal capturing and tracking module is used for configuring the initial frequency of the numerical control oscillator, starting the parallel correlator group to scan the carrier frequency and calculating frequency domain power spectrum data; and the angle calculation module is used for mapping the resampling phase difference and the baseline parameter into an azimuth angle based on a quaternion solution, and superposing IMU angular velocity data for dynamic compensation. According to the invention, a multi-stage phase-locked loop architecture, a dynamic threshold adaptive algorithm, cascade frequency division coefficient compensation and an FIR comb filter are adopted, so that high-sensitivity acquisition of signals in a broadband is realized; an extended Kalman filtering algorithm and a mechanical lag compensation algorithm are fused, so that the phase lag of the steering engine system is greatly reduced; and in combination with real-time fusion of the IMU angular velocity, the system can still keep relatively high pointing precision in a dynamic scene.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The present invention discloses a fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth. The fractional all-digital phase-locked loop includes a frequency and phase detector, a time-to-digital converter, a first subtractor, a second subtractor, a first adder, a first register, a first multiplier, an adaptive step size / bandwidth control algorithm module, an LMS algorithm module, a digital loop filter, a numerically controlled oscillator, a multi-mode frequency divider, and a ΣΔ modulator. The present invention improves the existing circuit structure, and optimizes the performance and innovates the structure of the circuit modules. The adaptive step size / bandwidth control algorithm of the present invention simultaneously adjusts the convergence step size of the LMS algorithm and the bandwidth of the phase-locked loop according to the state of the phase-locked loop, thereby achieving the characteristics of short LMS algorithm convergence time, good fractional spurious performance, short phase-locked loop locking time, and good in-band phase noise of the phase-locked loop.

This invention discloses a gain-variable numerically controlled oscillator, comprising a current-controlled oscillator, a coarse-tuning control circuit, a mid-tuning control circuit, a fine-tuning control circuit, and a gain-adjustable circuit. The coarse-tuning, mid-tuning, and fine-tuning control circuits control the current flowing into the current-controlled oscillator to control its oscillation frequency. The gain-adjustable circuit controls the current in the fine-tuning control circuit to control the frequency gain of the numerically controlled oscillator. By controlling the current in the fine-tuning control circuit through the gain-adjustable circuit to control the frequency gain of the numerically controlled oscillator, the flexibility of the system is improved.

A digital signal generator includes a numerically controlled oscillator (NCO) configured to generate a modulated phase signal, and to convert the modulated phase signal into a sinusoidal output signal, and a pre-distortion module configured to adjust a phase of the phase-modulated signal prior to conversion to the sinusoidal output signal, and to adjust an amplitude of the sinusoidal output signal to obtain a pre-distorted digital output signal. The phase and amplitude adjustments are frequency dependent, and the pre-distortion module is configured to determine an instantaneous frequency of the NCO by computing a derivative of the modulated phase signal, and to address a memory table correlating the determined instantaneous frequency with the phase and amplitude adjustments.

The invention provides a frequency offset tracking method and system, electronic equipment, a medium and a program product. The frequency offset tracking method comprises the following steps: tracking an SSB signal and a TRS signal; in response to the SSB signal and / or the TRS signal meeting a preset condition, acquiring a first frequency offset value of the SSB and determining a corresponding acquisition moment; determining a target proportion of a first frequency offset value of the SSB in the frequency offset estimation result according to the target difference value in response to the condition that the TRS signal is not received in the preset time period; and determining a frequency offset estimation result according to the first frequency offset value of the SSB and the target proportion. The proportion of the first frequency offset value of the SSB in the frequency offset estimation result is improved under the condition that the SSB signal is reliable, and the proportion of the first frequency offset value of the SSB in the frequency offset estimation result is reduced under the condition that the SSB signal is unreliable, so that the precision of the frequency offset estimation result is improved, the jitter of a voltage-controlled oscillator and a numerically-controlled oscillator is reduced, and the reliability of the frequency offset estimation result is improved. And the downlink decoding performance is improved.

The invention discloses a carrier tracking method, system, equipment and medium for a second-order frequency-locked loop assisted third-order phase-locked loop, and the method comprises the steps: receiving an in-phase integral value and a quadrature integral value outputted by a correlator, and carrying out the second-order frequency-locked loop tracking and the third-order phase-locked loop tracking based on the in-phase integral value and the quadrature integral value, the control quantity of the frequency-locked loop and the phase-locked loop is obtained; estimating a carrier-to-noise ratio and a carrier wave attitude of the received signal corresponding to the in-phase integral value and the orthogonal integral value in real time, and determining a first gain coefficient and a second gain coefficient according to the carrier-to-noise ratio and the carrier wave attitude; and generating a final control quantity of the carrier numerical control oscillator based on the control quantities of the frequency-locked loop and the phase-locked loop, the first gain coefficient and the second gain coefficient. By introducing a real-time sensing and dynamic gain control mechanism based on the carrier-to-noise ratio and the carrier wave fluctuation attitude, weighted fusion of contribution of the frequency-locked loop and the phase-locked loop is realized, and the robustness, the precision and the adaptive capacity of the carrier tracking loop under all working conditions can be improved.

A fractional divider, a digitally controlled oscillator, a phase-locked loop circuit are provided. The fractional divider includes a multi-modulus divider configured to generate a first divided clock based on an input clock and a sequence of division coefficients; a first flip-flop configured to generate a second divided clock based on the first divided clock; a second flip-flop configured to generate a third divided clock based on the first divided clock; a first multiplexer configured to select one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer configured to select one of the second divided clock and the third divided clock as a second output divided clock.

The invention provides a digital clock recovery system and method, and relates to the technical field of digital signal processing. The system comprises an interpolator, a timing error detector, a loop filter and a numerically controlled oscillator which form a feedback loop. Wherein the interpolator is a polynomial interpolator and is used for obtaining an interpolation result or an intermediate value by inquiring a pre-calculation module so as to reduce the operation complexity; a digitally controlled oscillator determines a base point and a fractional interval for interpolation by operating bits on an internal phase accumulator value to avoid division operations. The method comprises the following steps: performing polynomial interpolation by querying a pre-calculation module; detecting a timing error; filtering the error; and updating the timing information by performing a bit operation on the phase accumulator value. By means of the scheme, unification of high precision and low delay is achieved, loop performance is improved, and system resource consumption is reduced.

The invention discloses a numerical control oscillator tuning curve fitting method for a frequency synthesizer, the frequency synthesizer, equipment and a medium. The method comprises the following steps: modeling a tuning curve of the numerically controlled oscillator by adopting a parameterized tuning model, wherein the model comprises learnable fitting parameters; in the frequency hopping process of the phase-locked loop, predicting an estimation control word OTWesti corresponding to the target frequency based on the current fitting parameter of the model; acquiring an actual control word OTWreal when the phase-locked loop works stably; and on the basis of a prediction error between the actual control word and the estimated control word, a stochastic gradient descent algorithm is adopted to update fitting parameters of the model online. Through continuous iterative optimization, the model can accurately fit the nonlinear behavior of the numerically controlled oscillator, thereby realizing rapid and accurate frequency locking. According to the scheme provided by the invention, the calculation overhead is low, on-chip integration is easy, and the frequency switching capability of the frequency synthesizer can be remarkably improved.

The invention relates to a carrier synchronization method of a receiver, a receiver system, a medium, a product and equipment, and the method comprises the steps: carrying out the correction processing of carrier frequency offset in the receiver based on a plurality of numerical control frequency control words of a numerical control oscillator in the receiver under the condition that a loop of the receiver is stable, as the frequency control words of the numerical control oscillator can reflect the carrier frequency offset of the receiver, carrier frequency offset correction is carried out based on the multiple numerical control frequency control words, the frequency jitter of the numerical control oscillator can be eliminated, the carrier frequency offset of signals in the receiver is reduced and corrected fundamentally, and the stability of carrier synchronization is improved.

The embodiment of the invention provides a wireless communication method and equipment. AMP equipment can decode a first signal according to a third signal obtained by performing cross modulation or intermodulation processing on the first signal and a second signal; and the AMP equipment does not need to generate an accurate oscillation signal according to an oscillator (such as a crystal oscillator and a numerical control oscillator) to perform down-conversion processing to obtain a signal for decoding, so that the power consumption and the cost of the AMP equipment can be further reduced. The wireless communication method comprises the following steps: the AMP equipment receives a first signal and a second signal; the AMP device performs intermodulation or intermodulation processing on the first signal and the second signal to obtain a third signal; and the AMP device decodes the first signal according to the third signal.

The present disclosure provides a method and an apparatus for tracking a direct sequence spread spectrum (DSSS) signal in a fractional Fourier domain (FRFD). The method includes the steps of: receiving an intermediate frequency (IF) DSSS signal; removing a Doppler frequency component by mixing with local sine and cosine waveforms generated by a carrier numerically controlled oscillator (NCO) to obtain in-phase (I) and quadra-phase (Q) carrier-stripped samples; performing code tracking and integration / dumping operations in the FRFD using chirp-signal modulation; discriminating carrier phase errors via I and Q prompt correlations and code chip errors via I and Q early / late correlations through carrier and code discriminators; filtering the discriminated errors through low-pass loop filters; and using filter outputs to generate carrier and code measurements while adjusting carrier and code NCOs for real-time tracking in subsequent epochs.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The present disclosure relates to electronic devices with a quadratic phase generation circuit. An electronic device can include wireless circuitry. The wireless circuitry can include a quadratic phase generator for an outputting a full interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator can include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator can receive a chirp count and a word length as inputs. The switch can be configured to switchably feed back one of two input values as a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator can output a full bandwidth chirp or a reduced bandwidth chirp. Bandwidth reduction can be achieved by scaling the two input values of the switch.

The invention relates to a fractional frequency division all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator, and belongs to the field of radio frequency integrated circuit design. The phase-locked loop adopts an all-digital architecture and comprises a time-to-digital converter (TDC), a digital loop filter (DLF), a digital controlled oscillator (DCO), a programmable frequency divider (MMD) and a parallel four-order Sigma-delta modulator. A phase-locked loop adopts an all-digital closed-loop feedback structure, the phase difference between a reference signal and a feedback signal is detected through a TDC without dead-zone influence, DCO output is fed back to a loop after being subjected to MMD frequency division, parallel four-order Sigma-delta modulators dynamically control the frequency division ratio of MMD, a bit adder and an accumulator of each stage of modulator are split to obtain four low-order adders for parallel computing, and the low-order adders are used for parallel computing. The signal-to-noise ratio and the noise shaping capability of the modulator are improved, and quantization noise and fractional spurious are suppressed by using the high-order noise shaping characteristic.

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities pl = ml / L and p2 = (L-ml) / L for selecting the first and second delay settings, where ml represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.

The present invention proposes an all-digital phase-locked loop architecture based on a phase discrimination algorithm, which includes an interpolation-type automatic frequency calibration Ip-AFC module, a frequency calibration loop DFTFAL module based on discrete Fourier transform, a digital loop filter DLF, a numerically controlled oscillator DCO module, a programmable divider PGD, and an interpolator DPI. This architecture obtains a pre-tuning word corresponding to the phase-locked loop frequency control word through an automatic frequency calibration module based on an interpolation algorithm, enabling the phase-locked loop to quickly lock. By embedding an interpolation-type frequency prediction loop, the output frequency of the numerically controlled oscillator is compared with the reference frequency to obtain a frequency difference, thereby obtaining a corresponding calibration oscillation tuning control word, making the phase-locked loop lock more accurately and reducing loop noise.

Method and waveform generator for generating at least two signals. The signals are generated by separate channels, with each channel having a numerically controlled oscillator and a digital envelope generator, whose outputs are multiplied and fed to a digital-analog converter. The signal from the digital-analog converter is multiplied with the signal from a local oscillator for generating pulses with an up-converted carrier. The phases of the numerically controlled oscillators are changed between pulses in order to adjust the phase of the up-converted carrier. This allows to generate pulses where the up-converted carriers have a defined phase relationship.

This application relates to the field of resolver technology and discloses an apparatus for recovering a carrier signal. A phase detector compares the phase error between the carrier signal and the first feedback signal output by a numerically controlled oscillator in the carrier signal to be recovered, obtaining a phase difference signal corresponding to the phase error. Then, a loop filter is used to filter the phase difference signal. The numerically controlled oscillator obtains the first feedback signal corresponding to the oscillation frequency. With the phase error between the first feedback signal and the carrier signal within a set range, the recovered carrier signal is determined based on the first feedback signal at the carrier signal output terminal, and this carrier signal is output. This avoids phase delay in the recovered carrier signal, improving the subsequent tracking effect of the envelope signal, thereby improving the accuracy of obtaining the position and speed information of the motor rotor. This application also discloses a method for recovering a carrier signal.

The application relates to the field of digital signal processing, in particular to a symbol synchronization method suitable for a wired communication system of THP, a feedforward transversal filter FFE is used to pre-process baseband receiving symbols, phase discrimination processing is carried out on the symbols processed by the FFE, in the phase discrimination processing part, an estimated value of the current receiving symbol is obtained through modulo operation and decision, an error between the receiving symbol and the estimated value is calculated, threshold comparison and compensation are carried out on the error, sampling phase deviation information is obtained by correlating the compensated error with an expected symbol; finally, the sampling deviation information is processed by using a direct path and an integral path of a loop filter, and is used for controlling a numerically controlled oscillator NCO to adjust a next sampling position. The sampling phase error information is processed in a linear domain, the influence of nonlinear modulo operation of THP on the phase discrimination algorithm is avoided, the stability of the symbol synchronization method is improved, and low calculation complexity is maintained.