383 results about "Numerically controlled oscillator" patented technology

A digital phase locked loop (PLL) frequency synthesizer includes a 1-bit numerically controlled oscillator (NCO) to negate the requirement that a VCO frequency be an integer multiple of its reference frequency. Thus, in accordance with the principles of the present invention, a direct digital synthesizer (DDS) or numerically controlled oscillator (NCO) is used to form a frequency divider in a feedback path of a PLL. Thus, a synthesizer with fine frequency control and very fast settling time is disclosed. The conventional integer-ratio relationship between the reference frequency fREF and the synthesized output frequency signal fVCO is overcome by replacement of a conventional VCO divider in a feedback path of a digital PLL with a 1-bit NCO. This allows the reference frequency fREF to be greater than the channel spacing, i.e., the channel spacing can be smaller than the reference frequency fREF. Thus, a much quicker settling time and improved VCO phase noise are provided, either of which results in a significant improvement in the performance of virtually any communications system.

The invention relates to a rapid locking method for a full digital phase-locked loop, which is used for locking the frequency of the full digital phase-locked loop comprising a phase detection discriminator, a time-to-digit converter, a digital filter, a digital controlled oscillator and a frequency divider in a short time. The method is characterized by comprising the following steps: finding a control word controlling the frequency of the digital controlled oscillator by a designed algorithm; dividing the frequency of a clock output by the digital controlled oscillator which is controlled bythe control word to obtain a divided-frequency clock with the frequency approximate to a reference clock frequency; and then, controlling the digital controlled oscillator to lock based on a phase difference between the reference clock and the divided-frequency clock which are distinguished by the phase detection discriminator. The full digital phase-locked loop is provided with a rapid frequencycapture loop and a phase-locked loop which alternately work, i.e. firstly, the rapid frequency capture loop finishes frequency capture, and then, the phase-locked loop finishes accurate locking.

The invention discloses a fully-digital direct sequence spread spectrum communication system and a rapid pseudo code capturing method thereof. A digital signal is processed by using an FPGA (Field Programmable Gate Array) which comprises a pseudo code capturing module, a sampling signal of an ADC (Analog To Digital Converter) is subjected to frequency mixing with a signal of a local carrier NCO (Numerically Controlled Oscillator) and filtered to obtain a baseband signal, residual carrier Doppler frequency is eliminated from the baseband signal by adopting a differential multiplying mode, thus the phase deviation of a receiving signal and a local pseudo code is further obtained through an FFT (Fast Fourier Transform) algorithm without scanning on a carrier frequency domain; and when the phase deviation of the pseudo code is obtained, a local pseudo code phase is modified and is subjected to correlation degree of dissociation with the receiving signal, and the carrier Doppler frequency is figured out by using the FFT algorithm, and is compensated to a carrier NCO and a pseudo code NCO, thus carrier frequency capturing and pseudo code capturing are realized.

An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (K_DCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δf_max) in the oscillating frequency; (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (d_k^TF) can then be applied to a control input of switchable devices within the digitally controlled oscillator; and (3) a non-linear differential term (187, 331) can be used to expedite correction of the digitally controlled oscillator when large phase error changes (335) occur.

One embodiment of the invention discloses a device and a method of phase error correction, comprising: a phase discriminator, used for latching a controlled phase position sent by the numerical controlled oscillator when a line synchronizing signal and a field synchronizing signal arrive, and comparing with the moment reference phase position, and outputting phase error; a loop filter, used for receiving the phase error sent by the phase discriminator, performing low-pass filtering, and obtaining a frequency control word signal; a numerical controlled oscillator, used for receiving the frequency control word signal sent by the loop filter, generating controlled phase signal, wherein, the phase signal is transmitted to the phase discriminator, and the high position part of the phase signal is transmitted to the lookup table; a lookup table, used for obtaining a quantized value of corresponding sine and cosine functions according to the high position part of the phase signal. The invention eliminates long term accumulation of DDS to frequency quantized error in a complex video signal coder, cuts the phase error with large granularity into uniform phase error with small granularity, and distributes the phase error uniformly on the time.

The invention discloses a digital signal down-conversion processing system based on an MIMO real-time testing platform, pertaining to the technical field of digital signal processing. The system comprises four DDC modules and each DDC module consists of four independent digital signal down-conversion processing channels. Each channel consists of an analog-to-digital converter, a digital quarter mixer and a digital decimation filter set. The digital quarter mixer consists of a digital controlled oscillator and two paths of multipliers, and the digital controlled oscillator is respectively connected with the two multipliers; the digital decimation filter set consists of two groups of filters with complete same parameters and each filter group respectively comprises a CIC decimation filter, a CFIR compensation filter and a PFIR matched filter which are connected in sequence. The system has good expansibility and modularization and can meet the requirements of real-time and high-speed performance.

A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The 1-bit precision NCO includes an adder and a phase accumulator register which is clocked by a master clock signal. A two-input multiplexer has a single bit symbol value to generate BFSK, or larger input multiplexers can be implemented to provide M-ary FSK. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. Alternatively, the intermediate frequency may be arrived at without the need for upconversion by directly utilizing a harmonic alias at a desired IF frequency. The undesirable portion of the upconverted signal may be suppressed using I/Q image rejection, and/or an appropriate bandpass filter may be used. A band limited, hard limited signal at the high IF is presented to the 1-bit precision demodulator as a receive IF signal, which is treated as a 1-bit quantization of the signal. The receive IF signal is digitally down-converted to a low IF signal to produce an alias signal at the low IF frequency.

A device for fast transition from preamble synchronization of a received baseband signal to demodulation of the received baseband signal may include a baseband chip tracking loop to generate an offset tracking value to track any initial chip phase offset and Doppler-caused baseband chip frequency drift associated with the received baseband signal. The device may also include a numerical controlled oscillator to correct any Doppler-caused phase rotation associated with the received signal. The device may additionally include a preamble synchronization unit to detect a preamble of the received baseband signal, and to measure a chip phase offset and a baseband Doppler frequency shift associated with the received baseband signal. The chip phase offset may be used to set an initial chip phase offset value of the chip tracking loop so that the chip tracking loop starts with approximately a zero pull-in error. The baseband Doppler frequency shift may be used to set initial frequency offset values in the chip tracking loop and the numerical controlled oscillator so that both start with substantially near-zero offset errors for substantially immediate demodulation of the received signal. The device may further include an output device to output the data demodulated from the received baseband signal.

The invention discloses a method for realizing a software phase-locked loop with an unfixed sampling frequency. The method comprises the following steps: firstly adopting an analog phase-locked loop digital controlled oscillator of the DSP period counter to obtain digital controlled oscillator output signals; then working out the phase error between the mains voltage and a reference signals in the DQ-transformation phase demodulation mode by using the digital controlled oscillator output signals as the reference signals; and establishing a closed loop transfer function secular equation of a phase-locked loop system and determining the parameters of the designed loop filter based on the digital controlled oscillator output signals and the phase error between the mains voltage and the reference signals. The invention can maintain the fixed number of the sampling points in the primitive period, and is used for repeatedly controlling various grid-connected converting devices, such as active electric filters, new energy-powered grid-connected converters and the like. By adopting the DQ-transformation phase demodulation mode, the invention can well inhibit the harmonic and unbalanced mains, resist the fluctuation of the mains voltage, and ensure the reliable operation of the phase-locked loop under the conditions of multiple mains voltage zero passage, voltage harmonics, voltage fluctuation and mains voltage imbalance.

A estimating method of OFDM communication system carrier frequency excursion, in original place of systems frame adds two training sequence that were designed especially, using the result of cross correlation of class A training sequence estimates original value of frequency excursion, namely to make rough estimation of frequency excursion, then using class B makes autocorrelation, gained frequency deviation signal was estimated precisely in small scale, namely to make frequency excursion precise estimation, then make two estimating value combined to get precise value of system frequency excursion, finally control numerical control oscillator to produce rectify value of system frequency excursion, and put it to multiply with time domain data to make compensation of frequency excursion.

A numerically-controlled phase-lock loop with input clock dependent ratio adjustment provides for narrower-bandwidth loops that lock to a wide range of frequencies and/or operation with an absent or degraded input timing reference. A timing reference characteristic detector determines an input frequency range of the input timing reference signal, the data type of the timing reference, and/or whether a timing reference signal of sufficient quality is present. A numerically controlled oscillator is controlled by a numeric ratio that is adjusted to provide the desired clock frequency output in conformity with the detected frequency range and/or data type. If the timing reference signal is absent or degraded, then the numeric ratio can be set to a fixed value or a local timing reference can be applied in order to generate the desired clock output frequency.

The invention discloses a multi-channel digital down-conversion device, which comprises a signal acquisition module, an m*n-way switch matrix, a digital down-conversion module and an FPGA controller. Firstly, the FPGA controller controls the digital down-conversion module and determines the working mode of the digital down-conversion module, such as a narrow-band parallel mode, an orthogonal joint mode and an orthogonal alternative joint mode; secondly, the FPGA controller controls the input/output connection state of the m*n-way switch matrix to further finish the paired connection between an m-channel signal acquisition channel and a digital down-conversion channel so as to carry out demodulation according to different down-conversion working modes; and thirdly, the FPGA controller controls each digital down-converter and writes the index parameters of a numerical control oscillator, the index parameters of a digital extractor and the index parameters of a low-pass filter into corresponding internal registers so that each digital down-converter can be independently programmed. The digital down-conversion device of the invention can realize digital down-conversion processing of various band widths and various index parameters for multiple-channel digital intermediate-frequency signals, ensuring better real-time performance.

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

The present invention provides a novel direct digital synthesis system architecture which employs a numerically-controlled oscillator (NCO), some decoding logic, and a sine-weighted digital-to-analog converter (DAC) with significantly fewer output values required than conventional DDS systems to provide improved spurious performance (relative to the number of bits of resolution required of the DAC), extended frequency of operation, reduced chip area, and reduced power consumption relative to conventional DDS techniques. The output of the decoder is input to a sine-weighted digital-to-analog converter (DAC). Importantly, the sine-weighted DAC outputs a constant number of samples per cycle using a relatively few number of taps. Although there are significantly fewer taps in the sine-weighted DAC as compared to the linear DAC in conventional DDS systems, each tap of the sine-weighted DAC has a high degree of accuracy, e.g., 16-18 bits. Accordingly, a constant number of sample values are repetitively used in the stepped approximation of a sine wave, regardless of output frequency, significantly reducing the number of discrete output values that a digital-to-analog converter (DAC) is otherwise required to produce. Unlike conventional direct digital synthesis (DDS) architectures which use linear digital-to-analog converters having many bits of resolution, the present invention provides a sine-weighted digital-to-analog converter having relatively few taps to produce a constant number of samples per cycle, eliminating the conventional need for a memory-based sine wave look-up table.

A carrier tracking circuit includes a first phase adjustment circuit coupled to an input of a delay element and a second phase adjustment circuit coupled to an output of the delay element. A phase correction circuit is coupled to output of the delay element is operable to generate a phase adjustment value based upon a data symbol output from the delay element. The phase correction circuit includes a double phase correction circuit to prevent double application of the same phase adjustment value to a symbol by both the first and second phase adjustment circuits. The carrier tracking circuit may be used in OFDM communications systems with each data symbol being an OFDM symbol and with the delay element being an FFT. The carrier tracker circuit also may include a feed forward circuit for correcting the phase error of a given data symbol using a phase error generated from that symbol.

The invention relates to a full digital phase-locked loop applying a rapid frequency capture method for locking the frequency of the full digital phase-locked loop comprising a phase detection discriminator, a time-to-digit converter, a digital filter, a digital controlled oscillator and a frequency divider in a short time. The full digital phase-locked loop is characterized by comprising the following steps: finding a control word controlling the frequency of the digital controlled oscillator by a designed algorithm; and dividing a frequency output by the digital controlled oscillator which is controlled by the control word to obtain a divided-frequency clock with the frequency approximate to a reference clock frequency. The full digital phase-locked loop is provided with a rapid frequency capture loop and a phase-locked loop which alternately work, i.e. firstly, the rapid frequency capture loop finishes frequency capture, and then, the phase-locked loop finishes accurate locking.

One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error.

A satellite-based positioning receiver includes processing channels, each processing channel being associated with a respective satellite from among N satellites, and an extended Kalman filter for performing a vector tracking for the set of satellites using signals received from the satellites. The extended Kalman filter performs a resetting on the basis of the phase error and code error received directly from the phase and code discriminators, of each channel, and the receiver includes first means for calculating the code-wise and carrier-wise control signals for the said code phase and carrier phase numerically-controlled oscillators, on the basis of data provided by the said extended Kalman filter, for each channel.

The invention discloses a method and a system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in an FPGA. The system comprises the components of a plurality of ADC sampling chips, a high-speed ADC data receiving module, an over-clock processing module, a global clock module, a local numerical control oscillator and a multichannel digital decimation filter. The designed working frequency of the traditional FPGA is hard to exceed 200MHz. According to the method and the system, a numerical control oscillator (NCO) and the digital decimation filter as core parts in orthogonal down conversion are improved; furthermore through reasonably restraining layout and wiring of the FPGA, highest sampling rate above 500Msps and output baseband data rate above 125MHz can be ensured on a common FPGA device. Furthermore the method and the device can support simultaneous parallel sampling of multiple paths of ADC data, thereby adapting with a multichannel data receiving occasion.

The invention provides a method for capturing, tracking and receiving a Beidou signal of a high-dynamic movement carrier. Through the adoption of the method, a satellite signal can be quickly captured and tracked, the capturing time is shortened, the tracking reliability is ensured, and the signal loss is avoided. The method comprises the following steps: Step 1, capturing a satellite signal of the high-dynamic movement carrier, using repeated uncorrelated accumulation and Tong detection, and obtaining a rough carrier frequency and a pseudo code phase of a received signal; Step 2, using a second-order FLL (frequency locked loop) for tracking the received signal during initial tracking so as to obtain frequency tracking errors, and at the same time, selecting a frequency tracking error for feeding back and rectifying the output carrier wave frequency of a numerically controlled oscillator (NCO) of the FLL by an output selector; Step 3, when the frequency tracking error is smaller than a preset threshold, using a third-order PLL for tracking so as to obtain phase tracking errors, at the same time, selecting the phase tracking error for feeding back and rectifying the output phase of the numerically controlled oscillator (NCO) of the FLL by the output selector, and realizing accurate tracking; Step 4, when the phase tracking error of the third-order PLL is greater than the preset threshold, returning to the Step 2 to perform the second-order FLL tracking, and completing carrier tracking.

A method and system for modulating data onto a carrier signal in a plurality of channels, each of the channels having a channel bandwidth, can be created for use in any two-way satellite communication system or other wireless communication application where frequency hopping with or without Doppler compensation is desired. The system preferably includes a digital modulator that outputs a modulated baseband signal, an intermediate frequency modulator that receives the modulated baseband signal and outputs an intermediate frequency signal derived from the modulated baseband signal, a frequency synthesizing system that outputs a synthesized intermediate frequency signal to the intermediate frequency modulator, and a circuit (numerically controlled oscillator) connected to the digital modulator which provides a signal to the digital modulator. This signal has a frequency including an offset that allows the frequency synthesizing system and intermediate frequency modulator to make frequency steps equal to the channel bandwidth. The offset can also include a small offset that compensates for the Doppler effect.