7492 results about "Phase-locked loop" patented technology

Controls for an optical scanner, such as a single fiber scanning endoscope (SFSE) that includes a resonating optical fiber and a single photodetector to produce large field of view, high-resolution images. A nonlinear control scheme with feedback linearization is employed in one type of control to accurately produce a desired scan. Open loop and closed loops controllers are applied to the nonlinear optical scanner of the SFSE. A closed loop control (no model) uses either phase locked loop and PID controllers, or a dual-phase lock-in amplifier and two PIDs for each axis controlled. Other forms of the control that employ a model use a frequency space tracking control, an error space tracking control, feedback linearizing controls, an adaptive control, and a sliding mode control.

A synchronous bi-directional active power conditioning system (11) suitable for wide variable frequency systems or active loads such as adjustable speed drives which require variable voltage variable frequency power management systems is disclosed. Common power electronics building blocks (100, 200) (both hardware and software modular blocks) are presented which can be used for AC-DC, DC-AC individually or cascaded together for AC-DC-AC power conversion suitable for variable voltage and/or wide variable frequency power management systems. A common control software building block (2, 5) includes a digital control strategy/algorithm and digital phase lock loop method and apparatus which are developed and implemented in a digital environment to provide gating patterns for the switching elements (3, 6) of the common power-pass modular power electronics building blocks (100, 200).

A system and method for synchronizing a local clock to a reference clock using a linear model of the error between the local clock and the reference clock is disclosed. In one embodiment, a direct smoothing process is used in conjunction with the linear model to estimate a frequency offset by which the frequency of an oscillator of the local clock is adjusted. Also disclosed herein is a phased-lock loop (PLL) adapted to synchronize a local clock with a reference clock using the direct smoothing process, as well as a system implementing the PLL for timing the playout of data received from a transmitter.

A phase locked loop includes at least one control circuit, where a voltage-controlled oscillator provides an output frequency which is arranged to strive to follow an input frequency. The phase locked loop also includes an outer, slow, negative feedback control circuit, having the input frequency as a setpoint, the output frequency as a process value and an outer output signal. The phase locked loop also includes an inner, fast, negative feedback control circuit, having the sum of a reference frequency from a stable oscillator and the outer output signal as a setpoint, the output frequency as the process value and an inner output signal for controlling the voltage controlled oscillator.

A millimeter wave pulsed radar system includes a radar synthesizer having a voltage controlled oscillator/phase locked loop (VCO/PLL) circuit, direct digital synthesizer (DDS) circuit and quadrature modulator circuit that are operative to generate an intermediate frequency local oscillator signal (IF/LO signal). A radar transceiver is operative with the radar synthesizer for receiving the IF/LO signal. A transmitter section has a frequency multiplier that multiplies the IF/LO signal up to a millimeter wave (MMW) radar signal and a receiver section and includes a direct conversion mixer that receives a MMW radar signal and the IF/LO signal to produce I/Q baseband signals that are later digitized and processed.

Plasma distribution is controlled in a plasma reactor by controlling the phase difference between opposing RF electrodes, in accordance with a desired or user-selected phase difference, by a phase-lock feedback control loop.

This invention relates to opto-electronic systems using semiconductor lasers driven by feedback control circuits that control the laser's optical phase and frequency. Feedback control provides a means for coherent phased laser array operation and reduced phase noise. Systems and methods to coherently combine a multiplicity of lasers driven to provide high power coherent outputs with tailored spectral and wavefront characteristics are disclosed. Systems of improving the phase noise characteristics of one or more semiconductor lasers are further disclosed.

The invention discloses a method for improving the estimation accuracy of the rotor position of a permanent magnet synchronous motor. The method comprises the following steps: on the basis of realizing estimation of the rotor position of the permanent magnet synchronous motor by utilizing a pulse-shake high frequency voltage injection method, processing the extracted position estimation error function, eliminating a second harmonic component introduced due to asymmetric motor parameters, so as to obtain a processed position estimation error function, then establishing a phase-locked loop, and adjusting the phase-locked loop to be 0, thus obtaining estimated rotor speed and estimated rotor position. The method disclosed by the invention can effectively inhibit position estimation second harmonic error caused by the asymmetric motor parameters, and the performance of a control system without a position sensor can be improved.

A power inverter system includes a DC to AC inverter configured to convert DC voltage from a DC power source to AC voltage. A DC link couples the DC power source and the inverter. An inverter pre-charger operates to pre-charge the inverter to achieve a desired DC link voltage prior to connecting the power inverter system to an AC power grid. A phased lock loop synchronizes the pre-charged inverter to the AC power grid prior to connecting the power inverter system to the AC power grid. The pre-charged inverter regulates the DC link voltage to about the minimum voltage level that allows control of AC grid currents via the inverter subsequent to connecting the power inverter system to the AC grid. The inverter operates in a maximum power point tracking control mode only subsequent to a first voltage transient caused by connecting the DC power source to energize the power inverter system.

A method and apparatus for anti-islanding of distributed power generation systems having an inverter comprising a phase locked loop (PLL), a phase shift generator for injecting a phase shift into the PLL during at least one sample period, and a phase error signature monitor for monitoring at least one phase error response of the PLL during the at least one sample period.

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

A power system having a phase locked loop (PLL) with a notch filter for synchronous reference frame sequence separation. The notch filter includes a generalized integrator tuned to the notch frequency. The output of the generalized integrator is summed with the filter input signal and the output of the summer is fed back to the integrator input. In one embodiment, the notch filter is programmable by a control signal generated in response to the filter output signal, thereby causing the filter to self-regulate to a frequency related to the PLL input signal. Illustrative power systems include active VAR generators and active rectifiers. One or more additional notch filters may be used to remove harmonic components from derived synchronous reference frame sequence components.

Aspects of the disclosure relate generally to a circuit for sustaining an radio frequency (RF) modulated optical signal. The circuit may comprise a self injection locking component having a fiber optic delay line over which a portion of the optical signal propagates. The circuit may also comprise a self phase locked loop component having at least two fiber optic cables having different lengths and over which another portion of the optical signal propagates and a phase detector coupled to the at least two fiber optic cables and configured to determine a phase difference between the signals propagating over one of the respective fiber optic cables. The circuit may further comprise a voltage controlled oscillator configured to generate a stable oscillating signal in response to signals generated by each of the self injection locking and self phase locked loop components, the stable oscillating signal being configured to sustain the optical signal.

Servo writing a disk of a disk drive is disclosed. A phase locked loop (PLL) is synchronized to first sectors previously written on a first track, and second sectors are written to a second track using the PLL, wherein a plurality of phase errors corresponding to the second sectors are saved. A correction value is computed corresponding to a selected one of the second sectors, wherein the correction value is computed in response to a plurality of the phase errors generated for a plurality of the second sectors leading the selected sector. The PLL is synchronized to the second sectors using the correction value, a third sector is written to a third track using the PLL, and a phase error is saved corresponding to the third sector.

A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog/RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.

Measurements made by a rotating sensor on a bottomhole assembly are used to determine the toolface angle of the BHA. The method includes using a phase locked loop (PLL) to determine a phase difference between the sensor output and a reference signal.

A low-cost sine-wave drive for a 3-phase permanent magnet synchronous AC machines (PMSM) in open-loop control is based on the measurements of two linear Hall sensors. The two Hall sensors are excited by a magnetic ring with the same pole number as the PMSM rotor magnet and sinusoidal flux distributions. The output signals of the Hall sensors are unified through a two-phase-type phase-lock-loop in order to reduce the impact of the sensor mounting non-uniformity during mass production. The peak torque and speed of motor is simply controlled by adjusting the amplitude of pulse-width-modulation carrier. Smooth torque control is achieved due to sinusoidal 3-phase currents. Such a simple sine-wave drive can be achieved with or without the assistance of a micro-controller unit (MCU). No current sensor is required for the motor phase current detection. This motor can be used in industrial applications where there is no strict requirement on torque response and constant speed control of PMSM machines.

The present invention provides an improved method and apparatus for independently controlling phase and frequency using an oscillator having a plurality of stages in combination with a phase selector within a digitally controlled phase-locked loop, preferably, a read phase locked loop. The present invention provides a digitally controlled variable phase of the read timing loop in read channel integrated circuits associated with data storage devices. The phase selector has a digitally controlled fine interpolator with 12 states for further fine interpolation between at least two multiplexer phase outputs to provide a single phase output selected from a range comprising at least 2pi in selectable variable phase increments of 2pi/96 radian. The combined oscillator with the phase selector within a phase locked loop controls phase by exact fractional increments of equally space phases of the operating frequency within the phase locked loop, therein controlling phase at all operating frequencies.