2868 results about "Phase-locked loop" patented technology

Controls for an optical scanner, such as a single fiber scanning endoscope (SFSE) that includes a resonating optical fiber and a single photodetector to produce large field of view, high-resolution images. A nonlinear control scheme with feedback linearization is employed in one type of control to accurately produce a desired scan. Open loop and closed loops controllers are applied to the nonlinear optical scanner of the SFSE. A closed loop control (no model) uses either phase locked loop and PID controllers, or a dual-phase lock-in amplifier and two PIDs for each axis controlled. Other forms of the control that employ a model use a frequency space tracking control, an error space tracking control, feedback linearizing controls, an adaptive control, and a sliding mode control.

A synchronous bi-directional active power conditioning system (11) suitable for wide variable frequency systems or active loads such as adjustable speed drives which require variable voltage variable frequency power management systems is disclosed. Common power electronics building blocks (100, 200) (both hardware and software modular blocks) are presented which can be used for AC-DC, DC-AC individually or cascaded together for AC-DC-AC power conversion suitable for variable voltage and/or wide variable frequency power management systems. A common control software building block (2, 5) includes a digital control strategy/algorithm and digital phase lock loop method and apparatus which are developed and implemented in a digital environment to provide gating patterns for the switching elements (3, 6) of the common power-pass modular power electronics building blocks (100, 200).

A phase locked loop includes at least one control circuit, where a voltage-controlled oscillator provides an output frequency which is arranged to strive to follow an input frequency. The phase locked loop also includes an outer, slow, negative feedback control circuit, having the input frequency as a setpoint, the output frequency as a process value and an outer output signal. The phase locked loop also includes an inner, fast, negative feedback control circuit, having the sum of a reference frequency from a stable oscillator and the outer output signal as a setpoint, the output frequency as the process value and an inner output signal for controlling the voltage controlled oscillator.

A millimeter wave pulsed radar system includes a radar synthesizer having a voltage controlled oscillator/phase locked loop (VCO/PLL) circuit, direct digital synthesizer (DDS) circuit and quadrature modulator circuit that are operative to generate an intermediate frequency local oscillator signal (IF/LO signal). A radar transceiver is operative with the radar synthesizer for receiving the IF/LO signal. A transmitter section has a frequency multiplier that multiplies the IF/LO signal up to a millimeter wave (MMW) radar signal and a receiver section and includes a direct conversion mixer that receives a MMW radar signal and the IF/LO signal to produce I/Q baseband signals that are later digitized and processed.

This invention relates to opto-electronic systems using semiconductor lasers driven by feedback control circuits that control the laser's optical phase and frequency. Feedback control provides a means for coherent phased laser array operation and reduced phase noise. Systems and methods to coherently combine a multiplicity of lasers driven to provide high power coherent outputs with tailored spectral and wavefront characteristics are disclosed. Systems of improving the phase noise characteristics of one or more semiconductor lasers are further disclosed.

The invention discloses a method for improving the estimation accuracy of the rotor position of a permanent magnet synchronous motor. The method comprises the following steps: on the basis of realizing estimation of the rotor position of the permanent magnet synchronous motor by utilizing a pulse-shake high frequency voltage injection method, processing the extracted position estimation error function, eliminating a second harmonic component introduced due to asymmetric motor parameters, so as to obtain a processed position estimation error function, then establishing a phase-locked loop, and adjusting the phase-locked loop to be 0, thus obtaining estimated rotor speed and estimated rotor position. The method disclosed by the invention can effectively inhibit position estimation second harmonic error caused by the asymmetric motor parameters, and the performance of a control system without a position sensor can be improved.

A power inverter system includes a DC to AC inverter configured to convert DC voltage from a DC power source to AC voltage. A DC link couples the DC power source and the inverter. An inverter pre-charger operates to pre-charge the inverter to achieve a desired DC link voltage prior to connecting the power inverter system to an AC power grid. A phased lock loop synchronizes the pre-charged inverter to the AC power grid prior to connecting the power inverter system to the AC power grid. The pre-charged inverter regulates the DC link voltage to about the minimum voltage level that allows control of AC grid currents via the inverter subsequent to connecting the power inverter system to the AC grid. The inverter operates in a maximum power point tracking control mode only subsequent to a first voltage transient caused by connecting the DC power source to energize the power inverter system.

A method and apparatus for anti-islanding of distributed power generation systems having an inverter comprising a phase locked loop (PLL), a phase shift generator for injecting a phase shift into the PLL during at least one sample period, and a phase error signature monitor for monitoring at least one phase error response of the PLL during the at least one sample period.

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

A power system having a phase locked loop (PLL) with a notch filter for synchronous reference frame sequence separation. The notch filter includes a generalized integrator tuned to the notch frequency. The output of the generalized integrator is summed with the filter input signal and the output of the summer is fed back to the integrator input. In one embodiment, the notch filter is programmable by a control signal generated in response to the filter output signal, thereby causing the filter to self-regulate to a frequency related to the PLL input signal. Illustrative power systems include active VAR generators and active rectifiers. One or more additional notch filters may be used to remove harmonic components from derived synchronous reference frame sequence components.

Aspects of the disclosure relate generally to a circuit for sustaining an radio frequency (RF) modulated optical signal. The circuit may comprise a self injection locking component having a fiber optic delay line over which a portion of the optical signal propagates. The circuit may also comprise a self phase locked loop component having at least two fiber optic cables having different lengths and over which another portion of the optical signal propagates and a phase detector coupled to the at least two fiber optic cables and configured to determine a phase difference between the signals propagating over one of the respective fiber optic cables. The circuit may further comprise a voltage controlled oscillator configured to generate a stable oscillating signal in response to signals generated by each of the self injection locking and self phase locked loop components, the stable oscillating signal being configured to sustain the optical signal.

Servo writing a disk of a disk drive is disclosed. A phase locked loop (PLL) is synchronized to first sectors previously written on a first track, and second sectors are written to a second track using the PLL, wherein a plurality of phase errors corresponding to the second sectors are saved. A correction value is computed corresponding to a selected one of the second sectors, wherein the correction value is computed in response to a plurality of the phase errors generated for a plurality of the second sectors leading the selected sector. The PLL is synchronized to the second sectors using the correction value, a third sector is written to a third track using the PLL, and a phase error is saved corresponding to the third sector.

A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog/RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.

Measurements made by a rotating sensor on a bottomhole assembly are used to determine the toolface angle of the BHA. The method includes using a phase locked loop (PLL) to determine a phase difference between the sensor output and a reference signal.

A low-cost sine-wave drive for a 3-phase permanent magnet synchronous AC machines (PMSM) in open-loop control is based on the measurements of two linear Hall sensors. The two Hall sensors are excited by a magnetic ring with the same pole number as the PMSM rotor magnet and sinusoidal flux distributions. The output signals of the Hall sensors are unified through a two-phase-type phase-lock-loop in order to reduce the impact of the sensor mounting non-uniformity during mass production. The peak torque and speed of motor is simply controlled by adjusting the amplitude of pulse-width-modulation carrier. Smooth torque control is achieved due to sinusoidal 3-phase currents. Such a simple sine-wave drive can be achieved with or without the assistance of a micro-controller unit (MCU). No current sensor is required for the motor phase current detection. This motor can be used in industrial applications where there is no strict requirement on torque response and constant speed control of PMSM machines.

The present invention provides an improved method and apparatus for independently controlling phase and frequency using an oscillator having a plurality of stages in combination with a phase selector within a digitally controlled phase-locked loop, preferably, a read phase locked loop. The present invention provides a digitally controlled variable phase of the read timing loop in read channel integrated circuits associated with data storage devices. The phase selector has a digitally controlled fine interpolator with 12 states for further fine interpolation between at least two multiplexer phase outputs to provide a single phase output selected from a range comprising at least 2pi in selectable variable phase increments of 2pi/96 radian. The combined oscillator with the phase selector within a phase locked loop controls phase by exact fractional increments of equally space phases of the operating frequency within the phase locked loop, therein controlling phase at all operating frequencies.

An Orthogonal Frequency Division Multiplexing (OFDM) receiver that employs N second-order phase-lock loops sharing a common integrator (where N is the number of pilots in the system). The N second order phase-lock loops track out independent pilot phase rotations to facilitate the constructive averaging of the pilots' phase information. At the same time, by sharing a common integrator, the OFDM receiver takes advantage of noise averaging over multiple pilots to obtain a cleaner frequency offset estimation. The OFDM receiver may also compensate for FFT window drift by calculating a phase difference between a selected pair of pilots and tracking the rate of change of the calculated phase difference over time. The calculated phase difference is used to control the position of an upstream FFT window after a predetermined phase difference threshold is exceeded. The tracked rate of change is used to continuously adjust the phase of downstream equalizer taps.

An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

A method for maintaining the states of a receiver during the silent line state of a network device operating in a low power link suspend mode is presented. Accordingly, a method of freezing the states of the equalizer and keeping the receiver clock locked to a frequency that is approximately equal to that of the input data while providing for rapid adjustment to the phase and thus recovery of the input data is presented. During Silent Line State (SLS), the receiver states are frozen using methods that avoid parasitic decay. Also, the receive clock phase lock loop is locked onto the local transmit clock since the local transmit clock has a frequency approximating the incoming data frequency. During the SLS, the transmitter of the remote network device may have been turned off to conserve power therefore the receiver has no way of immediately knowing the phase of an incoming data. Thus, in order to prevent loss of data, the receiver loops of the receiving network device are trained to the frequency of the transmitting remote network device using periodic Link Suspend packets. Thus, in most cases, only the phase of the incoming signal need be acquired when data arrives. The phase may be quickly acquired using loop bandwidth shift methods whereby the receive clock phase lock loop bandwidth is increased to a value that aids rapid acquisition of the input clock and then, after acquisition, the bandwidth is shifted to a low value to enhance noise rejection during tracking.

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

A system and method are disclosed for implementing a power source including a power amplifier that generates a radio-frequency power signal with an adjustable operating frequency. The power amplifier also generates a reference phase signal that is derived from the radio-frequency power signal. An impedance match provides the radio-frequency power signal to a plasma coil that has a variable resonance condition. A phase probe is positioned adjacent to the plasma coil to generate a coil phase signal corresponding to the adjustable operating frequency. A phase-locked loop then generates an RF drive signal that is based upon a phase relationship between the reference phase signal and the coil phase signal. The phase-locked loop provides the RF drive signal to the power amplifier to control the adjustable operating frequency, so that the adjustable operating frequency then tracks the variable resonance condition.

The LC VCO includes an LC oscillator module with first and second tank nodes and a control module with positive and negative input voltage terminals. The control module includes four voltage dependent capacitive elements which are configured to be biased for operation as voltage dependent variable capacitances. The voltage dependent capacitive elements are interconnected such that the effect of a common mode input voltage is to increase the capacitance of two of the voltage dependent capacitive elements, while simultaneously decreasing the capacitance of two of the other voltage dependent capacitive elements by a substantially similar amount, such that a differential voltage applied across the positive and negative input voltage terminals is operable to change the capacitance of the voltage dependent capacitive elements, and thereby the frequency of the LC oscillator module, while effects on the output frequency of the oscillator caused by a common mode voltage tend to cancel. Accordingly, a fully differential signal path in phase locked loops employing LC oscillators, with improved noise rejection, substantial suppression of common mode noise, and a minimal increase in complexity over a single-ended control design can be achieved. Additional supply voltages need not be employed.

An automatic tuning system for a magnetic field generating tuned circuit includes a processor configured to maintain the resonant frequency of a tuned circuit equal to a reference frequency. The tuned circuit is driven by a power amplifier whose output provides an amplified signal at the reference frequency. The tuned circuit includes a magnetic field generating inductor and a bank of individually switchable capacitors controlled by the processor capable of adding and removing the respective capacitances to and from the tuned circuit. The inductor includes a Faraday shield to shield the tuned circuit from the influence of electric fields. A power sense circuit monitors the power delivered by the power amplifier to the tuned circuit and the processor sequentially switches the capacitors in a binary progression format to achieve maximum power delivery indicative of conforming the resonant frequency of the tuned circuit to the reference frequency. In an alternate embodiment of the invention, the inductor includes a plurality of taps that provide individually selectable inductance values available for use in the process of conforming the resonant frequency of the tuned circuit to the reference frequency. In further alternate embodiments, the variable capacitor is in the form of a motor driven variable capacitor and the tuning sequence relies on a phase locked loop using the phase of a reference frequency signal and the phase of the inductor current as control parameters.

Digital transmitters having improved characteristics are described. In one design of a digital transmitter, a first circuit block receives inphase and quadrature signals, performs conversion from Cartesian to polar coordinates, and generates magnitude and phase signals. A second circuit block (which may include a delta-sigma modulator or a digital filter) generates an envelope signal based on the magnitude signal. A third circuit block generates a phase modulated signal based on the phase signal. The third circuit block may include a phase modulating phase locked loop (PLL), a voltage controlled oscillator (VCO), a saturating buffer, and so on. A fourth circuit block (which may include one or more exclusive-OR gates or an amplifier with multiple gain states) generates a digitally modulated signal based on the envelope signal and the phase modulated signal. A fifth circuit block (which may include a class D amplifier and/or a power amplifier) amplifies the digitally modulated signal and generates an RF output signal.

A phase-amplitude modulator for mobile communications employs a phase lock loop as an input to a nonlinear power amplifier providing phase information with amplitude information used to modulate the power amplifier output to synthesize phase-amplitude for the RF transmission signal.

A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock and a second input for a feedback signal, and outputting a difference signal representing a phase and/or frequency difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM. The system clock also may include a phase-locked loop (PLL) including a phase/frequency detector that has a first input coupled to the output of the DCO and a second input that is phase-locked to the first input, and a second frequency divider coupled from the second input of the PLL to the second input of the DPFD.

An RFID transponder comprises an antenna for receiving data in a downlink mode and transmitting data in an uplink mode, with a modulation stage for modulating uplink data and a demodulation stage for demodulating downlink data. A class C amplifier is provided, which has a resonant circuit, a plucking device coupled to the resonant circuit, and a controllable pulse width generator coupled to the plucking device. The controllable pulse width generator is adapted to periodically switch the plucking device on and off so as to maintain an oscillation of the resonant circuit. The transponder further comprises a phase locked loop configured to be locked to an oscillating signal received through the antenna and to be switched into a free running mode without being locked to the oscillating signal received through the antenna, thereby being adapted to output an independent internal clock signal for the RFID transponder.

Techniques for direct modulation of a switching-mode power amplifier with adaptive digital predistortion are disclosed. A baseband digital modulated signal is decomposed into an amplitude signal and a phase signal in polar coordinates. The amplitude signal is used to modulate supply voltages of the power amplifier. The phase signal is used to modulate a voltage-controlled oscillator (VCO) of a phase-locked loop (PLL), which generates a phase-modulated radio-frequency (RF) carrier coupled to the input of the power amplifier. The digital predistortion is implemented by using a feedback demodulator, which regenerates the baseband amplitude and phase information from the output of the power amplifier. The VCO drift and other non-linear effects of the power amplifier are compensated. High power efficiency and high linearity for different modulation standards are achieved.

An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL).

A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.