305results about "Generator stabilization" patented technology

The invention provides a crystal oscillator and an atomic clock, and relates to the technical field of oscillators, the crystal oscillator comprises a packaging cavity, a crystal, a temperature sensor and a cantilever beam assembly, the crystal, the temperature sensor and the cantilever beam assembly are arranged in a containing cavity of the packaging cavity, and the packaging cavity is of a vacuum packaging structure. The crystal and the temperature sensor are arranged on the cantilever beam assembly, the crystal and the temperature sensor are electrically connected with different connection points of the packaging cavity through the cantilever beam assembly, and the temperature sensor is arranged around the crystal; the cantilever beam assembly comprises a heating module, and when the temperature sensor monitors that the temperature of the area where the crystal is located is smaller than a preset temperature threshold value, the heating module heats the crystal. The energy loss of air damping to the high-frequency vibration of the crystal is eliminated, the Q value is improved, and the phase noise suppression capability is enhanced; accurate control over the temperature of the area where the crystal is located is achieved, the thermal response speed and the temperature control precision are improved, and the problem that an existing crystal oscillator is poor in stability is solved.

To provide a temperature-compensated crystal oscillator capable of coping with miniaturization and limitation of thermal capacity, a method of manufacturing the same, and an electronic apparatus equipped with the temperature compensated crystal oscillator.SOLUTION: A temperature-compensated crystal oscillator 30 includes: a crystal resonator 31; a temperature-compensated oscillation chip 32 with a built-in temperature sensor; an insulation layer 33; and a first electrode structure 34. The crystal resonator includes: a vibration element 311; and an airtight packaging structure 312 packaged on an outer periphery of the vibration element. The temperature-compensated oscillation chip 32 is disposed on one side of the hermetic sealed structure. The insulation layer covers at least one side of the temperature compensation oscillation chip and the airtight packaging structure, and includes a first via hole 331 formed with a conductive material and a heat insulation cavity 36 including a sealed cavity or a semi-sealed cavity. The insulation cavity has gas or is in a vacuum state. The first electrode structure is disposed on the insulating layer and electrically connected to the temperature-compensated oscillation chip through the conductive material in the first via hole.SELECTED DRAWING: Figure 3

An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

Embodiments herein relate to an apparatus and method for calibrating a notch filter which filters a power supply signal for a voltage-controlled oscillator (VCO). In one aspect, a control circuit performs a number of calibration cycles for the filter to determine a value of a calibration code for the filter which minimizes a change in a frequency of the output signal of the VCO due to a change in the voltage of the power supply signal. After each calibration cycle, the calibration code is adjusted based on whether the frequency of the output signal increase or decreases. The calibration cycles can therefore converge on an optimal calibration code which minimizes the change in frequency due to the change in voltage. This minimizes a sensitivity of the VCO to noise in the power supply signal.

A clock generation circuit has a voltage-controlled oscillator that includes a first transistor pair coupled in series between a power rail and ground, a replica transistor pair coupled in series between a reference node and ground, a current source having an output coupled to the reference node. The current source is coupled to a control signal that determines amplitude of current flowing through the replica transistor pair. A voltage regulator has an input coupled to the reference node and an output coupled to the power rail. The voltage regulator is configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. Each transistor in the replica transistor pair is collocated on an integrated circuit with and has a same type as a corresponding transistor in the first transistor pair.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The invention discloses a GPS oscillator taming system and method based on PID parameter adaptive adjustment, and the system comprises a forgetting factor dynamic updating module which is used for dynamically updating a forgetting factor with the variance of the frequency error of VC-TCXO as a negative index; the system identification module is used for estimating ARX model parameters of the VC-TCXO by adopting a recursive least square algorithm with the updated forgetting factor; the model parameter mapping module is used for mapping the estimated ARX model parameters to obtain PID control parameters; the incremental PID controller is used for calculating a frequency control word increment based on the frequency error; the digital-to-analog converter is used for calculating according to the frequency control word increment to obtain a frequency control word and converting the frequency control word into analog voltage; and the VC-TCXO is used for obtaining the frequency of the GPS reference signal based on the analog voltage corresponding to the frequency control word so as to complete frequency taming. The method is high in calculation efficiency and robustness, and can adapt to the dynamic change and external disturbance of the controlled object in real time.

The embodiment of the invention discloses a clock source and electronic equipment, and belongs to the technical field of integrated circuits. The clock source comprises a plurality of inverter chain loops, the plurality of inverter chain loops comprise a main loop and at least two auxiliary loops, and the main loop is respectively coupled with the at least two auxiliary loops to construct at least two coupling relations. According to the embodiment of the invention, the problem of oscillation mode ambiguity of a clock source design scheme capable of improving the oscillation frequency in the related technology is at least solved.

The invention discloses a constant-temperature crystal oscillator and rubidium clock combined taming device and method, and relates to the technical field of time frequency, and the device comprises a single-chip microcomputer, an FPGA module, a TDC module, a rubidium atomic clock and a constant-temperature crystal oscillator. The FPGA module is connected with the single-chip microcomputer, the TDC module, the rubidium atomic clock and the constant-temperature crystal oscillator, the FPGA module is used for receiving a reference 1PPS signal input from the outside, the single-chip microcomputer is connected with the constant-temperature crystal oscillator through the DAC module, the TDC module is connected with the single-chip microcomputer through an SPI bus, the TDC module is used for measuring the phase difference, and the single-chip microcomputer is used for adjusting the voltage control of the constant-temperature crystal oscillator or the frequency of the rubidium atomic clock; and the FPGA module communicates with the rubidium atomic clock through a UART serial port. The output frequency has the characteristics of a constant-temperature crystal oscillator and a rubidium atomic clock at the same time, and low noise and high stability are achieved; a taming state can be quickly entered to output an accurate clock without waiting for preheating of a rubidium clock during startup; a serial taming mode is avoided, parallel taming is adopted, and when one clock source is abnormal, clock hot backup can be achieved.

The thermosensitive crystal resonator comprises a base, a quartz wafer and a thermistor, the base comprises a base bottom plate, a base middle plate and a base wall which are sequentially arranged from bottom to top, an inner cavity is defined by the upper end face of the base middle plate and the inner wall of the base wall, an upper end opening of the inner cavity is sealed through an upper cover, and a lower end opening of the inner cavity is sealed through a lower cover. A center through hole is longitudinally formed in the middle of the upper end face of the base middle plate, a thermistor is installed in the center through hole, side edge through holes are formed in the positions, located on the two sides of the center through hole, of the upper end of the base middle plate respectively, embedded blocks are installed in the side edge through holes, a plurality of honeycomb holes are formed in the upper portions of the embedded blocks, and the honeycomb holes are filled with conductive buffer rubber. And the upper ends of the two embedded blocks are connected with a quartz wafer through conductive silver adhesive. By optimizing multiple designs of the base structure, the honeycomb buffer structure, the close-range thermosensitive compensation arrangement structure and the double-sealing structure, temperature compensation precision, stress buffer high efficiency and sealing performance long-term performance are achieved.

Disclosed is a clock system for generating an error-reduced clock output. In one implementation, the clock system includes a plurality of physical clusters of MEMS oscillators that provide a set of associated clock inputs to a processor. The processor performs RMS error correction and / or Kalman filtering and / or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. In another implementation, the processor configures the MEMS oscillators into a dynamic plurality of logical clusters instead of relying on a plurality of physical clusters. The processor performs RMS error correction and / or Kalman filtering and / or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. Also disclosed are techniques for compensating for errors related to temperature drift, tilt, and age drift of the MEMS oscillators.

A clock integrated circuit (100) is provided. The clock integrated circuit includes: a first clock generator (110) which includes a crystal oscillator (XTAL) configured to generate a first clock signal (fxo); and a second clock generator (120) which includes a resistance-capacitance (RC) oscillator (121) and a first frequency divider (122), and is configured to: generate a second clock signal (fRTC)using the first frequency divider (122) based on a clock signal (fRCO) output from the RC oscillator (121); perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider (122) to a first frequency division ratio based on the first clock signal (fxo) ; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

A delay-line circuit includes multiple variable-delay circuits and may generate an output signal that is a delayed version of an input signal. A calibration circuit includes an oscillator circuit that may generate an oscillator signal, and may include a replica of at least one of the multiple variable-delay circuits. The calibration circuit may perform an initial calibration of the delay-line circuit and, in response to a completion of the initial calibration, perform a background calibration of the delay-line circuit using the oscillator signal.

A semiconductor device includes: a semiconductor element configured to output a compensation voltage; a constant current circuit configured to output a constant current so as to compensate for temperature dependence according to the comparison of the compensation voltage and a reference voltage; an oscillation circuit configured to output an oscillation signal according to the constant current; a check voltage generation circuit configured to output a check voltage; and a signal generation circuit configured to output a temperature information signal corresponding to the compensation voltage and the check voltage.

The invention relates to the technical field of ultrasonic transducers, in particular to an ultrasonic transducer signal anti-interference transmission method and device, and the device comprises a signal preprocessing unit, an anti-interference unit, an isolation driving unit and a receiving demodulation and decoding unit. The signal preprocessing unit receives the original electric signal and performs differential amplification to generate a differential signal; the anti-interference unit collects the working environment temperature in real time through the temperature monitoring module, the coding strategy selection module and the modulation parameter control module dynamically select and optimize coding rules and adjust modulation parameters according to the working environment temperature, and the signal processing module converts differential signals into digital signals and completes coding modulation. The isolation driving unit performs signal isolation and power amplification; the receiving demodulation and decoding unit demodulates and decodes according to a corresponding rule and restores the ultrasonic signal; according to the invention, the coding rule, the modulation parameter and the heat dissipation strategy are dynamically adapted through temperature monitoring, the high-temperature performance drift of the anti-interference unit is inhibited, and reliable transmission of signals of the ultrasonic transducer is ensured.

Oscillator. The present invention provides an oscillator in which external heat is less likely to be transmitted to a vibrating element, and which has stable frequency characteristics. The oscillator has: an outer package; an inner package housed in the outer package and fixed to the outer package via a heat-insulating member; a vibrating element housed in the inner package; a temperature sensor; a first circuit element including an oscillation circuit that causes the vibrating element to oscillate and generates an oscillation signal that is temperature-compensated based on the temperature sensor, the first circuit element being housed in the inner package; and a second circuit element fixed to the outer package and including a frequency control circuit that controls the frequency of the oscillation signal.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

Aspects described herein include devices and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having an analog 1-bit sampler configured to sample a phase locked loop (PLL) output signal using a PLL reference clock to generate 1-bit samples and a digital phase computation and control circuit configured to receive the 1-bit samples from the analog 1-bit sampler and apply phase corrections to the PLL based on a phase error derived from the 1-bit samples.

The present invention relates to a radio transmitter (200) for operating a radio transmission system (100), preferably an SRD radio transmission system, between at least one radio transmitter (200), preferably between a plurality of radio transmitters (200), and a radio receiver (300) operating as a base station, wherein the respective radio transmitter (200) sends a telegram in the form of a data packet or a plurality of successively sent partial data packets to the radio receiver (300) at specific transmission times, each as a burst or bursts, wherein the respective radio transmitter (200) has a quartz crystal (201) which generates an oscillation for a timer, on the basis of which the timer determines the start and / or end times of the transmission of the respective burst, wherein the quartz crystal (201) is characterized by a quartz error profile (F1) which determines the original temperature dependence of the quartz error of the quartz crystal (201).To solve the problem of providing a radio transmitter that allows for the time-accurate transmission of telegrams even when its hardware does not enable alignment with the transmission frequency or carrier frequency of the radio signal, compensation means for the quartz error of the quartz crystal (201) are provided, which change, in particular shift, the quartz error curve (F1).

A circuit for reducing a temperature-induced frequency drift in a voltage to current (V2I) converter based voltage-controlled oscillator (VCO) for at least one wide band phase-locked loop (PLL), the circuit includes a V2I resistor node of the V2I converter, the V2I resistor node being at one end of a resistor, the VCO, and a current controlled oscillator (CCO), and the circuit is configured to provide a fixed offset current to the V2I resistor node to cause at least one V2I output current to have a value conversely proportional to absolute temperature (CTAT), the at least one V2I output current being output by the V2I converter, and mirror the at least one V2I output current to the CCO to reduce the temperature-induced frequency drift at a lower frequency band of the VCO.

The present invention discloses a ring oscillator, chip, and electronic device that utilizes reverse clock compensation for reinforcement. The ring oscillator includes a compensation reinforcement circuit for reinforcing the output pin OUT1 of a delay node using reverse clock compensation. The compensation reinforcement circuit includes two PMOS transistors M1 and M2, and two NMOS transistors M3 and M4. The source of the PMOS transistor M1 is connected to voltage VDD, and its drain is connected to ground via a series connection of PMOS transistors M2, M3, and M4. The gates of the PMOS transistors M1 and M4 are connected to the output pin OUT1, and the gates of the PMOS transistors M2 and NMOS transistors M3 are both connected to the input pin IN3, which has a complementary signal to the output pin OUT1. The present invention aims to provide radiation hardening for the ring oscillator and improve its resistance to single-event interference.

The application discloses an inductor coil, a voltage-controlled oscillator and a method for improving gate voltage swing, and relates to the technical field of inductor coils. The inductor coil comprises a P-side inductor coil branch and an N-side inductor coil branch, and the P-side inductor coil branch is connected with the N-side inductor coil branch. The P-side inductor coil branch comprises a first P-side inductor and a second P-side inductor connected in series, and the connection point of the first P-side inductor and the second P-side inductor is a first tapping point, which is used for increasing P-side passive gain. The N-side inductor coil branch comprises a first N-side inductor and a second N-side inductor connected in series, and the connection point of the first N-side inductor and the second N-side inductor is a second tapping point, which is used for increasing N-side passive gain. The first P-side inductor is connected with the first N-side inductor. When the inductor coil is applied to a resonant cavity of a voltage-controlled oscillator, passive gain can be used to improve gate voltage swing, reduce saturation time and realize current noise suppression.

The application provides an electronic watch running time precision regulation system, and relates to the technical field of data processing.The system is used for collecting temperature values, voltage values and cumulative running time, counting the number of pulses output by a crystal oscillator in a unit time, obtaining state data and basic frequency data, calculating frequency offset values in different periods, performing window sliding, calculating drift trend values in different windows, calculating the difference between different states between adjacent periods, obtaining state change values, combining and analyzing the state change values with a frequency drift trend sequence, obtaining a state response coefficient set, identifying effective disturbance components in state change vectors of different periods, calculating pulse compensation values in different periods, obtaining pulse compensation data, correcting timing pulses, obtaining a pulse output sequence, and updating the time of the electronic watch according to the pulse output sequence.The application can regulate the pulse signal of the electronic watch and ensure the precision of running time.

This invention relates to a ground-based analog frequency conversion system for satellite payloads and its implementation method. The system includes: a filtering and coupling module for receiving high-frequency signals in the Q and V bands and splitting them into a coupling signal and a main signal, which are then transmitted to a detector module and a limiter, respectively. The detector module detects the power of the coupling signal at different temperatures and feeds it back to the control module. The limiter limits the maximum strength of the main signal to protect the low-noise amplifier (LNO). The LNO amplifies the main signal and reduces noise. A phase-locked loop (PLL) and frequency conversion module down-converts the high-frequency signal to an intermediate-frequency (IF) signal. An IF filtering and amplification module suppresses spurious interference and amplifies the IF signal. A temperature compensation module and a gain control module adjust the attenuation value to achieve temperature compensation and ensure that the IF output signal strength meets preset requirements. All modules are integrated using micro-assembly technology. This system can reduce the power consumption and cost of satellite launch and communication.

The present invention provides a thermostatic piezoelectric oscillator capable of high-precision control of both the temperature of the heating element and the piezoelectric vibration of the piezoelectric vibrator, while reducing costs. The thermostatic piezoelectric oscillator (1) has a core (5) having a crystal resonator (50), an oscillator IC (51), and a heater IC (52). In the thermostatic piezoelectric oscillator (1), the core (5) is supported in a package (2) by an intermediate member (4) and sealed inside the package (2) in a sealed state.

Disclosed is a method comprising obtaining a plurality of previous clock skews, a reported temperature and a reported time, based on the plurality of previous clock skews, the reported temperature and the reported time, obtaining a prediction of the current clock skew, determining a current clock offset based on the predicted current clock skew, determining a clock adjustment based on the current clock offset and the reported time, and determining a corrected time based on the clock adjustment.

One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.

An example resonating structure comprises a substrate, a resonator body, and an anchoring body for anchoring the resonator body to the substrate. The resonator body is doped with a dopant having a concentration chosen so as to minimize a second order temperature coefficient of frequency for the resonator body. The resonator body is operable in an in-plane mode of vibration and an out-of-plane mode of vibration.

This application discloses a crystal oscillator frequency self-calibration method, an electronic device, and a computer-readable storage medium. The method includes: acquiring a time deviation sequence; acquiring a voltage sequence; acquiring the processor's behavioral characteristics at the current wake-up time; determining the equivalent temperature of the crystal oscillator at the current wake-up time based on the time deviation sequence, voltage sequence, and processor behavioral characteristics; testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matched test strategy based on the equivalent temperature of the crystal oscillator at the current wake-up time; and determining the final target capacitor connected to the crystal oscillator based on the target test frequency of the crystal oscillator with multiple different test capacitors connected and the multiple different test capacitors. This method can achieve self-calibration of the crystal oscillator frequency.

A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.