209results about "Generator stabilization" patented technology

An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The invention discloses a GPS oscillator taming system and method based on PID parameter adaptive adjustment, and the system comprises a forgetting factor dynamic updating module which is used for dynamically updating a forgetting factor with the variance of the frequency error of VC-TCXO as a negative index; the system identification module is used for estimating ARX model parameters of the VC-TCXO by adopting a recursive least square algorithm with the updated forgetting factor; the model parameter mapping module is used for mapping the estimated ARX model parameters to obtain PID control parameters; the incremental PID controller is used for calculating a frequency control word increment based on the frequency error; the digital-to-analog converter is used for calculating according to the frequency control word increment to obtain a frequency control word and converting the frequency control word into analog voltage; and the VC-TCXO is used for obtaining the frequency of the GPS reference signal based on the analog voltage corresponding to the frequency control word so as to complete frequency taming. The method is high in calculation efficiency and robustness, and can adapt to the dynamic change and external disturbance of the controlled object in real time.

The embodiment of the invention discloses a clock source and electronic equipment, and belongs to the technical field of integrated circuits. The clock source comprises a plurality of inverter chain loops, the plurality of inverter chain loops comprise a main loop and at least two auxiliary loops, and the main loop is respectively coupled with the at least two auxiliary loops to construct at least two coupling relations. According to the embodiment of the invention, the problem of oscillation mode ambiguity of a clock source design scheme capable of improving the oscillation frequency in the related technology is at least solved.

The invention discloses a constant-temperature crystal oscillator and rubidium clock combined taming device and method, and relates to the technical field of time frequency, and the device comprises a single-chip microcomputer, an FPGA module, a TDC module, a rubidium atomic clock and a constant-temperature crystal oscillator. The FPGA module is connected with the single-chip microcomputer, the TDC module, the rubidium atomic clock and the constant-temperature crystal oscillator, the FPGA module is used for receiving a reference 1PPS signal input from the outside, the single-chip microcomputer is connected with the constant-temperature crystal oscillator through the DAC module, the TDC module is connected with the single-chip microcomputer through an SPI bus, the TDC module is used for measuring the phase difference, and the single-chip microcomputer is used for adjusting the voltage control of the constant-temperature crystal oscillator or the frequency of the rubidium atomic clock; and the FPGA module communicates with the rubidium atomic clock through a UART serial port. The output frequency has the characteristics of a constant-temperature crystal oscillator and a rubidium atomic clock at the same time, and low noise and high stability are achieved; a taming state can be quickly entered to output an accurate clock without waiting for preheating of a rubidium clock during startup; a serial taming mode is avoided, parallel taming is adopted, and when one clock source is abnormal, clock hot backup can be achieved.

The thermosensitive crystal resonator comprises a base, a quartz wafer and a thermistor, the base comprises a base bottom plate, a base middle plate and a base wall which are sequentially arranged from bottom to top, an inner cavity is defined by the upper end face of the base middle plate and the inner wall of the base wall, an upper end opening of the inner cavity is sealed through an upper cover, and a lower end opening of the inner cavity is sealed through a lower cover. A center through hole is longitudinally formed in the middle of the upper end face of the base middle plate, a thermistor is installed in the center through hole, side edge through holes are formed in the positions, located on the two sides of the center through hole, of the upper end of the base middle plate respectively, embedded blocks are installed in the side edge through holes, a plurality of honeycomb holes are formed in the upper portions of the embedded blocks, and the honeycomb holes are filled with conductive buffer rubber. And the upper ends of the two embedded blocks are connected with a quartz wafer through conductive silver adhesive. By optimizing multiple designs of the base structure, the honeycomb buffer structure, the close-range thermosensitive compensation arrangement structure and the double-sealing structure, temperature compensation precision, stress buffer high efficiency and sealing performance long-term performance are achieved.

A clock integrated circuit (100) is provided. The clock integrated circuit includes: a first clock generator (110) which includes a crystal oscillator (XTAL) configured to generate a first clock signal (fxo); and a second clock generator (120) which includes a resistance-capacitance (RC) oscillator (121) and a first frequency divider (122), and is configured to: generate a second clock signal (fRTC)using the first frequency divider (122) based on a clock signal (fRCO) output from the RC oscillator (121); perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider (122) to a first frequency division ratio based on the first clock signal (fxo) ; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

A delay-line circuit includes multiple variable-delay circuits and may generate an output signal that is a delayed version of an input signal. A calibration circuit includes an oscillator circuit that may generate an oscillator signal, and may include a replica of at least one of the multiple variable-delay circuits. The calibration circuit may perform an initial calibration of the delay-line circuit and, in response to a completion of the initial calibration, perform a background calibration of the delay-line circuit using the oscillator signal.

A semiconductor device includes: a semiconductor element configured to output a compensation voltage; a constant current circuit configured to output a constant current so as to compensate for temperature dependence according to the comparison of the compensation voltage and a reference voltage; an oscillation circuit configured to output an oscillation signal according to the constant current; a check voltage generation circuit configured to output a check voltage; and a signal generation circuit configured to output a temperature information signal corresponding to the compensation voltage and the check voltage.

The invention relates to the technical field of ultrasonic transducers, in particular to an ultrasonic transducer signal anti-interference transmission method and device, and the device comprises a signal preprocessing unit, an anti-interference unit, an isolation driving unit and a receiving demodulation and decoding unit. The signal preprocessing unit receives the original electric signal and performs differential amplification to generate a differential signal; the anti-interference unit collects the working environment temperature in real time through the temperature monitoring module, the coding strategy selection module and the modulation parameter control module dynamically select and optimize coding rules and adjust modulation parameters according to the working environment temperature, and the signal processing module converts differential signals into digital signals and completes coding modulation. The isolation driving unit performs signal isolation and power amplification; the receiving demodulation and decoding unit demodulates and decodes according to a corresponding rule and restores the ultrasonic signal; according to the invention, the coding rule, the modulation parameter and the heat dissipation strategy are dynamically adapted through temperature monitoring, the high-temperature performance drift of the anti-interference unit is inhibited, and reliable transmission of signals of the ultrasonic transducer is ensured.

Oscillator. The present invention provides an oscillator in which external heat is less likely to be transmitted to a vibrating element, and which has stable frequency characteristics. The oscillator has: an outer package; an inner package housed in the outer package and fixed to the outer package via a heat-insulating member; a vibrating element housed in the inner package; a temperature sensor; a first circuit element including an oscillation circuit that causes the vibrating element to oscillate and generates an oscillation signal that is temperature-compensated based on the temperature sensor, the first circuit element being housed in the inner package; and a second circuit element fixed to the outer package and including a frequency control circuit that controls the frequency of the oscillation signal.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

The present invention relates to a radio transmitter (200) for operating a radio transmission system (100), preferably an SRD radio transmission system, between at least one radio transmitter (200), preferably between a plurality of radio transmitters (200), and a radio receiver (300) operating as a base station, wherein the respective radio transmitter (200) sends a telegram in the form of a data packet or a plurality of successively sent partial data packets to the radio receiver (300) at specific transmission times, each as a burst or bursts, wherein the respective radio transmitter (200) has a quartz crystal (201) which generates an oscillation for a timer, on the basis of which the timer determines the start and / or end times of the transmission of the respective burst, wherein the quartz crystal (201) is characterized by a quartz error profile (F1) which determines the original temperature dependence of the quartz error of the quartz crystal (201).To solve the problem of providing a radio transmitter that allows for the time-accurate transmission of telegrams even when its hardware does not enable alignment with the transmission frequency or carrier frequency of the radio signal, compensation means for the quartz error of the quartz crystal (201) are provided, which change, in particular shift, the quartz error curve (F1).

A circuit for reducing a temperature-induced frequency drift in a voltage to current (V2I) converter based voltage-controlled oscillator (VCO) for at least one wide band phase-locked loop (PLL), the circuit includes a V2I resistor node of the V2I converter, the V2I resistor node being at one end of a resistor, the VCO, and a current controlled oscillator (CCO), and the circuit is configured to provide a fixed offset current to the V2I resistor node to cause at least one V2I output current to have a value conversely proportional to absolute temperature (CTAT), the at least one V2I output current being output by the V2I converter, and mirror the at least one V2I output current to the CCO to reduce the temperature-induced frequency drift at a lower frequency band of the VCO.

The present invention discloses a ring oscillator, chip, and electronic device that utilizes reverse clock compensation for reinforcement. The ring oscillator includes a compensation reinforcement circuit for reinforcing the output pin OUT1 of a delay node using reverse clock compensation. The compensation reinforcement circuit includes two PMOS transistors M1 and M2, and two NMOS transistors M3 and M4. The source of the PMOS transistor M1 is connected to voltage VDD, and its drain is connected to ground via a series connection of PMOS transistors M2, M3, and M4. The gates of the PMOS transistors M1 and M4 are connected to the output pin OUT1, and the gates of the PMOS transistors M2 and NMOS transistors M3 are both connected to the input pin IN3, which has a complementary signal to the output pin OUT1. The present invention aims to provide radiation hardening for the ring oscillator and improve its resistance to single-event interference.

The application discloses an inductor coil, a voltage-controlled oscillator and a method for improving gate voltage swing, and relates to the technical field of inductor coils. The inductor coil comprises a P-side inductor coil branch and an N-side inductor coil branch, and the P-side inductor coil branch is connected with the N-side inductor coil branch. The P-side inductor coil branch comprises a first P-side inductor and a second P-side inductor connected in series, and the connection point of the first P-side inductor and the second P-side inductor is a first tapping point, which is used for increasing P-side passive gain. The N-side inductor coil branch comprises a first N-side inductor and a second N-side inductor connected in series, and the connection point of the first N-side inductor and the second N-side inductor is a second tapping point, which is used for increasing N-side passive gain. The first P-side inductor is connected with the first N-side inductor. When the inductor coil is applied to a resonant cavity of a voltage-controlled oscillator, passive gain can be used to improve gate voltage swing, reduce saturation time and realize current noise suppression.

The application provides an electronic watch running time precision regulation system, and relates to the technical field of data processing.The system is used for collecting temperature values, voltage values and cumulative running time, counting the number of pulses output by a crystal oscillator in a unit time, obtaining state data and basic frequency data, calculating frequency offset values in different periods, performing window sliding, calculating drift trend values in different windows, calculating the difference between different states between adjacent periods, obtaining state change values, combining and analyzing the state change values with a frequency drift trend sequence, obtaining a state response coefficient set, identifying effective disturbance components in state change vectors of different periods, calculating pulse compensation values in different periods, obtaining pulse compensation data, correcting timing pulses, obtaining a pulse output sequence, and updating the time of the electronic watch according to the pulse output sequence.The application can regulate the pulse signal of the electronic watch and ensure the precision of running time.

This invention relates to a ground-based analog frequency conversion system for satellite payloads and its implementation method. The system includes: a filtering and coupling module for receiving high-frequency signals in the Q and V bands and splitting them into a coupling signal and a main signal, which are then transmitted to a detector module and a limiter, respectively. The detector module detects the power of the coupling signal at different temperatures and feeds it back to the control module. The limiter limits the maximum strength of the main signal to protect the low-noise amplifier (LNO). The LNO amplifies the main signal and reduces noise. A phase-locked loop (PLL) and frequency conversion module down-converts the high-frequency signal to an intermediate-frequency (IF) signal. An IF filtering and amplification module suppresses spurious interference and amplifies the IF signal. A temperature compensation module and a gain control module adjust the attenuation value to achieve temperature compensation and ensure that the IF output signal strength meets preset requirements. All modules are integrated using micro-assembly technology. This system can reduce the power consumption and cost of satellite launch and communication.

The present invention provides a thermostatic piezoelectric oscillator capable of high-precision control of both the temperature of the heating element and the piezoelectric vibration of the piezoelectric vibrator, while reducing costs. The thermostatic piezoelectric oscillator (1) has a core (5) having a crystal resonator (50), an oscillator IC (51), and a heater IC (52). In the thermostatic piezoelectric oscillator (1), the core (5) is supported in a package (2) by an intermediate member (4) and sealed inside the package (2) in a sealed state.

Disclosed is a method comprising obtaining a plurality of previous clock skews, a reported temperature and a reported time, based on the plurality of previous clock skews, the reported temperature and the reported time, obtaining a prediction of the current clock skew, determining a current clock offset based on the predicted current clock skew, determining a clock adjustment based on the current clock offset and the reported time, and determining a corrected time based on the clock adjustment.

One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.

This application discloses a crystal oscillator frequency self-calibration method, an electronic device, and a computer-readable storage medium. The method includes: acquiring a time deviation sequence; acquiring a voltage sequence; acquiring the processor's behavioral characteristics at the current wake-up time; determining the equivalent temperature of the crystal oscillator at the current wake-up time based on the time deviation sequence, voltage sequence, and processor behavioral characteristics; testing the target test frequency of the crystal oscillator with multiple different test capacitors connected using a matched test strategy based on the equivalent temperature of the crystal oscillator at the current wake-up time; and determining the final target capacitor connected to the crystal oscillator based on the target test frequency of the crystal oscillator with multiple different test capacitors connected and the multiple different test capacitors. This method can achieve self-calibration of the crystal oscillator frequency.

A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor package structure includes a substrate, a first electronic component, and a support component. The first electronic component is disposed on the substrate. The first electronic component has a back surface facing the first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The back surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.

The invention discloses a high-precision temperature control circuit of a self-adaptive heating and cooling constant-temperature crystal oscillator, which is characterized in that on the basis of a traditional thermosensitive bridge and a heating circuit, a switch driving mode of a driving circuit is changed into a linear mode, namely a linear voltage comparison circuit is added, and meanwhile, a proportional-integral-differential (PID) circuit is connected behind the linear voltage comparison circuit, so that the temperature of the constant-temperature crystal oscillator is controlled. And the proportional-integral-differential (PID) circuit is connected with the heating / cooling circuit. When the thermo-sensitive bridge is unbalanced, the thermo-sensitive bridge generates a voltage signal difference related to temperature, and the voltage difference passes through the linear voltage comparison circuit and then is subjected to proportional-integral-differential (PID) operation to drive a thermoelectric cooler (TEC) of the heating / cooling circuit to heat or cool a circuit board where the thermo-sensitive bridge is located. The linear comparison circuit and the PID circuit are matched to regulate and control the voltage difference, then the heating / cooling circuit is controlled, the isolation degree is enhanced, the problem that temperature control fails when the external environment temperature exceeds the set temperature can be effectively solved, control is not in an on state or an off state any more and is related to the amplitude of the voltage difference, and the control reliability is improved. In this way, the temperature control precision is improved, and the temperature overshoot phenomenon is well restrained under the cooperation of the PID circuit.

Provided are a circuit device, an oscillator, and a processing system that can effectively use a temperature sensor circuit of the circuit device to perform accurate temperature detection. The circuit device includes an oscillation circuit that generates an oscillation signal using a vibrator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that temperature-compensates an oscillation frequency of the oscillation signal based on the temperature detection data; a memory that stores correction data for correcting the temperature detection data to find a temperature; and an interface circuit that outputs the temperature detection data and the correction data.

Methods, systems, and computer program products are presented herein for circuit timing using ultra-low power (ULP) timing circuit systems. A ULP timing circuit system comprises a receiver circuit, phase lock loop (PLL) circuit, crystal oscillator (XO) circuit, temperature sensing and calibration circuit, and temperature compensation circuit. The receiver circuit is configured to receive a reference clock signal. The XO circuit is configured to produce an output clock signal. The PLL circuit is configured to produce a control signal based on the reference clock signal and output clock signal. The temperature compensation circuit is configured to produce a compensation signal based on an operating temperature. The temperature sensing and calibration circuit is configured to sense the operating temperature and to calibrate the XO circuit based on the operating temperature, control signal, and compensation signal to lock a frequency of the output clock signal to the reference clock signal.

The present application relates to the field of integrated circuit design, in particular to a clock source with temperature process voltage compensation. The present application improves the existing temperature process compensation module, so that the temperature process compensation module can compensate the voltage variation of temperature and process at the same time; a selection module is added between the temperature process compensation module and the voltage controlled oscillator, the four variation voltages output by the temperature process compensation module are compared, the largest variation voltage under the current temperature condition is selected as the compensation voltage Vctrl and output to the voltage controlled oscillator; at this time, the control voltage obtained is a curve fitted by straight lines with different slopes, which can be applied to the case of large frequency and large temperature variation, the fitting is very good, and the output frequency error is very small.

Embodiments relate to a frequency generator and a frequency correction method for a frequency generator, which have the purpose to provide a frequency correction technology that actively responds to continuous frequency fluctuations of a clock signal through a frequency measurement period of at least two unit periods. The frequency generator comprises: an oscillator which generates an oscillator clock signal; and a frequency correction circuit which selectively operates in one of a normal mode and a fast mode, which have different correction periods according to the state of the oscillator clock signal.

Disclosed is a quartz oscillator system comprising: a quartz oscillator comprising a quartz crystal and an oscillator circuit whose frequency is based on a resonant frequency of the quartz crystal; a monitoring module for monitoring an output frequency of the quartz oscillator; a control system external to the quartz oscillator, and configured to compare the output frequency with a setpoint frequency, and apply an adjustment signal to an electronic circuit of the quartz oscillator to adjust a frequency of the quartz oscillator based on the comparison with the reference frequency.