394results about "Generator stabilization" patented technology

The invention provides a crystal oscillator and an atomic clock, and relates to the technical field of oscillators, the crystal oscillator comprises a packaging cavity, a crystal, a temperature sensor and a cantilever beam assembly, the crystal, the temperature sensor and the cantilever beam assembly are arranged in a containing cavity of the packaging cavity, and the packaging cavity is of a vacuum packaging structure. The crystal and the temperature sensor are arranged on the cantilever beam assembly, the crystal and the temperature sensor are electrically connected with different connection points of the packaging cavity through the cantilever beam assembly, and the temperature sensor is arranged around the crystal; the cantilever beam assembly comprises a heating module, and when the temperature sensor monitors that the temperature of the area where the crystal is located is smaller than a preset temperature threshold value, the heating module heats the crystal. The energy loss of air damping to the high-frequency vibration of the crystal is eliminated, the Q value is improved, and the phase noise suppression capability is enhanced; accurate control over the temperature of the area where the crystal is located is achieved, the thermal response speed and the temperature control precision are improved, and the problem that an existing crystal oscillator is poor in stability is solved.

To provide a temperature-compensated crystal oscillator capable of coping with miniaturization and limitation of thermal capacity, a method of manufacturing the same, and an electronic apparatus equipped with the temperature compensated crystal oscillator.SOLUTION: A temperature-compensated crystal oscillator 30 includes: a crystal resonator 31; a temperature-compensated oscillation chip 32 with a built-in temperature sensor; an insulation layer 33; and a first electrode structure 34. The crystal resonator includes: a vibration element 311; and an airtight packaging structure 312 packaged on an outer periphery of the vibration element. The temperature-compensated oscillation chip 32 is disposed on one side of the hermetic sealed structure. The insulation layer covers at least one side of the temperature compensation oscillation chip and the airtight packaging structure, and includes a first via hole 331 formed with a conductive material and a heat insulation cavity 36 including a sealed cavity or a semi-sealed cavity. The insulation cavity has gas or is in a vacuum state. The first electrode structure is disposed on the insulating layer and electrically connected to the temperature-compensated oscillation chip through the conductive material in the first via hole.SELECTED DRAWING: Figure 3

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

Embodiments herein relate to an apparatus and method for calibrating a notch filter which filters a power supply signal for a voltage-controlled oscillator (VCO). In one aspect, a control circuit performs a number of calibration cycles for the filter to determine a value of a calibration code for the filter which minimizes a change in a frequency of the output signal of the VCO due to a change in the voltage of the power supply signal. After each calibration cycle, the calibration code is adjusted based on whether the frequency of the output signal increase or decreases. The calibration cycles can therefore converge on an optimal calibration code which minimizes the change in frequency due to the change in voltage. This minimizes a sensitivity of the VCO to noise in the power supply signal.

A clock generation circuit has a voltage-controlled oscillator that includes a first transistor pair coupled in series between a power rail and ground, a replica transistor pair coupled in series between a reference node and ground, a current source having an output coupled to the reference node. The current source is coupled to a control signal that determines amplitude of current flowing through the replica transistor pair. A voltage regulator has an input coupled to the reference node and an output coupled to the power rail. The voltage regulator is configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. Each transistor in the replica transistor pair is collocated on an integrated circuit with and has a same type as a corresponding transistor in the first transistor pair.

The invention relates to the technical field of duplexers, and discloses a duplexer temperature compensation parameter automatic adjusting method and device. The method comprises the following steps: performing working temperature sampling on a duplexer to obtain temperature sampling data, and performing distribution feature extraction on the temperature sampling data to obtain temperature feature data; inputting the temperature feature data into a mechanism information neural network for feature reconstruction to obtain temperature compensation features; performing radial basis function neural network mapping on the temperature compensation characteristics to obtain a duplexer frequency drift state quantity; performing sliding window adaptive Kalman filtering operation on the frequency drift state quantity of the duplexer to obtain a compensation parameter; the compensation parameters are input into a feedforward compensation controller, a voltage-controlled resonator of the duplexer is adjusted through a sliding mode control structure, a frequency compensation signal is obtained, and stable compensation of the frequency of the duplexer is achieved.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The invention discloses a GPS oscillator taming system and method based on PID parameter adaptive adjustment, and the system comprises a forgetting factor dynamic updating module which is used for dynamically updating a forgetting factor with the variance of the frequency error of VC-TCXO as a negative index; the system identification module is used for estimating ARX model parameters of the VC-TCXO by adopting a recursive least square algorithm with the updated forgetting factor; the model parameter mapping module is used for mapping the estimated ARX model parameters to obtain PID control parameters; the incremental PID controller is used for calculating a frequency control word increment based on the frequency error; the digital-to-analog converter is used for calculating according to the frequency control word increment to obtain a frequency control word and converting the frequency control word into analog voltage; and the VC-TCXO is used for obtaining the frequency of the GPS reference signal based on the analog voltage corresponding to the frequency control word so as to complete frequency taming. The method is high in calculation efficiency and robustness, and can adapt to the dynamic change and external disturbance of the controlled object in real time.

The embodiment of the invention discloses a clock source and electronic equipment, and belongs to the technical field of integrated circuits. The clock source comprises a plurality of inverter chain loops, the plurality of inverter chain loops comprise a main loop and at least two auxiliary loops, and the main loop is respectively coupled with the at least two auxiliary loops to construct at least two coupling relations. According to the embodiment of the invention, the problem of oscillation mode ambiguity of a clock source design scheme capable of improving the oscillation frequency in the related technology is at least solved.

The invention discloses a constant-temperature crystal oscillator and rubidium clock combined taming device and method, and relates to the technical field of time frequency, and the device comprises a single-chip microcomputer, an FPGA module, a TDC module, a rubidium atomic clock and a constant-temperature crystal oscillator. The FPGA module is connected with the single-chip microcomputer, the TDC module, the rubidium atomic clock and the constant-temperature crystal oscillator, the FPGA module is used for receiving a reference 1PPS signal input from the outside, the single-chip microcomputer is connected with the constant-temperature crystal oscillator through the DAC module, the TDC module is connected with the single-chip microcomputer through an SPI bus, the TDC module is used for measuring the phase difference, and the single-chip microcomputer is used for adjusting the voltage control of the constant-temperature crystal oscillator or the frequency of the rubidium atomic clock; and the FPGA module communicates with the rubidium atomic clock through a UART serial port. The output frequency has the characteristics of a constant-temperature crystal oscillator and a rubidium atomic clock at the same time, and low noise and high stability are achieved; a taming state can be quickly entered to output an accurate clock without waiting for preheating of a rubidium clock during startup; a serial taming mode is avoided, parallel taming is adopted, and when one clock source is abnormal, clock hot backup can be achieved.

The thermosensitive crystal resonator comprises a base, a quartz wafer and a thermistor, the base comprises a base bottom plate, a base middle plate and a base wall which are sequentially arranged from bottom to top, an inner cavity is defined by the upper end face of the base middle plate and the inner wall of the base wall, an upper end opening of the inner cavity is sealed through an upper cover, and a lower end opening of the inner cavity is sealed through a lower cover. A center through hole is longitudinally formed in the middle of the upper end face of the base middle plate, a thermistor is installed in the center through hole, side edge through holes are formed in the positions, located on the two sides of the center through hole, of the upper end of the base middle plate respectively, embedded blocks are installed in the side edge through holes, a plurality of honeycomb holes are formed in the upper portions of the embedded blocks, and the honeycomb holes are filled with conductive buffer rubber. And the upper ends of the two embedded blocks are connected with a quartz wafer through conductive silver adhesive. By optimizing multiple designs of the base structure, the honeycomb buffer structure, the close-range thermosensitive compensation arrangement structure and the double-sealing structure, temperature compensation precision, stress buffer high efficiency and sealing performance long-term performance are achieved.

Embodiments herein relate to a system which predicts the frequency or phase offset of a primary clock signal relative to a stable reference such as an atomic clock based on the frequency or phase offsets, respectively, of secondary clock signals relative to the frequency or phase, respectively, of the primary clock signal. The system can include a neural network which is trained to learn a correspondence between the offset of the primary clock signal relative to the stable reference and the offsets of the secondary clock signals relative to the primary clock signal. The training can include varying environmental conditions such as temperature, vibration, pressure, humidity or magnetic field. Once trained, the neural network can be used to provide a stable output clock signal based on the primary clock signal and its predicted offset.

The invention relates to an A-f effect-based MEMS oscillator active temperature compensation method and system, the system is composed of a closed-loop oscillation circuit and a frequency drift compensation control circuit, an upper computer in the frequency drift compensation control circuit calculates an error between an actual frequency and an initial set frequency according to the frequency, collected in real time, of an MEMS oscillator in the closed-loop oscillation circuit, and the error is calculated according to the frequency of the MEMS oscillator in the closed-loop oscillation circuit. The frequency difference is converted into alternating-current excitation voltage through a built-in compensation control algorithm, the response amplitude of an MEMS oscillator in the closed-loop oscillation circuit is controlled in real time, the oscillation frequency of the MEMS oscillator changes along with the A-f effect, the oscillation frequency is stabilized near the set frequency all the time, and therefore compensation of frequency drift is achieved; according to the invention, the amplitude-frequency dependency relationship in the nonlinear MEMS oscillator is utilized to realize rapid, high-precision and low-power-consumption compensation of the temperature drift of the MEMS oscillator.

Disclosed is a clock system for generating an error-reduced clock output. In one implementation, the clock system includes a plurality of physical clusters of MEMS oscillators that provide a set of associated clock inputs to a processor. The processor performs RMS error correction and / or Kalman filtering and / or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. In another implementation, the processor configures the MEMS oscillators into a dynamic plurality of logical clusters instead of relying on a plurality of physical clusters. The processor performs RMS error correction and / or Kalman filtering and / or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. Also disclosed are techniques for compensating for errors related to temperature drift, tilt, and age drift of the MEMS oscillators.

The invention relates to the technical field of atomic frequency standards, in particular to a temperature drift suppression compensation system for an atomic frequency standard, which comprises a measured atomic frequency standard, a reference atomic frequency standard, a high and low temperature test box, a temperature measurement unit, a frequency adjustment unit, a frequency measurement unit and a temperature drift suppression compensation unit, wherein the tested atomic frequency standard is arranged in the high and low temperature test box; the measured atomic frequency standard outputs frequency signals to the frequency adjusting unit and the frequency measuring unit respectively; the reference atomic frequency standard outputs a reference signal to the frequency measurement unit; the temperature measurement unit is electrically connected with the high and low temperature test box and the temperature drift suppression compensation unit respectively; the frequency adjustment unit and the frequency measurement unit are electrically connected with the temperature drift suppression compensation unit. According to the invention, the temperature characteristics, accuracy and long-term stability of the cesium clock and the hydrogen clock can be improved by researching the temperature characteristics of the cesium atom frequency standard and the hydrogen atom frequency standard for the time keeping system and compensating the temperature drift suppression of the cesium atom frequency standard and the hydrogen atom frequency standard.

The invention belongs to the technical field of integrated circuits, and particularly relates to a PLL (Phase Locked Loop) adaptive trimming circuit. Comprising a sampling analog-to-digital conversion module, the sampling analog-to-digital conversion module comprises three sampling analog-to-digital conversion units, the in-phase input ends of the three sampling analog-to-digital conversion units are connected with voltage division nodes N1-N3 on a voltage division network respectively, the inverted input ends of the three sampling analog-to-digital conversion units are connected with control voltage VCTRL, and the output ends of the three sampling analog-to-digital conversion units output a control signal B, a control signal E and a control signal A respectively; wherein each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2 and a phase inverter INV1 which are sequentially connected in series; the digital trimming state machine is composed of a first gate circuit, an N-stage locking loop and a second gate circuit which are sequentially connected in series; the problem that the working characteristic of the PLL is obviously reduced after the PLL is influenced by the PVT is solved.

The present specification provides a crystal-less radio frequency (RF) transmitter for correcting frequency depending on temperature. The RF transmitter may include: an antenna that transmits an RF signal; a temperature sensor that measures ambient temperature; a digitally controlled oscillator (DCO) that digitally controls an output frequency for the RF signal; a frequency control and locking circuit (FCLC) that performs frequency locking related to correction of the output frequency; a digital-to-analog converter (DAC) that transmits a control voltage to the DCO based on a digital code received from the FCLC; and a memory in which a look up table (LUT) that corrects the output frequency based on the temperature is stored.

A temperature insensitive oscillator system. The system includes a substrate having a first surface and an opposing second surface, a CMOS device with one or more CMOS circuits attached to the first surface of the substrate, one or more piezoelectric transducers attached to an outer surface of the CMOS device, a voltage-controlled oscillator generating a RF frequency, which is transmitted as a plurality of short pulses to the one or more piezoelectric transducers, and one or more delays and oscillators using resistor and active components arranged alongside the piezoelectric transducers or on the CMOS device such that the voltage-controlled oscillator has minimal dependence on temperature, and has minimal deviation from a programmed frequency. In order to meet the requirement of low phase noise and high clock frequencies, a very quality factor resonator-based oscillator is phase locked with the BAW wave based oscillator to realize both an accurate and low-phase noise oscillator.

The invention discloses a low-stray and low-jitter frequency synthesizer which is composed of a phase error averaging circuit, a notch filter circuit and a local oscillator and feedback clock generating circuit. According to the circuit, a notch filter is added behind a loop filter, and notch is carried out at a reference frequency to suppress periodic modulation of the reference frequency on a voltage-controlled oscillator, so that reference spurious is suppressed; meanwhile, the invention provides a phase error averaging circuit for averaging quantization errors generated by an error summation modulator module in an instantaneous state, and suppressing quantization noise, thereby reducing decimal stray and decimal jitter.

A clock integrated circuit (100) is provided. The clock integrated circuit includes: a first clock generator (110) which includes a crystal oscillator (XTAL) configured to generate a first clock signal (fxo); and a second clock generator (120) which includes a resistance-capacitance (RC) oscillator (121) and a first frequency divider (122), and is configured to: generate a second clock signal (fRTC)using the first frequency divider (122) based on a clock signal (fRCO) output from the RC oscillator (121); perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider (122) to a first frequency division ratio based on the first clock signal (fxo) ; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

A delay-line circuit includes multiple variable-delay circuits and may generate an output signal that is a delayed version of an input signal. A calibration circuit includes an oscillator circuit that may generate an oscillator signal, and may include a replica of at least one of the multiple variable-delay circuits. The calibration circuit may perform an initial calibration of the delay-line circuit and, in response to a completion of the initial calibration, perform a background calibration of the delay-line circuit using the oscillator signal.

A semiconductor device includes: a semiconductor element configured to output a compensation voltage; a constant current circuit configured to output a constant current so as to compensate for temperature dependence according to the comparison of the compensation voltage and a reference voltage; an oscillation circuit configured to output an oscillation signal according to the constant current; a check voltage generation circuit configured to output a check voltage; and a signal generation circuit configured to output a temperature information signal corresponding to the compensation voltage and the check voltage.

An oscillator and method for maintaining a phase lock is provided. The oscillator may include an oscillator input port for receiving a reference signal, an oscillator output port for outputting an oscillator output, an unlocked oscillator oscillating in an unlocked state and outputting at a resonance frequency configured to drift in response to changes in an operating environment, and a phase locked loop (PLL) including a mixer having an output port configured to output the unlocked oscillator output mixed with a local oscillator output, the mixer output port in communication with a phase frequency detector and the oscillator output port, and the phase frequency detector generating a control signal based on a detected phase difference between the reference signal and the mixer output wherein the control signal adjusts the local oscillator output to compensate for the resonance frequency drift of the unlocked oscillator when mixed with the unlocked oscillator output.

The invention relates to the technical field of ultrasonic transducers, in particular to an ultrasonic transducer signal anti-interference transmission method and device, and the device comprises a signal preprocessing unit, an anti-interference unit, an isolation driving unit and a receiving demodulation and decoding unit. The signal preprocessing unit receives the original electric signal and performs differential amplification to generate a differential signal; the anti-interference unit collects the working environment temperature in real time through the temperature monitoring module, the coding strategy selection module and the modulation parameter control module dynamically select and optimize coding rules and adjust modulation parameters according to the working environment temperature, and the signal processing module converts differential signals into digital signals and completes coding modulation. The isolation driving unit performs signal isolation and power amplification; the receiving demodulation and decoding unit demodulates and decodes according to a corresponding rule and restores the ultrasonic signal; according to the invention, the coding rule, the modulation parameter and the heat dissipation strategy are dynamically adapted through temperature monitoring, the high-temperature performance drift of the anti-interference unit is inhibited, and reliable transmission of signals of the ultrasonic transducer is ensured.

Oscillator. The present invention provides an oscillator in which external heat is less likely to be transmitted to a vibrating element, and which has stable frequency characteristics. The oscillator has: an outer package; an inner package housed in the outer package and fixed to the outer package via a heat-insulating member; a vibrating element housed in the inner package; a temperature sensor; a first circuit element including an oscillation circuit that causes the vibrating element to oscillate and generates an oscillation signal that is temperature-compensated based on the temperature sensor, the first circuit element being housed in the inner package; and a second circuit element fixed to the outer package and including a frequency control circuit that controls the frequency of the oscillation signal.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

Aspects described herein include devices and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having an analog 1-bit sampler configured to sample a phase locked loop (PLL) output signal using a PLL reference clock to generate 1-bit samples and a digital phase computation and control circuit configured to receive the 1-bit samples from the analog 1-bit sampler and apply phase corrections to the PLL based on a phase error derived from the 1-bit samples.

The present invention relates to a radio transmitter (200) for operating a radio transmission system (100), preferably an SRD radio transmission system, between at least one radio transmitter (200), preferably between a plurality of radio transmitters (200), and a radio receiver (300) operating as a base station, wherein the respective radio transmitter (200) sends a telegram in the form of a data packet or a plurality of successively sent partial data packets to the radio receiver (300) at specific transmission times, each as a burst or bursts, wherein the respective radio transmitter (200) has a quartz crystal (201) which generates an oscillation for a timer, on the basis of which the timer determines the start and / or end times of the transmission of the respective burst, wherein the quartz crystal (201) is characterized by a quartz error profile (F1) which determines the original temperature dependence of the quartz error of the quartz crystal (201).To solve the problem of providing a radio transmitter that allows for the time-accurate transmission of telegrams even when its hardware does not enable alignment with the transmission frequency or carrier frequency of the radio signal, compensation means for the quartz error of the quartz crystal (201) are provided, which change, in particular shift, the quartz error curve (F1).

A circuit for reducing a temperature-induced frequency drift in a voltage to current (V2I) converter based voltage-controlled oscillator (VCO) for at least one wide band phase-locked loop (PLL), the circuit includes a V2I resistor node of the V2I converter, the V2I resistor node being at one end of a resistor, the VCO, and a current controlled oscillator (CCO), and the circuit is configured to provide a fixed offset current to the V2I resistor node to cause at least one V2I output current to have a value conversely proportional to absolute temperature (CTAT), the at least one V2I output current being output by the V2I converter, and mirror the at least one V2I output current to the CCO to reduce the temperature-induced frequency drift at a lower frequency band of the VCO.