24 results about "Digital analog" patented technology

The utility model discloses a USB high-fidelity decoder with a vibration unit, which comprises an integrated board. According to the utility model, the USB assembly, the system control assembly, the Bluetooth assembly, the first motor assembly, the first vibration driving assembly, the audio signal processor assembly, the loudspeaker assembly, the second motor assembly, the second vibration driving assembly, the earphone assembly and the high-fidelity digital-to-analog conversion assembly are integrated in the integrated board, so that the integrated board forms an integral module; the module can be attached to the surface of an object such as a mobile phone and can also be embedded into a mobile phone shell, the design that sound is experienced through the touch sense of the human body is achieved, a user can feel the sound in multiple dimensions on the basis of traditional auditory sense, the overall experience of entertainment equipment is enhanced, and meanwhile brand new understanding of music / sound is achieved.

A digital-to-analog converter includes multiple current conversion units, a current compensation unit, and a first amplifier. Each current conversion unit includes a first differential switch pair, a first stacked transistor, and a first current source transistor. The first differential switch pair is controlled by a first control signal and a first inverting control signal. The first stacked transistor and the first current source transistor are connected in series and coupled to the first differential switch pair. The current compensation unit includes a second stacked transistor. The input terminal of the first amplifier is coupled to the source of the second stacked transistor, and the output terminal of the first amplifier is coupled to the gate of the second stacked transistor and the gate of the first stacked transistor. This increases the output impedance.

This application provides a digital signal processing device, communication equipment, and optical communication system, relating to the field of electronic technology, for improving the scalability of DSP chips and supporting product flexibility. The digital signal processing device includes at least one die, each die comprising: a digital signal processor, a switch, N first digital-to-analog converters, M second digital-to-analog converters, and a digital preprocessing circuit; N is a positive integer. The N output terminals of the digital signal processor are respectively connected to the N first terminals of the switch, and the N output terminals of the digital signal processor are also respectively connected to the N input terminals of the digital preprocessing circuit. The N first output terminals of the digital preprocessing circuit are respectively connected to the N second terminals of the switch, and the N second output terminals of the digital preprocessing circuit are respectively connected to the input terminals of the M second digital-to-analog converters. The N third terminals of the switch are respectively connected to the input terminals of the N first digital-to-analog converters.

A parallel data interface circuit, chip, electronic device, and parallel data transmission method are disclosed, applicable to the field of data communication. The parallel data interface circuit is used for parallel conversion and transmission between signals in the digital domain and signals in the analog domain within the chip. The parallel data interface circuit includes a digital-to-analog conversion interface and a first circuit located in the analog domain. The digital-to-analog conversion interface is configured to perform parallel conversion between N analog signals and N digital signals. The first circuit includes N data lines, configured to transmit N analog signals in parallel through the N data lines. At least one of the N data lines is divided into multiple data traces, and a buffer is provided between every two adjacent data traces to drive the transmission of analog signals in the first data line. The data traces farther from the digital-to-analog conversion interface have a wider line width. This parallel data interface circuit can improve data transmission speed and achieve high-speed communication.

This invention relates to the interdisciplinary field of computer-aided design and computer-aided engineering, and discloses a method for the collaborative design of wooden building complexes and green space thermal environment based on digital simulation. The method includes: performing bidirectional coupled finite element analysis, dynamically reconstructing near-field radiation shading and airflow fields during morphological iteration to correct water demand, and calculating heat transfer and dynamic evaporation; introducing volumetric moisture content to quantify the water deficit index, activating an inverse topology generation algorithm, generating a microfluidic water-guiding geometry based on the condensate distribution on the wooden surface, and precisely guiding water to the target root system nearby; constructing a global objective function composed of building heating and cooling loads and water deficit, placing the above process in a global optimization loop, and continuously iteratively adjusting the macroscopic building morphology and microfluidic water-guiding topology within a controlled construction parameter space using a heuristic algorithm until convergence, outputting the final model. This invention achieves proactive and precise collaborative optimization of building spatial morphology and microclimate water cycle.

This invention discloses an oral digital twin simulation platform, belonging to the field of digital simulation technology. The oral digital twin simulation platform includes: a channel construction module, a simulation prediction module, a deviation mapping module, a fusion rendering module, and a feedback calibration module. This invention constructs parallel precise data channels and time-varying prediction channels, uses physiological rules for dynamic prediction, compares the deviations between the two in real time and presents them as a visual cloud map, and continuously optimizes the prediction rules based on a feedback calibration mechanism using new measured data. This achieves dynamic calibration and accurate prediction of the digital twin, enabling it to autonomously evolve over time and continuously approach the real physiological state. This solves the problem in existing technologies where the digital twin gradually deviates from the real state during treatment due to a lack of dynamic updates and calibration.

It is described a transmitter device (100) and a method for transmitting an analog signal (251, 261) via an electric cable (192). The transmitter device (100) comprises (a) a signal generation circuit (210) for generating a digital transmit signal (211) comprising a sequence of transmit symbols; (b) a filter circuit (230) for spectrally shaping the generated digital transmit signal (211, 221) and for outputting a filtered digital transmit signal (231); (c) a switching unit (240) comprising (c1) a first input terminal (242) for receiving the filtered digital transmit signal (231), (c2) a second input terminal (244) for receiving another digital transmit signal (297), (c3) an output terminal (246) for outputting a digital transmit output signal (241), wherein the digital transmit output signal (241) is based on, depending on a switching state of the switching unit (240), the filtered digital transmit signal (231) or the another digital transmit signal (297), and (c4) a control terminal (248) for receiving a control signal (285) from a control circuit (280), the control signal (285) being indicative for the switching state. The transmitter device (100) further comprises the control circuit (280); and a digital to analog converter (250) for receiving the digital transmit output signal (241) and for converting the received digital transmit output signal (241) to the analog signal (251, 261).

The utility model relates to a wireless transformer winding deformation detection device belongs to transformer winding deformation detection field. Solve the problem that cable lengthens and wired connection cannot realize data synchronous acquisition caused by transformer high altitude operation. It includes: excitation end and response end realize data transmission through wireless communication module, excitation end includes signal generating circuit, excitation output end and excitation end main control chip, response end includes signal acquisition circuit, response input end and response end main control chip, through signal generating circuit, signal conversion excitation external transformer winding is carried out, and excitation end input end inserts the first section of external winding and collects digital signal, and through ADC digital analog conversion is transmitted to excitation end main control chip, and excitation end main control chip will analog signal transmission to transformer winding, and response end carries out AD conversion according to the size of external winding impedance through signal acquisition circuit, and response end main control chip will digital signal through wireless communication module and upload host computer, be used for electric power detection field.

This application relates to a digital slope analog-to-digital converter and a signal conversion method. The digital slope analog-to-digital converter includes a charge-injection digital-to-analog converter circuit, a comparator circuit, a detection circuit, and a control logic circuit system. The charge-injection digital-to-analog converter circuit includes multiple capacitors and samples multiple input signals through these capacitors, generating multiple signals. The comparator circuit compares these multiple signals to generate multiple decision signals. The detection circuit generates an index signal based on the multiple decision signals. The control logic circuit system generates an enable signal based on the index signal and generates a digital output when the comparator circuit detects a crossover point of the multiple signals. The charge-injection digital-to-analog converter circuit gradually adjusts the charge stored in at least one of the multiple capacitors according to the enable signal until the comparator circuit detects the crossover point.

This invention relates to the field of optical element fabrication technology and discloses a system for fabricating microstructured optical elements. The system includes a light source, a beam shaping assembly, a beam splitting assembly, a spatial light modulator, an optical lens assembly, and a photosensitive material. After beam expansion or shaping, the incident light from the light source is split by the beam splitting assembly and then shines onto the spatial light modulator. The spatial light modulator loads a zone plate image or a digital analog optical element image, modulating the incident light to form a specific wavefront. This specific wavefront is spatially mapped by the optical lens assembly to form a wavefront associated with the optical element at a specific location. After exposing the photosensitive material at an appropriate position and performing corresponding processing, a microstructured optical element with the same or similar function as the optical element can be obtained. In the context of the rapid development of digital technology, microstructured optical elements, as an important type of optical element, have broad application prospects.

Embodiments of the present disclosure relate to the technical field of optical transmission networks, and provide a clock synchronization device, an optical transmitter, and an optical receiver. The clock synchronization device comprises: a phase detection module configured to obtain first total phase error information on the basis of a service recovery clock and a first phase-locked clock, wherein the first phase-locked clock is obtained from a first phase-locked loop of a digital-to-analog converter; and a loop filter configured to obtain first adjustment information on the basis of the first total phase error information, so that the first phase-locked loop obtains a second phase-locked clock on the basis of the first adjustment information, and the digital-to-analog converter converts service data into analog data on the basis of the second phase-locked clock, wherein the service recovery clock is a sampling clock for the service data.

This invention discloses a source driving device, comprising a first digital-to-analog converter (D / A converter) and a second D / A converter for driving sub-pixels of different colors. Each D / A converter outputs at least one output voltage based on an N-bit data code, and includes multiple sub-D / A converters, an interpolation circuit, and a switching circuit. Each sub-D / A converter receives m bits from the N-bit data code to generate a set of intermediate voltages. The interpolation circuit performs interpolation based on k bits from the N-bit data code and an interpolation control signal for a selected set of intermediate voltages to generate an output voltage. The switching circuit electrically connects the interpolation circuit to a selected sub-D / A converter used to output the selected set of intermediate voltages. The interpolation circuits in the first and second D / A converters perform interpolation based on different numbers of interpolation bits.

This invention discloses a control circuit for a feedforward equalizer and the feedforward equalizer thereof. The control circuit includes a feedforward equalizer controller and an impedance control loop. The feedforward equalizer has multiple voltage-mode drivers that are commonly coupled to an output terminal. The feedforward equalizer controller receives a base current from a current generator and includes a current-to-analog converter and a current mirror. The current-to-analog converter generates a reference current based on the base current. The current mirror mirrors the reference current to generate at least one first reference voltage and outputs the at least one first reference voltage to at least one first voltage-mode driver. The impedance control loop generates a second reference voltage based on the at least one first reference voltage and outputs the second reference voltage to at least one second voltage-mode driver.

The present application belongs to the field of digital-analog hybrid integrated circuits, and particularly relates to an asynchronous envelope detector based on zero-crossing events of an input signal. The asynchronous envelope detector based on zero-crossing events of the input signal can flexibly adapt to input signals of different frequencies, and the detection timing thereof is directly driven by zero-crossing events of the input signal, so that real-time envelope detection can be realized without an external clock. The design completely relies on dynamic characteristics of the input signal itself to realize asynchronous adaptive operation, so that the working frequency of the envelope detector can be automatically adjusted according to the change of the input signal frequency, thereby maintaining stable detection precision and rapid response capability under the condition of wide-band signals from low frequency to high frequency. The present application does not require complex clock distribution and control logic, significantly reduces system power consumption and design complexity, can realize high real-time and high energy efficiency envelope extraction in a high-speed signal environment, and is very suitable for integrated implementation and high-speed signal processing applications.

A digital to analog converter includes multiple switching current cells, an offset current cell, and a first amplifier. Each of the switching current cells includes a first differential switch pair, a first stack transistor and a first current source transistor. The first differential switch pair is controlled by a first control signal and a first inverted control signal. The first stack transistor and the first current source transistor are coupled in series and are coupled to the first differential switch pair. The offset current cell includes a second stack transistor. An input terminal of the first amplifier is coupled to a source of the second stack transistor. An output terminal of the first amplifier is coupled to each of a gate of the second stack transistor and a gate of the first stack transistor.

This invention provides a waveform generation circuit, a control chip, and a waveform generation method. The waveform generation circuit includes a storage circuit, a counter, a first digital-to-analog converter (DAC), a second DAC, and a logic circuit. The storage circuit stores multiple digital values. The counter adjusts a count value. The first DAC sequentially converts multiple first input values ​​to generate a first waveform. The second DAC sequentially converts multiple second input values ​​to generate a second waveform. Whenever the count value equals an initial value, the logic circuit selects a digital value as a first input value. After the count value equals a threshold value a preset number of times, whenever the count value equals the threshold value, the logic circuit selects a digital value as a second input value.

The output power of the digital-to-analog converter (DAC) can be set independently of the board-level power supply. [Solution] The DAC230 adjusts the total current (I) of the switch cell 310 within the DAC by adjusting the shunt current control signals (SCCS1, SCCS2) applied to a pair of programmable shunt current sources 335b and 335c with opposite polarity to the tail current control signal (TCCS) applied to the programmable tail current source 335a. total Maintain the output voltage (V) at a controllable operating point. A controlled common-mode voltage or operating point is possible, allowing the output voltage (V) to be maintained at a controllable operating point. outp , V outn This allows for reduced device voltage stress over a wider dynamic range.

The utility model relates to resistance test technical field, and disclose a thermistor test system, including temperature control module and digital analog conversion module, temperature control module is heating cooling platform, temperature sensor, relay and singlechip development board constitute closed loop temperature control system, digital analog conversion module is analog digital converter and development board links, and the accurate measurement of thermistor value is realized to cooperation standard pull -up resistance. Through PC end control program realizes temperature setting, data acquisition and processing, can automatically complete thermistor's temperature - resistance characteristic curve test. The utility model adopts modularization design, can realize real -time temperature and resistance measurement, has promoted test efficiency and precision, is suitable for thermistor's semi -automatic test.

The application discloses a three-layer digital-analog hybrid beamforming array and a MIMO transceiving system architecture. The three-layer digital-analog hybrid beamforming array comprises, along a signal transmitting direction, a third-level subarray with a digital full-connection architecture, a second-level subarray with an analog subarray connection architecture and a first-level subarray with an analog full-connection architecture in sequence; along a signal receiving direction, the three-layer digital-analog hybrid beamforming array comprises, in sequence, the first-level subarray with the analog full-connection architecture, the second-level subarray with the analog subarray connection architecture and the third-level subarray with the digital full-connection architecture. The application combines the advantages of a traditional full-connection hybrid beamforming architecture and a subarray connection beamforming architecture, realizes a large-scale three-layer digital-analog hybrid beamforming array, simultaneously generates multiple beams, and has the advantages of high system beamforming performance and low circuit design and baseband signal processing complexity.

The invention provides a light compensation circuit, a pulse blood oxygen simulation system and a light compensation method, and relates to the technical field of blood oxygen detection.The light compensation circuit comprises an ambient light detection circuit, an ambient light simulation generation circuit and a compensation superposition circuit; the ambient light detection circuit comprises a light sensor, a first operational amplifier, a first resistor and a microprocessor; the optical sensor is connected with the inverted input end of the first operational amplifier, the inverted input end of the first operational amplifier is connected with the output end of the first operational amplifier through the first resistor, and the output end of the first operational amplifier is connected with the input end of a digital analog converter port of the microprocessor. The output end of the digital analog converter port of the microprocessor is connected with the first input end of the compensation superposed circuit, and the output end of the ambient light analog generation circuit is connected with the second input end of the compensation superposed circuit. Therefore, the resistance of the system to ambient light interference is effectively improved.

The present invention relates to apparatuses for digital-to-analog conversion with improved performance and related methods. In one exemplary embodiment, an apparatus includes a DAC for converting a digital input signal to an analog output signal. The DAC includes a decoder that decodes the digital input signal and provides a first set of control signals and a second set of control signals. The DAC also includes a resistor DAC (RDAC) that provides a first voltage and a second voltage in response to the first set of control signals. The DAC further includes an interpolator that is coupled to receive the first voltage and the second voltage in response to the second set of control signals and provide a first analog signal.

The present application relates to the technical field of digital simulation, and provides a ballast model generation method and device. The ballast model generation method comprises: determining a particle size grading standard of ballast; obtaining a size range of the ballast based on the particle size grading standard; generating a random convex hull in the size range; and performing different scale recess processing on at least two face sheets of the random convex hull respectively to generate a ballast model. The particle size grading standard determines the size distribution characteristics of the ballast particle group, the particle size grading standard is converted into the size range of the ballast, the distribution requirement of the group level can be decomposed into the generation constraint of the individual particle, the random convex hull generated thereby provides a basic grid structure for subsequent multi-scale recess processing, the recess processing with different scales is applied to the random convex hull, the multi-level roughness and irregularity can be introduced, so that the roughness and irregularity of the real ballast particle surface are simulated, and the accuracy of the simulation result based on the ballast model in reflecting the real mechanical performance of the ballast layer is improved.

A 10BASE-T transmitter and a 10BASE-T transmission method are provided. The 10BASE-T transmitter includes a Manchester encoder circuit, a waveform shaper circuit, and a digital-to-analog converter circuit. The Manchester encoder circuit applies Manchester encoding to an input data to generate an encoded data. The waveform shaper circuit converts the encoded data into a plurality of digital codes. The digital-to-analog converter circuit generates a transmission waveform in accordance with the plurality of digital codes. The waveform shaper circuit controls a portion of the plurality of digital codes to apply pre-compensation of inter-symbol interference to the transmission waveform.

The present disclosure relates to emulating mobile devices, and specifically to apparatuses, systems, and techniques for performing digital analog of wireless networks. In at least one embodiment, a processor generates a virtual network simulation and combines user equipment in the virtual network simulation into a virtual cell to enable selection of at least one of two or more mobile device emulators based at least in part on two or more different physical resource block parameters corresponding to the two or more mobile devices.