324 results about "Field-programmable gate array" patented technology

The invention discloses a high-speed camera data self-adaptive two-stage caching system and method and a storage medium, and relates to the technical field of machine vision high-speed imaging and high-speed data storage, a preprocessing unit is used for performing deserialization and parallel connection, ROI cutting and gain adjustment on collected item number data, and writing incremental FrameID and cyclic redundancy check codes into each frame; the DDR annular cache unit comprises a monitoring module, a decision module and an execution module; the decision module is used for calculating an instantaneous cache demand Cnew and a dynamic cache occupancy U; the execution module expands and shrinks an annular buffer space in a single shot through a DDR4 controller, and outputs a Hi / Lo mark in real time through an occupancy rate comparator to drive an NVMe queue manager. According to the invention, on the premise of zero extra burden in a normal working condition, millisecond-level automatic capacity expansion and high-speed flood discharge can be realized in a sudden working condition, and real-time frame-level integrity verification can be completed on a local FPGA (Field Programmable Gate Array) side. The patent is subsidized by national key research and development plans, and the project number is 2023YFF0719700.

The invention discloses a low-rank DCT (Discrete Cosine Transform) compressed sensing algorithm realized based on an FPGA (Field Programmable Gate Array), and relates to the technical field of image data processing, and the compressed sensing algorithm comprises the following specific steps: carrying out blocking processing on an input signal, dynamically adjusting the blocking granularity based on a calculation result of a signal local gradient entropy, and when the gradient entropy is higher than a set threshold value, adopting fine granularity blocking, when the frequency is lower than a threshold value, coarse granularity partitioning is adopted, the partitioning granularity is dynamically adjusted within a preset range, discrete cosine transform is conducted on the partitioned signals, the spectrum entropy of coefficients after transform is calculated, and the number of the reserved low-frequency coefficients is dynamically adjusted according to the magnitude of the spectrum entropy. According to the dynamic blocking strategy based on the gradient entropy, the compressed sensing algorithm can automatically adjust the blocking granularity according to the local features of signals, so that the compression ratio of a complex texture region and a smooth region is improved, the blocking boundary is dynamically judged through the gradient entropy, it is ensured that pixel affiliation of an edge region is more accurate, and the blocking effect is reduced; and complete structure information is reserved for subsequent reconstruction.

The invention belongs to the technical field of multi-camera cooperative imaging, and discloses a multi-camera cooperative anti-shake control system and method. The method comprises the following steps: generating a global hardware trigger signal by using an FPGA (Field Programmable Gate Array), synchronizing IMU and multi-camera acquisition, and combining motion parameters to obtain a space-time aligned multi-view image; obtaining a global jitter component through feature extraction, motion vector field generation, depth map analysis and the like; fusing the data with IMU data to generate a trajectory, and inputting the trajectory into LSTM to obtain future compensation amount; and cutting based on deep layered transformation to obtain an EIS optimized frame, dynamically electing a main camera for super-resolution reconstruction, and outputting a final anti-shake video stream. Through multi-source information fusion, layered precise compensation and dynamic optimization, the accuracy and stability of motion estimation are remarkably improved, the jitter influence of the finally output video stream is effectively weakened, and the reliability and visual coherence of the image stabilization effect in a complex scene are ensured.

The invention relates to the technical field of data processing, in particular to an FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) cooperative network data processing system, which comprises a network interface module for receiving and forwarding an external data flow, and a protocol analysis module for distinguishing a service message and a protocol message based on a message header characteristic and a load mode; the service processing module executes protocol format conversion, security encryption and data extraction in the FPGA; the protocol stack interaction module transmits a protocol message to the CPU through the MAC layer communication interface; the protocol stack module activates necessary protocol services in the CPU and generates a resource allocation instruction; and the data integration module receives the service data flow and the protocol processing result, and dynamically adjusts the encryption rule. According to the invention, FPGA business data closed-loop processing and CPU protocol service physical isolation are realized, a double-processing-unit architecture supports financial signature and industrial filtering cascade operation, the MAC layer interface is additionally provided with cyclic redundancy check to guarantee transmission reliability, and equipment processing efficiency and anti-attack capability under a fusion scene are improved.

The invention provides a dynamic high-precision PTP (Precision Time Protocol) time synchronization system realized based on an FPGA (Field Programmable Gate Array), which comprises a master device and a slave device, and the master device and the slave device are connected through a PHY (Physical Layer) to carry out PTP time synchronization; the master device and the slave device have the same structure and comprise an FPGA and a voltage-controlled crystal oscillator; in the master device, the FPGA obtains the frequency difference and the phase difference between the master device and an externally input reference source, further adjusts the frequency of a voltage-controlled crystal oscillator, corrects a local time mark, and sends a PTP message to the slave device; and in the slave equipment, the FPGA obtains the frequency difference and the phase difference between the slave equipment and the master equipment based on the received PTP message, so that the frequency of the voltage-controlled crystal oscillator is adjusted, and the local time scale is corrected. According to the invention, low-cost and high-precision PTP time synchronization is realized.

The invention discloses a low-resource and low-energy-consumption remote sensing image brain-like computing system based on an FPGA (Field Programmable Gate Array), which belongs to the cross technical field of brain-like computing and remote sensing information processing, and comprises a data interaction module which is used for high-speed data transmission between a PC (Personal Computer) end and the FPGA and comprises a PCIe (Peripheral Component Interconnect Express) interface sub-module and a data transmission control sub-module; the storage control module is used for data interaction control of the off-chip DDR and the on-chip BRAM and providing efficient data supply for the processing engine; the processing engine module is used for simulating a brain-like pulse neural network to complete convolution calculation of the remote sensing image; comprising a convolution processing sub-module, a data storage sub-module, an input buffer sub-module and an output buffer sub-module. According to the low-resource and low-energy-consumption remote sensing image brain-like computing system based on the FPGA, the brain-like pulse neural network is adopted, the BRAM is allocated to store the intermediate computing result, and the computing unit is designed in combination with SNN characteristics, so that energy consumption and resource waste are effectively reduced, and computing efficiency is improved.

The invention provides a method for rapidly determining the center position of an electron cloud cluster of a reading circuit in an XS anode detector, and aims to solve the problems that the existing method for calculating the center position of the electron cloud cluster of the reading circuit in the XS anode detector cannot realize higher spatial resolution, or easily causes image distortion, and is inconvenient to use. The software processing speed is slow, the FPGA is not easy to implement, or the calculation error at the edge strip is relatively large. The method for rapidly determining the center position of the electronic cloud cluster of the reading circuit in the XS anode detector is realized by adopting an FPGA (Field Programmable Gate Array), the peak value of effective data of each channel is obtained through single-channel processing, and then a corresponding drop point distribution index code is generated through table look-up and cross-channel processing; and then adaptive weight selection is carried out according to the drop point distribution index code, so that the weight accuracy of weighted average operation is ensured, key support is provided for rapid and accurate calculation of the center position of the electronic cloud cluster, and high efficiency and accuracy of the whole data processing flow are ensured.

The invention relates to a full-unloading regular matching system and method based on an FPGA (Field Programmable Gate Array). The system comprises a regular rule compiling unit and an FPGA full matching unit, the regular rule compiling unit is used for receiving a regular rule set, extracting each rule fixed feature substring, compiling the uniform format isomorphic NFA, and constructing a mapping relation table of the substrings and the corresponding NFA; the FPGA full matching unit comprises a parallel high-speed character string matching engine array, a character string-NFA mapping table module, a full-quantity regular data memory, a reconfigurable general NFA engine module and a matching result output module; and the reconfiguration engine module is used for executing full unloading regular matching on the input network traffic: scanning the traffic through the engine array, screening to-be-verified traffic containing a fixed feature substring and outputting a substring identifier, querying the NFA identifier through the mapping table module, and loading NFA matching by the reconfiguration engine module. By adopting the method, low delay and high throughput performance of regular matching in a high-speed network environment can be ensured.

The invention discloses a business travel user real-time feedback and suggestion system, which relates to the technical field of mobile application development and multi-terminal adaptation, and is characterized in that an edge layer guarantees the completeness of offline scene data through a dynamic load adapter, starting a structured compression protocol in a weak network, switching a multi-mode enhancement protocol in a strong network and matching with a priority cache queue; the decision-making layer adopts a parallel processing unit accelerated by an FPGA (Field Programmable Gate Array), and a real-time stream filtering unit adopts SimHash fingerprints to remove duplication; the scene understanding unit fuses the spatio-temporal data to generate event tags; the grading response unit automatically triggers AI compensation and manual work orders according to risk grades; and the collaboration layer verifies the responsible party of the travel system on the premise of hiding the user ID based on the zero-knowledge proof gateway so as to realize cross-platform secure data exchange. According to the system, a three-layer intelligent architecture is innovatively constructed, and full-link real-time response of travel service is realized.

The invention discloses a multi-task parallel data stream processing method and device based on an FPGA (Field Programmable Gate Array), which are applied to the technical field of data processing. Carrying out normalization processing on the decoded data to generate a data stream in a unified format; performing coding and ID identification code embedding processing on the normalized data to generate to-be-stored data with an identifier; carrying out FIFO (First In First Out) buffering and write-in priority judgment on the coded data to generate priority queue data; dDR writing and BANK scheduling processing are carried out on the priority queue data, and stably stored parallel data are generated; carrying out reading and output coordination processing on DDR storage data to generate a continuous output data stream, and triggering a reading application by decoding ID identification code positioning data, reading FIFO according to depth scheduling and monitoring data volume by channel temporary storage FIFO; and performing dynamic bandwidth allocation and energy efficiency optimization on the whole data stream processing process to generate an efficient parallel processing result.

The invention provides a method for testing the communication bandwidth of a 10-gigabit network between an FPGA (Field Programmable Gate Array) and a CPU (Central Processing Unit), which is applied to a radar system. The FPGA completes a function of regularly generating data and a function of downlink transmission of the data; the 10-gigabit network exchange board card completes data transmission and sends data to the CPU board card through a 10-gigabit network; and the CPU board card receives the data and calculates the communication bandwidth and the network quality. According to the invention, the limitation of traditional single-port point-to-point transmission or simple multi-port parallel transmission on synchronization, load balancing or protocol overhead is solved, and a solution is provided for how to effectively utilize multiple ports, enable the multiple ports to simultaneously and efficiently work and ensure parallel transmission of data without mutual interference.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

The invention discloses a lining pipeline interface contact pressure distribution testing device and method, relates to the technical field of pipeline detection, and aims at solving the problem that in the prior art, interface contact pressure distribution is difficult to represent in a lossless and quantitative mode. The device comprises a testing machine moving platform, an overground control moving platform, a lining pipe wall testing claw, an ultrasonic signal transceiver and a three-dimensional imaging module, the testing claw carries four curved-surface ultrasonic probes, and signals are collected in a one-transmitting-multiple-receiving mode controlled by an FPGA (Field Programmable Gate Array); according to the method, a contact pressure characterization model is constructed through self-adaptive positioning and signal excitation and processing, and interface pressure distribution visualization is achieved in combination with a three-dimensional imaging technology. The method does not need to damage the pipeline structure, can accurately capture the spatial distribution characteristics of the contact pressure, is adaptive to the conventional detection of long-distance pipelines, provides a scientific basis for lining repair quality evaluation and pipeline operation safety, and is convenient to operate and high in applicability.

The invention relates to a satellite-borne super-large-scale digital phased array system based on a JESD204B clock synchronization network, and the system comprises a radio frequency antenna layer which is used for receiving and transmitting electromagnetic waves in a space, and completing the mutual conversion of a radio frequency signal and a space electromagnetic wave; the sub-array baseband layer is used for realizing S-band 64-path intermediate frequency signal sampling, transmitting and digital domain multi-beam synthesis in a transceiving link, realizing data transmission with the mother board clock layer, and completing a reconstruction function of a baseband module signal processing FPGA (Field Programmable Gate Array) through a low-speed interface; the mother board clock layer serves as a function of realizing data summarization and distribution and performs task scheduling and management on the whole digital phased array system, and a JESD204B clock tree network is designed in the board and is distributed to a synchronous clock of each baseband module so as to indicate a target signal to complete synchronous sampling and emission output. By adopting the system, access, efficient tracking and accurate pointing of massive ground users can be realized.

The invention relates to the technical field of digital signal processing, and particularly discloses a mixed precision low-resource digital control oscillator implementation method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: dividing a 32-bit phase accumulator into a high-bit 24-bit dominant frequency control section and a low-bit 8-bit dynamic compensation section, and carrying out the phase accumulation in parallel through double carry chains, the high-order section receives high 24 bits of a frequency tuning word FTW to control a dominant frequency, and the low-order section receives low 8 bits of the FTW and overlaps an overflow remainder to dynamically compensate for a phase error. According to the implementation method of the mixed precision low-resource digital control oscillator based on the FPGA disclosed by the embodiment of the invention, through collaborative innovation of mixed precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, the core problems of a traditional NCO in resource occupation, phase continuity, waveform precision and time sequence performance are systematically solved.

The invention belongs to the technical field of distributed optical fiber sensing (DAS) system signals, and discloses a time axis phase unwrapping method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps of phase data acquisition, stable group formation, phase progressive unwrapping, assembly line and cache cooperative processing and quality measurement closed-loop correction. According to the system, real-time phase extraction of interference signals is achieved through the FPGA demodulation unit, phase change is dynamically unwrapped through the reliable period screening unit and the phase progressive unwrapping unit, a self-adaptive unwrapping mechanism is formed in combination with anomaly judgment and threshold updating logic, and through collaborative design of an annular cache and a three-level assembly line comparator, the interference signal is obtained. According to the method, parallel transmission and time sequence synchronization of data are achieved, the precision and stability of phase unwrapping can be effectively improved in a complex noise environment, hardware delay and resource occupation are remarkably reduced, and the method is suitable for real-time signal unwrapping processing of a high-precision distributed optical fiber sensing system.

The invention provides a programmable frequency control array radar waveform generation system and method based on an FPGA, and belongs to the technical field of radar systems and digital signal processing. In order to solve the technical problems of complex hardware system, inflexible parameter adjustment and poor multi-channel synchronism of the traditional frequency control array radar, the invention provides an integrated high-performance solution. The system adopts an FPGA (Field Programmable Gate Array) architecture of an integrated processing system (PS) and programmable logic (PL). The method comprises the following steps: a PS end receives waveform control parameters of an upper computer through a communication interface and transmits the waveform control parameters to a PL end; and a plurality of parallel direct digital frequency synthesizer (DDS) modules in the PL end synchronously generate multi-channel digital baseband signals with programmable frequency offset at high precision according to the parameters under the unified driving of the FPGA global clock network. And the digital signal is subjected to digital-to-analog conversion and radio frequency front-end processing to finally form a transmitting wave beam. According to the invention, flexible programmability of parameters is realized by utilizing a PS-PL collaborative architecture, the synchronization precision of multi-channel signals is remarkably improved through a global clock network and a parallel DDS module generated in the FPGA, and meanwhile, the system has the advantages of high integration level and low complexity.

The invention discloses a gas leakage detection imaging device and method based on a single photon detection technology, and belongs to the technical field of gas detection and imaging. Aiming at the limitation problems of the existing gas leakage detection technology in the aspects of sensitivity, response speed, space imaging capability and anti-interference capability, nanosecond modulation control and synchronous photon counting are realized by utilizing an FPGA (Field Programmable Gate Array) through a visual gas detection imaging device combining an SPAD (Single Program Amplifier) array detector and a WMS modulation-demodulation mechanism; and the second harmonic of the absorption signal is further extracted by combining digital phase-locked amplification, so that gas leakage three-dimensional imaging with high spatial resolution, ppb-level sensitivity, strong background suppression capability and high time response is realized. The system has the advantages of high detection sensitivity, real-time imaging capability with high spatial resolution, high background light interference resistance and high signal-to-noise ratio, the demodulation method is novel, and the modular design has multi-gas compatibility and system expansibility.

The invention discloses a loader remote intelligent control system based on multi-network fusion and modular design, and relates to the technical field of loader remote control, and the loader remote intelligent control system comprises an equipment end, a remote control end and a cloud server end; the equipment end comprises the following hardware modules: a hardware sensing module which comprises a multi-type sensor array and a data acquisition unit and realizes real-time acquisition of mechanical parameters, environmental parameters and attitude data; and the main control processing module integrates a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array) acceleration unit, is internally provided with a QNX real-time operating system, and is used for data preprocessing, control logic execution and hardware drive management. Through a remote intelligent control scheme, an operator can operate and control equipment in a safe area, the operation safety is improved, the operability and flexibility of the equipment are enhanced, modular design is adopted to facilitate installation, maintenance and rapid deployment, and a multi-network fusion architecture ensures stable data transmission in different environments; the low-delay and accurate control technology realizes the undifferentiated response speed of remote control and field operation.

The invention discloses a module and a method applied to FPGA (Field Programmable Gate Array) remote upgrade configuration data integrity verification. The module and the method are realized by FPGA logic resources. The configuration data integrity verification module comprises a message filling module, a message expansion function module, a compression iteration module, a constant parameter matrix and a top layer control module. The message filling module is used for receiving original configuration data; the message expansion function module is used for expanding the message blocks output by the message filling module; the compression iteration module is used for hash compression operation; the constant parameter matrix is used for storing constant values required by compression operation; and the top layer control module is used for completing the connection of the sub-modules. Compared with the existing technical scheme, the scheme can realize the integrity verification problem of the configuration data generated by random errors and malicious tampering; by adopting the mode of'pipeline + iteration ', the real-time performance and the low-delay characteristic are ensured, the consumption of the FPGA logic resources by the module is reduced, and the FPGA logic resources can be flexibly deployed on the small-capacity FPGA.

The invention relates to a scale out network backup path fast switching notification system and method, and aims to solve the problem that the existing VRRP / BFD protocol switching time cannot meet the high real-time requirement of an AI server scale out network. The scheme is realized through a collaborative architecture of a CPU (Central Processing Unit), an inspection FPGA (Field Programmable Gate Array) and power supply monitoring: the CPU runs a VRRP / BFD (Bidirectional Forwarding Detection) protocol stack and maintains a state table, and the FPGA is responsible for detecting a power supply fault, a port fault and GPU alarm in real time, and generating and sending a pre-installed message in one main frequency period; and the power supply monitoring module ensures that power supply is maintained for more than or equal to 5ms after sudden power failure through the energy storage capacitor, so that complete transmission of fault messages is ensured. The system has the advantages that the system supports multi-scale out interface redundancy, the end-to-end delay of fault detection and backup path switching is smaller than or equal to 1ms by adopting a low-power-consumption switching chip and independent minimum power domain design, the fault response speed and reliability of an AI server scale out network are remarkably improved, and the system is suitable for guaranteeing the network continuity of a high-density AI training cluster.

The invention provides a multi-interface test tool and test method applied to an external component of a domain controller. The multi-interface test tool comprises an FPGA (Field Programmable Gate Array) unit, a storage unit, a power management unit, a plurality of component interface units and a debugging interface unit, and each component interface unit can be externally connected with an external component of a domain controller. And the FPGA unit can test the domain controller external component currently connected with each component interface unit by loading the test tool mirror image in the storage unit. According to the invention, testing of various external components of the domain controller can be completed through one testing tool, and parallel testing of multiple components is supported.

The invention relates to the technical field of parallel processing, and discloses an FPGA (Field Programmable Gate Array)-based ultra-wideband radar data processing method, which comprises the following steps of: acquiring ultra-wideband radar signals through a radio frequency direct acquisition framework, generating a noise reduction data stream, generating a target rate data stream, and acquiring a target rate data stream by setting the radio frequency direct acquisition framework and a plurality of division modules. When ultra-wideband radar signals are processed, GHz-level original data streams are directly captured, intelligent parallel path division is carried out, the feasibility of high-sampling-rate signal processing is guaranteed, meanwhile, the data streams are decomposed into multiple parallel processing channels, the synchronization problem and the spectrum integrity problem in a traditional narrowband method can be avoided in real time, and the method can be applied to the field of ultra-wideband radar signal processing. According to the method, the signal acquisition accuracy and the system reliability are ensured, the data processing error is further reduced, and the frequency deviation can be dynamically corrected through a zero-frequency centralization strategy in the frequency spectrum shifting process, so that the system can reduce the resource bottleneck and the signal distortion risk in single-path processing, and the signal purity and the anti-interference capability are ensured.

The invention discloses a multi-dimensional metering system and metering method based on an FPGA, and belongs to the technical field of electronic data processing, and the system comprises a data collection module which is used for obtaining and preprocessing multi-source sensing data; the simulator construction module is used for constructing a multi-physics field interference simulator and loading a geometric model and a physical response coefficient of a reference shadow workpiece, the reference shadow workpiece is digital representation of an actual measured workpiece, and the geometric model and the physical response coefficient of the reference shadow workpiece are mutually decoupled data sets; the vector field generation module is used for generating a pre-distortion vector field based on the output of the interference simulator and the reference shadow workpiece; and the interference identification module is used for extracting primary features from the multi-source sensing data. Through constructing a multi-physical field interference simulator and generating a pre-distortion vector field, physical state drift of a cross-sensing channel is accurately modeled, a multi-sensor data fusion error is reduced, and data consistency and reliability in a high-speed dynamic measurement scene are improved.

The invention discloses a standard output serial port based on an FPGA (Field Programmable Gate Array) and a working method thereof, a medium and equipment, and relates to the technical field of signal communication, the standard output serial port comprises a synchronous serial port control module, an FIFO (First In First Out) module, a frequency division module and a standard serial port output module, the synchronous serial port control module is respectively connected with the FIFO module, the frequency division module and the standard serial port output module; the synchronous serial port control module is used for instantiating and calling the FIFO module, the frequency division module and the standard serial port output module, the FIFO module is used for reading and writing an input signal, the frequency division module is used for improving the precision of aligning a synchronous signal, and the standard serial port output module outputs a serial signal based on the state of a state machine. According to the invention, the serial port output module can be universally applied to the requirement of converting parallel data into serial data. Compared with a CPU for realizing serial port communication, the method has the characteristics of lower clock jitter, high-precision alignment and predictable alignment error, and the reliability and certainty of the method have better guarantee capability.

The invention discloses a full-data backup method for a fast and slow operation period of an industrial controller. The full-data backup method comprises the following steps: detecting whether a main power supply is powered down or a backup command is received by an FPGA (Field Programmable Gate Array); if yes, the FPGA writes the latest fast-cycle integrity data into the power-down nonvolatile storage chip by comparing the integrity marks and the timestamps of the fast-cycle data of the data A area and the data B area of the memory chip; then, the FPGA writes the completeness data of the latest slow period into the power-down nonvolatile storage chip by comparing the completeness marks and the timestamps of the data of the slow period of the data A area and the data B area of the memory chip; according to the data backup method, data does not need to be selected, one cycle of complete data can be recovered under the condition of power failure or no power failure, common memory chips and power failure non-volatile storage chips are used, and cost and implementation complexity are effectively reduced.

The invention relates to the technical field of power transmission line monitoring, in particular to a power transmission line visual multi-dimensional monitoring system based on an AI model, which comprises an image acquisition module, an edge calculation module, a deep learning analysis module, an intelligent diagnosis module and a time sequence correlation analysis module. The image acquisition module acquires multispectral data through a visible light camera, an infrared thermal imager and an unmanned aerial vehicle; the edge calculation module adopts an FPGA (Field Programmable Gate Array) chip to realize data preprocessing; the deep learning analysis module comprises a feature fusion sub-module, an anomaly detection sub-module and a three-dimensional reconstruction sub-module which are respectively used for extracting multi-scale features, identifying equipment defects and constructing digital twin bodies; the intelligent diagnosis module integrates the knowledge graph to provide decision support; and the time sequence correlation analysis module is combined with an LSTM-GRU model to realize state prediction. According to the invention, through multi-source data fusion and intelligent analysis, the problems of many blind areas, low identification precision and the like in traditional monitoring are solved, and all-weather and intelligent monitoring, operation and maintenance of the power transmission line are realized.

The invention discloses a full-closed-loop control method for a humanoid robot joint module based on an FPGA (Field Programmable Gate Array), which relates to the technical field of robot control and comprises the following steps of: performing second-order active low-pass filtering and programmable gain amplification on analog signals of an encoder, a gyroscope and a force sensor to convert the analog signals into digital signals; a multi-dimensional feature sequence is constructed, temperature signals of a joint driver and an encoder are collected through a temperature sensor interface, a temperature drift model is constructed, and zero drift compensation parameters are obtained; further obtaining a joint elastic deformation error, and applying the joint elastic deformation error to an encoder signal for online offset correction; outputting a reconfiguration region selection signal based on the lightweight neural network; and triggering bit stream local refresh corresponding to the PR Region according to a region selection signal output by the lightweight neural network. The problem that a control loop is difficult to eliminate flexible errors due to the fact that a traditional rigid model or a constant parameter model is difficult to reflect deformation characteristics under the heat-lubrication-load combined action in real time is solved.

The invention discloses a Tranformer network-oriented hybrid precision multiplier, which is applied to an FPGA (Field Programmable Gate Array), and is used for allocating a target high-resolution image according to the weight precision of the weight data of the current layer of the target Tranformer network, the feature map precision of the feature map data of the target high-resolution image and a preset data allocation rule. Determining a first quantity of weight data and a second quantity of feature map data of a single calculation cycle; according to the first quantity of weight data and the second quantity of feature map data, recoding the weight data and the feature map data after determining a target recoding algorithm to obtain weight coded data and feature map coded data; performing multiplication calculation on the weight coding data and the feature map coding data in a single calculation period to obtain an initial product result of the single calculation period; and decoding the initial product result, and merging the multiple sub-feature map data of all the calculation periods corresponding to the current layer of the target Transform network to obtain target feature map data. According to the method, the resource utilization rate is improved on the basis of ensuring the model precision.

The invention provides a double-MCU (Microprogrammed Control Unit) hot backup control method based on an FPGA (Field Programmable Gate Array), and relates to the technical field of power supply system control. Comprising the following steps: acquiring fixed frequency self-checking PWM signals output by a main MCU and a standby MCU in real time by using an FPGA; measuring the frequency and the period of the fixed frequency self-checking PWM signal by using an FPGA internal counter to obtain a real-time frequency value, and comparing the real-time frequency value with a preset frequency threshold to obtain a frequency deviation; whether the frequency deviation is larger than a deviation threshold value or not is judged, if not, the main MCU and the standby MCU do not have faults, and if yes, deviation period monitoring is carried out, a monitoring result is obtained, and a fault signal is output according to the monitoring result; determining a fault type according to the fault signal; and determining an output signal according to the fault type and the input signal. According to the invention, the problems of single-point fault, poor information transmission real-time performance and low control logic accuracy of the double-MCU hot backup control system in the prior art are solved.