2469 results about "Field-programmable gate array" patented technology

A state machine gesture recognition algorithm for interpreting streams of coordinates received from a touch sensor. The gesture recognition code can be written in a high level language such as C and then compiled and embedded in a microcontroller chip, or CPU chip as desired. The gesture recognition code can be loaded into the same chip that interprets the touch signals from the touch sensor and generates the time series data, e.g. a microcontroller, or other programmable logic device such as a field programmable gate array.

An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).

The invention discloses a continuous Doppler US imaging system orthogonal intrinsic signal generation device, which comprise a field programmable gate array (FPGA), a crystal oscillator, a first digital-analog converter and a second digital-analog converter. The output end of the field programmable gate array (FPGA) is connected with the input ends of the first digital-analog converter and the second digital-analog converter; the crystal oscillator is respectively connected with the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the crystal oscillator is used for supplying synchronizing clock signals to the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the field programmable gate array (FPGA) is used for outputting the sine value corresponding to the phase value to the first digital-analog converter according to the input phase value and outputting the cosine value corresponding to the phase value to the second digital-analog converter; the first digital-analog converter is used for converting the sine value into the corresponding analog signals; the second digital-analog converter is used for converting the cosine value into the corresponding analog signals.

A network tap for enabling attached devices, such as an intrusion detection system, to transmit information into a communication line of the network without disrupting the network traffic on the communication line. When the attached device is an intrusion detection device, the network tap is connected to a firewall. An Ethernet switch or field programmable gate array (FPGA) is incorporated in the network tap to coordinate the transmission of device data to avoid data collisions with data transmissions already existing in the communication line. The network tap may be operated in various modes to accommodate different capabilities of attached devices. In addition, the network tap has various port configurations to allow a user to connect various attached devices through a single cable or dual cables and to connect various combinations of attached devices.

A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises the steps of providing a serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of the configuration SRAM and the user assignable SRAM by the row and column counters; performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T₀ trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.

A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

An adaptive gate drive for an inverter includes control circuitry having a Field Programmable Gate Array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a Trench Gate Insulated Gate Bipolar Transistor (IGBT device). The control circuitry provides switching signals for operating the switching device. In addition, the control circuitry receives signals of output current of the IGBT device, temperature of the IGBT device, and DC link voltage. The FPGA has a plurality of operating points stored therein. Each operating point has corresponding parameters for a control signal that is used to control the turn-on or turn-off behavior of the IGBT device. During operation, the control circuitry compares the measured current, voltage and temperature operating points stored in the FPGA and sends the corresponding parameters to the gate drive circuit. The gate drive modifies the signal on the gate of the IGBT accordingly and thereby optimizes the turn-on and/or turn-off behavior of the device based on actual operating conditions.

The invention discloses an extensible multichannel parallel real-time data acquisition device and method. The device comprises a PXIe (PCI (Peripheral Component Interconnect) Extensions for Instrumentation Express) backboard, a CPU (Central Processing Unit) board card and a plurality of FPGA (Field-Programmable Gate Array) acquisition cards; the PXIe backboard comprises a CPU motherboard slot, a clock board slot, a plurality of FPGA board card slots and a PCIe (Peripheral Component Interface Express)/PCI switching bridge; the data transmission between the CPU board card and the FPGA acquisition cards is achieved by PCIe switches, and the P2P (Peer-to-Peer) data transmission is carried out among the FPGA acquisition cards; a clock module provides a system differential clock, differential synchronization signals and differential star-shaped triggers through a clock bus and is downwardly compatible with a PXI clock; and the FPGA board card slots realize the compatibility between a PXI and a Compact PCIe board card through a PCI bus and the PCIe/PCI switching bridge. The invention further provides the method based on the device. The device and the method have the advantages of high sampling rate, fast data transmission and easiness for the large-scale extension of a plurality of board cards.

A user-configurable and/or self-configurable System on a Chip (SoC) device and corresponding remote programming method enabling the SoC to be reprogrammed multiple times from a remote chip file server. Once programmed with the desired SoC design, the device can be debugged remotely in real-time by one or more users. The device includes a helper microcontroller/programmer, and a Field Programmable Gate Array (FPGA) fabric which is divided into a plurality of programmable logic and clock driver domains that may be independently programmed by way of the helper microcontroller. Once programmed, the helper microcontroller can serve as a real-time monitor/data exchange sub-controller and/or may be used by the end application.

The invention discloses a system for updating an FPGA (Field Programmable Gate Array) configuration program from a long distance based on the control of a processor and a method for updating the FPGA configuration program from a long distance based on the control of the processor. The system comprises a processor module, an FPGA module, an SPI (Serial Peripheral Interface) memory module and a buffer module, wherein the processor module is connected with the SPI memory module and is connected with a communication interface, the SPI memory module is connected with the FPGA module, and the processor module is connected with the SPI memory module by the buffer module. When the configuration program of an FPGA requires to be updated, an upper computer or a terminal downloads the FPGA configuration program into the SPI memory module through the communication interface and the processor module, and the FPGA module can automatically load the configuration program memorized in the SPI memory module in a MasterSPI mode. According to the system and the method, the FPGA configuration program is updated from a long distance, the function of updating the configuration program on line under the non-outage situation is realized, and therefore, the system and the method are particularly suitable for on-site application.

The invention provides a test system and method for a single event effect of an SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array). The test system comprises a single chip microcomputer processor, an RS232 interface circuit, a USB (Universal Serial Bus) interface circuit, a test FPGA and a storage unit. The test system and method can be used for fault injection tests of a configuration memory and a BRAM (Battery Random Access Memory) of the SRAM type FPGA, and single event function interrupting detection, single event locking detection and single event turning detection including single event turning detection for a configuration storage region, the BRAM and a trigger of the SRAM type FPGA are realized. The invention has the advantages of simplicity in operation, entirety in detection, high accuracy, good real-time property and strong universality.

An image processing system whose circuit size is small, and whose dissipation power is small is provided. The image processing system executes digital image processing of an interval of active pixel in the condition that a first internal logic description is written in a field programmable gate array. Subsequently, in interval of non-active pixel with the exception of the interval of active pixel, the image processing system executes digital control processing in the condition that the first internal logic description of the field programmable gate array is rewritten to a second internal logic description. The image processing system executes again the digital image processing in the condition that the second internal logic description of the field programmable gate array is rewritten to the first internal logic description.

Cache prefetching algorithm uses previously requested address and data patterns to predict future data needs and prefetch such data from memory into cache. A requested address is compared to previously requested addresses and returned data to compute a set of increments, and the set of increments is added to the currently requested address and returned data to generate a set of prefetch candidates. Weight functions are used to prioritize prefetch candidates. The prefetching method requires no changes to application code or operation system (OS) and is transparent to the compiler and the processor. The prefetching method comprises a parallel algorithm well-suited to implementation on an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA), or to integration into a processor.

The invention discloses an ARM (advanced RISC (reduced instruction set computer) machines) and FPGA (field-programmable gate array) based navigation and autonomous flight control system for an unmanned helicopter. The system comprises a PC (personal computer), an integrated navigation subsystem, a power supply module and controllers, wherein the integrated navigation subsystem comprises a sensor group; the sensor group comprises a GPS (global positioning system), a gyroscope, an accelerometer, a magnetoresistive sensor, a barometric altimeter and a sonar altimeter; the controllers include a main controller and a steering engine controller; the main controller adopts an ARM microprocessor to operate the integrated navigation algorithm and flight control PID (proportion integration differentiation) algorithm and simultaneously completes data acquisition of the GPS, the barometric altimeter and the sonar altimeter; and the steering engine controller adopts an FPGA to realize data acquisition of the gyroscope, the accelerometer and the magnetoresistive sensor and transfers the data to the main controller via a concurrent bus to carry out attitude calculation and control operation on the unmanned helicopter. With the unmanned helicopter as a carrier, the hardware environment of a whole set of flight control system integrating study of the aircraft navigation and control theory problem, data acquisition, information transfer and embedded control is set up.

A method for measuring the range to multiple points on a surface by projecting a line of light onto the surface, imaging said line of light onto an XY photodetector array at an oblique angle, reading out the array one line at a time, computing the centroid of said line of light on each Y line across X columns as each line is read out of the array in onboard FPGA (Field Programmable Gate Array) or similar real time logic, computing quality factors for each computed centroid and encoding this as one or more bits in the centroid value, transmitting said tagged centroid to a local or remote data receiver, and computing the range to the surface for each point corresponding to each centroid using a previous calibration step.

A method for providing redundancy in a floating charge trap device based programmable logic device includes the steps of sensing for a predetermined amount of stored charge in a first area of a floating trap devices in a floating trap device pair, and sensing for the predetermined amount of stored charge in a second area of the floating trap devices in the floating trap device pair when the charge in the stored charge in the first area in one of the floating trap devices is below the predetermined amount.

A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.

A packaged microelectronic device having a first and second electrically interconnected microelectronic elements and a method for its manufacture. Conductive posts extend from one major surface of the first microelectronic element. The first microelectronic element is electrically interconnected to the second microelectronic element via the conductive posts. The first microelectronic element preferably has an interposer element from which the conductive posts extend. The second microelectronic element is interconnected to the interposer element via contacts on the second microelectronic element via the conductive posts. The so interconnected microelectronic elements have coordinated functionality, such as a programmable logic device wherein one microelectronic element is a field programmable gate array and the other microelectronic element is a memory device. The packaged microelectronic device is formed by using a transfer substrate to transfer solder masses onto at least some of the conductive posts extending from the first major surface of the first microelectronic element or contacts on the second microelectronic element. The solder masses are then used to electrically interconnect the conductive posts with the contacts disposed on the surface of the second microelectronic element.

The invention discloses a one-layer network data processing method suitable for an intelligent substation. The one-layer network data processing method suitable for the intelligent substation is characterized in that preprocessing of all kinds of network message in the intelligent substation is achieved with a field programmable gate array (FPGA) module adopting FPGA technology, a time-stamp is stamped on the FPGA module as soon as the message enters into an measurement and control (MAC) controller and is stored with the message, network storm restraint, storage and message analysis are available, EtherType domain is distinguished, packet and classified processing is conducted, and meanwhile priority control and real-time transmitting of the message are achieved. The one-layer network data processing method for the intelligent substation has the advantages that realization of intelligent devices in the intelligent substation is simplified, reliability is strengthened, systematic manufacturing cost is reduced and maintainability of the system is optimized.

A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data is provided. Particularly, a genomics analysis platform for executing a sequence analysis pipeline is provided. The genomics analysis platform includes one or more of a first integrated circuit, where each first integrated circuit forms a central processing unit (CPU) that is responsive to one or more software algorithms that are configured to instruct the CPU to perform a first set of genomic processing steps of the sequence analysis pipeline. Additionally, a second integrated circuit is also provided, where each second integrated circuit forming a field programmable gate array (FPGA), the FPGA being configured by firmware to arrange a set of hardwired digital logic circuits that are interconnected by a plurality of physical interconnects to perform a second set of genomic processing steps of the sequence analysis pipeline, the set of hardwired digital logic circuits of each FPGA being arranged as a set of processing engines to perform the second set of genomic processing steps. A shared memory is also provided.

The invention discloses a method for accelerating an LSTM neural network algorithm on an FPGA platform. The FPGA is a field-programmable gate array platform and comprises a general processor, a field-programmable gate array body and a storage module. The method comprises the following steps that an LSTM neural network is constructed by using a Tensorflow pair, and parameters of the neural networkare trained; the parameters of the LSTM network are compressed by adopting a compression means, and the problem that storage resources of the FPGA are insufficient is solved; according to the prediction process of the compressed LSTM network, a calculation part suitable for running on the field-programmable gate array platform is determined; according to the determined calculation part, a softwareand hardware collaborative calculation mode is determined; according to the calculation logic resource and bandwidth condition of the FPGA, the number and type of IP core firmware are determined, andacceleration is carried out on the field-programmable gate array platform by utilizing a hardware operation unit. A hardware processing unit for acceleration of the LSTM neural network can be quicklydesigned according to hardware resources, and the processing unit has the advantages of being high in performance and low in power consumption compared with the general processor.

A field programmable gate array (FPGA) and methods for executing operations using an FPGA are provided. The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be reconfigured. The method further includes executing a first operation associated with the user application using the first dynamic macro; reconfiguring the second macro to execute a second operation associated with the user application prior to completion of the first operation; and upon completion of the first operation, executing the second operation using the second dynamic macro.

The invention relates to a pipeline detection robot. The pipeline detection robot mainly comprises a laser detection mechanism (1), a traction mechanism (2), an electromagnetic ultrasonic detection mechanism (3) and an electronic cabin (4), all of which are connected through connecting hinge shafts; the traction mechanism (1) adopts a single-motor all-drive mode and is driven by a turbo-worm synchronous belt to supply a walking power to the robot; the laser detection mechanism (2) comprises a laser displacement sensor, a rotating arm, a counterweight, a support body and the like and is used for measuring surface corrosion and deformation of a pipeline; the electromagnetic ultrasonic detection mechanism (3) comprises a support assembly, a probe and a fixing plate and is used for measuring the wall thickness and the crack defect of the pipeline; the electronic cabin (4) is used for carrying auxiliary components, such as a stepping motor controller, a servo motor driver, a power supply and an FPGA (Field Programmable Gate Array) control panel. The pipeline detection robot disclosed by the invention can be used for finding the defects, such as pipeline corrosion, cracks and deformation, carrying out in-service detection on an oil and gas pipeline in a working process, carrying out targeted repair, maintenance and replacement according to a detection result, reducing the maintenance cost and guaranteeing safe and stable operation of the oil and gas pipeline.

The invention relates to a device and method for acquiring a digital image with high dynamic range in real time, which are used for synthesizing an image with high dynamic range in real time and outputting the image by directly utilizing an embedded image processing system. The device comprises an FPGA (Field Programmable Gate Array) programmable logic device, a CCD (Charge Coupled Device) imaging array, a video dedicated A/D chip, a coprocessor DSP (Digital Signal Processor) and a static random access memory (SRAM); and a system adopts two working modes of internal exposure and external exposure. In the working process, the FPGA is a central control and computation component, the DSP is the coprocessor, and image analysis and related parameter computation are realized. By means of the method disclosed by the invention, the image with high dynamic range can be generated in real time, the scene information of a bright region and a dark region is effectively expressed, the detailed characteristics of the image are enhanced, and the quality of the image shot by the CCD is improved.

A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA. A mechanical and electrical interface is for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard. After completion of a start-up cycle, the FPGA is configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.

A system for troubleshooting signals in a cellular communications network, and in particular, for determining the cause of distortion or corruption of such signals, includes a robotic or other type of switch. The robotic switch can tap into selected uplink fiber-optic lines and selected downlink fiber-optic lines between radio equipment and radio equipment controllers in a wireless (e.g., cellular) network to extract therefrom the I and Q data. The selected I and Q data, in an optical form, is provided to an optical-to-electrical converter forming part of the system. The system includes an FPGA (Field Programmable Gate Array) or the like, and an analytic computer unit, or web server, and SSD (Solid State Drive) and magnetic disk storage, among other components of the system. The system analyzes the I and Q data provided to it, and determines the cause, or at least narrows the field of possible causes, of impairment to transmitted signals. The system includes a display which provides the troubleshooting information thereon for a user of the system to review, or other form of a report, and may communicate the analytical findings to a remote location over a public or private internet protocol network.