489 results about "Field-programmable gate array" patented technology

The invention discloses an unmanned aerial vehicle radio communication frequency band countering method for automatic frequency identification and frequency writing, and relates to the technical field of unmanned aerial vehicle interference, and the method comprises a frequency band identification module which is used for scanning a 300MHz-6GHz frequency band in real time and identifying an enemy unmanned aerial vehicle communication signal; the signal analysis module is connected with the frequency band identification module, comprises a digital signal processor and an FPGA (Field Programmable Gate Array), and is used for analyzing signal modulation types and spectrum characteristics; the automatic frequency writing module is used for adjusting an interference frequency band through a direct digital frequency synthesis technology according to an analysis result; the multi-frequency-band interference transmitter supports synchronous interference in frequency bands of 1.2 GHz, 2.4 GHz, 5.2 GHz and 5.8 GHz; the intelligent control terminal integrates an adaptive interference algorithm, and the response time is less than or equal to 1 second. According to the unmanned aerial vehicle radio communication frequency band countering method capable of automatically identifying and writing the frequency, the radio communication frequency band used by the enemy unmanned aerial vehicle is automatically identified, and the corresponding frequency band is written in real time for accurate interference, so that the interference effect of an interference system facing the enemy unmanned aerial vehicle is improved.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

The invention discloses a control method and system of an automatic dispenser, and relates to the technical field of automatic control, and the control method comprises the following steps: collecting and preprocessing a dielectric loss factor and a temperature change rate of glue, calculating the dynamic viscosity, the shear temperature rise and the phase change rate of the glue through a time-frequency conjoint analysis method, and generating a phase change parameter matrix; inputting the phase change parameter matrix into a soliton kinetic model, obtaining a soliton waveform of the colloid under a nonlinear effect and a dissipation effect, optimizing the soliton waveform in combination with real-time viscosity, generating a pulse parameter and a dispersion compensation coefficient, and forming a soliton driving instruction set; loading the soliton driving instruction set to an FPGA (Field Programmable Gate Array) controller of the electric valve, generating a high-voltage pulse waveform, executing high-precision dispensing, monitoring a jet waveform and carrying out dynamic calibration; according to the method, the waveform is optimized through the soliton kinetic model and the step-by-step Fourier method, and accurate balance between the colloid dissipation effect and the nonlinear effect is achieved.

The invention discloses a high-speed camera data self-adaptive two-stage caching system and method and a storage medium, and relates to the technical field of machine vision high-speed imaging and high-speed data storage, a preprocessing unit is used for performing deserialization and parallel connection, ROI cutting and gain adjustment on collected item number data, and writing incremental FrameID and cyclic redundancy check codes into each frame; the DDR annular cache unit comprises a monitoring module, a decision module and an execution module; the decision module is used for calculating an instantaneous cache demand Cnew and a dynamic cache occupancy U; the execution module expands and shrinks an annular buffer space in a single shot through a DDR4 controller, and outputs a Hi / Lo mark in real time through an occupancy rate comparator to drive an NVMe queue manager. According to the invention, on the premise of zero extra burden in a normal working condition, millisecond-level automatic capacity expansion and high-speed flood discharge can be realized in a sudden working condition, and real-time frame-level integrity verification can be completed on a local FPGA (Field Programmable Gate Array) side. The patent is subsidized by national key research and development plans, and the project number is 2023YFF0719700.

The invention discloses a low-rank DCT (Discrete Cosine Transform) compressed sensing algorithm realized based on an FPGA (Field Programmable Gate Array), and relates to the technical field of image data processing, and the compressed sensing algorithm comprises the following specific steps: carrying out blocking processing on an input signal, dynamically adjusting the blocking granularity based on a calculation result of a signal local gradient entropy, and when the gradient entropy is higher than a set threshold value, adopting fine granularity blocking, when the frequency is lower than a threshold value, coarse granularity partitioning is adopted, the partitioning granularity is dynamically adjusted within a preset range, discrete cosine transform is conducted on the partitioned signals, the spectrum entropy of coefficients after transform is calculated, and the number of the reserved low-frequency coefficients is dynamically adjusted according to the magnitude of the spectrum entropy. According to the dynamic blocking strategy based on the gradient entropy, the compressed sensing algorithm can automatically adjust the blocking granularity according to the local features of signals, so that the compression ratio of a complex texture region and a smooth region is improved, the blocking boundary is dynamically judged through the gradient entropy, it is ensured that pixel affiliation of an edge region is more accurate, and the blocking effect is reduced; and complete structure information is reserved for subsequent reconstruction.

The invention belongs to the technical field of multi-camera cooperative imaging, and discloses a multi-camera cooperative anti-shake control system and method. The method comprises the following steps: generating a global hardware trigger signal by using an FPGA (Field Programmable Gate Array), synchronizing IMU and multi-camera acquisition, and combining motion parameters to obtain a space-time aligned multi-view image; obtaining a global jitter component through feature extraction, motion vector field generation, depth map analysis and the like; fusing the data with IMU data to generate a trajectory, and inputting the trajectory into LSTM to obtain future compensation amount; and cutting based on deep layered transformation to obtain an EIS optimized frame, dynamically electing a main camera for super-resolution reconstruction, and outputting a final anti-shake video stream. Through multi-source information fusion, layered precise compensation and dynamic optimization, the accuracy and stability of motion estimation are remarkably improved, the jitter influence of the finally output video stream is effectively weakened, and the reliability and visual coherence of the image stabilization effect in a complex scene are ensured.

The invention relates to the technical field of real-time kernel performance testing of special chips, in particular to a special chip real-time performance evaluation method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: (1) aiming at a real-time system on an ASIC (Application Specific Integrated Circuit) chip, setting an external interrupt source and an interrupt service program through a hardware interrupt controller; (2) two tasks with the same priority are created, scheduling of the tasks is achieved through time slice rotation, and a real dynamic load scene is simulated; (3) configuring an external FPGA (Field Programmable Gate Array) to generate a square wave signal to trigger external interruption of the ASIC chip, receiving a feedback signal, and connecting the FPGA and the GPIO through an external physical connecting line to form a hardware interruption triggering-response closed loop; and (4) realizing nanosecond timestamp capture through a counter built in the FPGA, acquiring time delay data, calculating interrupt response time, and transmitting the time delay data to a PC (Personal Computer) through a UART (Universal Asynchronous Receiver / Transmitter) to calculate a maximum value, a minimum value, an average value and a data jitter range of test data. The method can effectively solve the problem that the traditional internal closed-loop test cannot reflect the real interruption randomness and the dynamic load.

The invention provides a vehicle-mounted passive optical network area gateway and a protocol conversion method. The gateway comprises an interface module which comprises a plurality of communication interfaces, wherein the communication interfaces are used for receiving messages of a low-speed network protocol; the data processing module adopts an FPGA (Field Programmable Gate Array) core board and is used for receiving a message, extracting effective information from the message, packaging the effective information to obtain an Ethernet protocol frame and converting the Ethernet protocol frame into an SDU (Service Data Unit); and the ONU optical module is used for performing data link layer processing on the SDU to obtain an uplink FS burst frame, and performing physical layer processing on the uplink FS burst frame to obtain a burst mode optical signal frame. The gateway can realize data access of multiple paths of CAN nodes, LIN nodes and vehicle-mounted Ethernet nodes at the same time, meets the communication protocol conversion function of low-speed nodes in each region in a real vehicle environment, and is integrated into a whole vehicle all-optical backbone network. The method is used for converting data complying with a low-speed network protocol into data complying with an XGS-PON protocol.

The invention relates to the technical field of data processing, in particular to an FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) cooperative network data processing system, which comprises a network interface module for receiving and forwarding an external data flow, and a protocol analysis module for distinguishing a service message and a protocol message based on a message header characteristic and a load mode; the service processing module executes protocol format conversion, security encryption and data extraction in the FPGA; the protocol stack interaction module transmits a protocol message to the CPU through the MAC layer communication interface; the protocol stack module activates necessary protocol services in the CPU and generates a resource allocation instruction; and the data integration module receives the service data flow and the protocol processing result, and dynamically adjusts the encryption rule. According to the invention, FPGA business data closed-loop processing and CPU protocol service physical isolation are realized, a double-processing-unit architecture supports financial signature and industrial filtering cascade operation, the MAC layer interface is additionally provided with cyclic redundancy check to guarantee transmission reliability, and equipment processing efficiency and anti-attack capability under a fusion scene are improved.

The invention provides a dynamic high-precision PTP (Precision Time Protocol) time synchronization system realized based on an FPGA (Field Programmable Gate Array), which comprises a master device and a slave device, and the master device and the slave device are connected through a PHY (Physical Layer) to carry out PTP time synchronization; the master device and the slave device have the same structure and comprise an FPGA and a voltage-controlled crystal oscillator; in the master device, the FPGA obtains the frequency difference and the phase difference between the master device and an externally input reference source, further adjusts the frequency of a voltage-controlled crystal oscillator, corrects a local time mark, and sends a PTP message to the slave device; and in the slave equipment, the FPGA obtains the frequency difference and the phase difference between the slave equipment and the master equipment based on the received PTP message, so that the frequency of the voltage-controlled crystal oscillator is adjusted, and the local time scale is corrected. According to the invention, low-cost and high-precision PTP time synchronization is realized.

The invention discloses a low-resource and low-energy-consumption remote sensing image brain-like computing system based on an FPGA (Field Programmable Gate Array), which belongs to the cross technical field of brain-like computing and remote sensing information processing, and comprises a data interaction module which is used for high-speed data transmission between a PC (Personal Computer) end and the FPGA and comprises a PCIe (Peripheral Component Interconnect Express) interface sub-module and a data transmission control sub-module; the storage control module is used for data interaction control of the off-chip DDR and the on-chip BRAM and providing efficient data supply for the processing engine; the processing engine module is used for simulating a brain-like pulse neural network to complete convolution calculation of the remote sensing image; comprising a convolution processing sub-module, a data storage sub-module, an input buffer sub-module and an output buffer sub-module. According to the low-resource and low-energy-consumption remote sensing image brain-like computing system based on the FPGA, the brain-like pulse neural network is adopted, the BRAM is allocated to store the intermediate computing result, and the computing unit is designed in combination with SNN characteristics, so that energy consumption and resource waste are effectively reduced, and computing efficiency is improved.

The invention provides a method for rapidly determining the center position of an electron cloud cluster of a reading circuit in an XS anode detector, and aims to solve the problems that the existing method for calculating the center position of the electron cloud cluster of the reading circuit in the XS anode detector cannot realize higher spatial resolution, or easily causes image distortion, and is inconvenient to use. The software processing speed is slow, the FPGA is not easy to implement, or the calculation error at the edge strip is relatively large. The method for rapidly determining the center position of the electronic cloud cluster of the reading circuit in the XS anode detector is realized by adopting an FPGA (Field Programmable Gate Array), the peak value of effective data of each channel is obtained through single-channel processing, and then a corresponding drop point distribution index code is generated through table look-up and cross-channel processing; and then adaptive weight selection is carried out according to the drop point distribution index code, so that the weight accuracy of weighted average operation is ensured, key support is provided for rapid and accurate calculation of the center position of the electronic cloud cluster, and high efficiency and accuracy of the whole data processing flow are ensured.

The invention discloses an FPGA (Field Programmable Gate Array) and an interference suppression method based on the FPGA. The FPGA comprises an eigenvalue decomposition IP (Intellectual Property) core, an interference range expansion module, a matrix inversion IP core and an interference suppression module. According to the interference range expansion module, the virtual interference source is arranged near the real interference source, the null width of a received signal can be expanded, angle diffusion interference in a wide range can be covered, interference energy leakage is suppressed, and the interference suppression effect is enhanced; by customizing two IP cores (an eigenvalue decomposition IP core and a matrix inversion IP core) realized based on HLS and performing eigenvalue decomposition and matrix inversion operation based on the two IP cores, the phenomenon of iteration delay in an FPGA of a traditional structure can be slowed down, the operation speed of the FPGA is improved, and the real-time performance of interference suppression is enhanced.

The invention relates to a full-unloading regular matching system and method based on an FPGA (Field Programmable Gate Array). The system comprises a regular rule compiling unit and an FPGA full matching unit, the regular rule compiling unit is used for receiving a regular rule set, extracting each rule fixed feature substring, compiling the uniform format isomorphic NFA, and constructing a mapping relation table of the substrings and the corresponding NFA; the FPGA full matching unit comprises a parallel high-speed character string matching engine array, a character string-NFA mapping table module, a full-quantity regular data memory, a reconfigurable general NFA engine module and a matching result output module; and the reconfiguration engine module is used for executing full unloading regular matching on the input network traffic: scanning the traffic through the engine array, screening to-be-verified traffic containing a fixed feature substring and outputting a substring identifier, querying the NFA identifier through the mapping table module, and loading NFA matching by the reconfiguration engine module. By adopting the method, low delay and high throughput performance of regular matching in a high-speed network environment can be ensured.

The invention discloses a business travel user real-time feedback and suggestion system, which relates to the technical field of mobile application development and multi-terminal adaptation, and is characterized in that an edge layer guarantees the completeness of offline scene data through a dynamic load adapter, starting a structured compression protocol in a weak network, switching a multi-mode enhancement protocol in a strong network and matching with a priority cache queue; the decision-making layer adopts a parallel processing unit accelerated by an FPGA (Field Programmable Gate Array), and a real-time stream filtering unit adopts SimHash fingerprints to remove duplication; the scene understanding unit fuses the spatio-temporal data to generate event tags; the grading response unit automatically triggers AI compensation and manual work orders according to risk grades; and the collaboration layer verifies the responsible party of the travel system on the premise of hiding the user ID based on the zero-knowledge proof gateway so as to realize cross-platform secure data exchange. According to the system, a three-layer intelligent architecture is innovatively constructed, and full-link real-time response of travel service is realized.

The invention discloses a multi-task parallel data stream processing method and device based on an FPGA (Field Programmable Gate Array), which are applied to the technical field of data processing. Carrying out normalization processing on the decoded data to generate a data stream in a unified format; performing coding and ID identification code embedding processing on the normalized data to generate to-be-stored data with an identifier; carrying out FIFO (First In First Out) buffering and write-in priority judgment on the coded data to generate priority queue data; dDR writing and BANK scheduling processing are carried out on the priority queue data, and stably stored parallel data are generated; carrying out reading and output coordination processing on DDR storage data to generate a continuous output data stream, and triggering a reading application by decoding ID identification code positioning data, reading FIFO according to depth scheduling and monitoring data volume by channel temporary storage FIFO; and performing dynamic bandwidth allocation and energy efficiency optimization on the whole data stream processing process to generate an efficient parallel processing result.

The invention discloses an ISAR (Inverse Synthetic Aperture Radar) multi-pulse accumulation cross-correlation distance and phase correction system based on an FPGA (Field Programmable Gate Array). The ISAR multi-pulse accumulation cross-correlation distance and phase correction system comprises an upper computer and the FPGA, the upper computer is used for controlling the inverse synthetic aperture radar system to transmit a signal and receiving an echo signal; performing de-line frequency modulation on the echo signal to obtain an echo signal after pulse compression, and preprocessing the echo signal to obtain a to-be-processed echo signal; quantizing the echo signal to be processed, acquiring a quantized echo signal, transmitting the quantized echo signal to the FPGA, and receiving the distance returned by the FPGA and the echo signal after phase correction; and the FPGA is used for executing a multi-pulse cumulative cross-correlation envelope alignment algorithm to perform alignment processing on the quantized echo signal, obtaining a corrected echo signal and returning the corrected echo signal. The register transfer stage circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm is designed based on the FPGA, high-parallelization acceleration based on the multi-pulse cumulative cross-correlation envelope alignment algorithm module is achieved, and the processing speed and efficiency of the algorithm are remarkably improved.

The invention provides a method for testing the communication bandwidth of a 10-gigabit network between an FPGA (Field Programmable Gate Array) and a CPU (Central Processing Unit), which is applied to a radar system. The FPGA completes a function of regularly generating data and a function of downlink transmission of the data; the 10-gigabit network exchange board card completes data transmission and sends data to the CPU board card through a 10-gigabit network; and the CPU board card receives the data and calculates the communication bandwidth and the network quality. According to the invention, the limitation of traditional single-port point-to-point transmission or simple multi-port parallel transmission on synchronization, load balancing or protocol overhead is solved, and a solution is provided for how to effectively utilize multiple ports, enable the multiple ports to simultaneously and efficiently work and ensure parallel transmission of data without mutual interference.

The invention discloses a data transmission method and device, an industrial control system, a storage medium and a computer program product, and the method comprises the steps: initializing a continuous physical memory, dividing the continuous physical memory into memory blocks with a fixed size, recording the initial address, size, idle or occupied state of the memory blocks through a red-black tree, and forming a dynamic address pool; the dynamic address pool can realize on-demand allocation of memory blocks and merging and dynamic expansion of adjacent free blocks; the method comprises the following steps: acquiring a load index in real time through an FPGA (Field Programmable Gate Array), triggering interruption based on load grading and predicting a memory demand in combination with a machine learning model, and pre-fetching a memory block from a dynamic address pool to a user mode mapping region before a real-time task initiates a memory allocation request; a user mode atomic operation annular queue is designed, direct data interaction between the X86 and the FPGA is achieved through memory mapping, and a Burst transmission and cache consistency protocol of a hardware bus is combined. According to the scheme, the problem of memory fragmentation is solved, the data transmission delay is reduced, and the CPU occupancy rate is greatly reduced.

The invention discloses a lining pipeline interface contact pressure distribution testing device and method, relates to the technical field of pipeline detection, and aims at solving the problem that in the prior art, interface contact pressure distribution is difficult to represent in a lossless and quantitative mode. The device comprises a testing machine moving platform, an overground control moving platform, a lining pipe wall testing claw, an ultrasonic signal transceiver and a three-dimensional imaging module, the testing claw carries four curved-surface ultrasonic probes, and signals are collected in a one-transmitting-multiple-receiving mode controlled by an FPGA (Field Programmable Gate Array); according to the method, a contact pressure characterization model is constructed through self-adaptive positioning and signal excitation and processing, and interface pressure distribution visualization is achieved in combination with a three-dimensional imaging technology. The method does not need to damage the pipeline structure, can accurately capture the spatial distribution characteristics of the contact pressure, is adaptive to the conventional detection of long-distance pipelines, provides a scientific basis for lining repair quality evaluation and pipeline operation safety, and is convenient to operate and high in applicability.

The invention relates to a satellite-borne super-large-scale digital phased array system based on a JESD204B clock synchronization network, and the system comprises a radio frequency antenna layer which is used for receiving and transmitting electromagnetic waves in a space, and completing the mutual conversion of a radio frequency signal and a space electromagnetic wave; the sub-array baseband layer is used for realizing S-band 64-path intermediate frequency signal sampling, transmitting and digital domain multi-beam synthesis in a transceiving link, realizing data transmission with the mother board clock layer, and completing a reconstruction function of a baseband module signal processing FPGA (Field Programmable Gate Array) through a low-speed interface; the mother board clock layer serves as a function of realizing data summarization and distribution and performs task scheduling and management on the whole digital phased array system, and a JESD204B clock tree network is designed in the board and is distributed to a synchronous clock of each baseband module so as to indicate a target signal to complete synchronous sampling and emission output. By adopting the system, access, efficient tracking and accurate pointing of massive ground users can be realized.

The invention relates to the technical field of digital signal processing, and particularly discloses a mixed precision low-resource digital control oscillator implementation method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: dividing a 32-bit phase accumulator into a high-bit 24-bit dominant frequency control section and a low-bit 8-bit dynamic compensation section, and carrying out the phase accumulation in parallel through double carry chains, the high-order section receives high 24 bits of a frequency tuning word FTW to control a dominant frequency, and the low-order section receives low 8 bits of the FTW and overlaps an overflow remainder to dynamically compensate for a phase error. According to the implementation method of the mixed precision low-resource digital control oscillator based on the FPGA disclosed by the embodiment of the invention, through collaborative innovation of mixed precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, the core problems of a traditional NCO in resource occupation, phase continuity, waveform precision and time sequence performance are systematically solved.

The invention belongs to the technical field of distributed optical fiber sensing (DAS) system signals, and discloses a time axis phase unwrapping method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps of phase data acquisition, stable group formation, phase progressive unwrapping, assembly line and cache cooperative processing and quality measurement closed-loop correction. According to the system, real-time phase extraction of interference signals is achieved through the FPGA demodulation unit, phase change is dynamically unwrapped through the reliable period screening unit and the phase progressive unwrapping unit, a self-adaptive unwrapping mechanism is formed in combination with anomaly judgment and threshold updating logic, and through collaborative design of an annular cache and a three-level assembly line comparator, the interference signal is obtained. According to the method, parallel transmission and time sequence synchronization of data are achieved, the precision and stability of phase unwrapping can be effectively improved in a complex noise environment, hardware delay and resource occupation are remarkably reduced, and the method is suitable for real-time signal unwrapping processing of a high-precision distributed optical fiber sensing system.

The embodiment of the invention relates to the technical field of remote sensing, in particular to an unmanned aerial vehicle-mounted hyperspectral acquisition system and method based on an FPGA (Field Programmable Gate Array). The system comprises an FPGA (Field Programmable Gate Array) processing module carried by an unmanned aerial vehicle, a hyperspectral camera module, a visible light camera module, an inertia measurement module, a zenith light module and a power supply module, a trigger signal is provided for a hyperspectral camera module, a visible light camera module, an inertia measurement module and a zenith light module according to the second pulse signal, an acquisition period is generated according to the trigger signal, and in the acquisition period, the FPGA processing module executes the following steps: opening up a temporary storage area; receiving hyperspectral image data, visible light image data, flight attitude data and zenith light data; aligning and caching according to a time axis; calculating the reflectivity, and carrying out geometric correction; and generating a data packet, persistently storing the data packet and returning the data packet to the ground control center.

The invention provides a programmable frequency control array radar waveform generation system and method based on an FPGA, and belongs to the technical field of radar systems and digital signal processing. In order to solve the technical problems of complex hardware system, inflexible parameter adjustment and poor multi-channel synchronism of the traditional frequency control array radar, the invention provides an integrated high-performance solution. The system adopts an FPGA (Field Programmable Gate Array) architecture of an integrated processing system (PS) and programmable logic (PL). The method comprises the following steps: a PS end receives waveform control parameters of an upper computer through a communication interface and transmits the waveform control parameters to a PL end; and a plurality of parallel direct digital frequency synthesizer (DDS) modules in the PL end synchronously generate multi-channel digital baseband signals with programmable frequency offset at high precision according to the parameters under the unified driving of the FPGA global clock network. And the digital signal is subjected to digital-to-analog conversion and radio frequency front-end processing to finally form a transmitting wave beam. According to the invention, flexible programmability of parameters is realized by utilizing a PS-PL collaborative architecture, the synchronization precision of multi-channel signals is remarkably improved through a global clock network and a parallel DDS module generated in the FPGA, and meanwhile, the system has the advantages of high integration level and low complexity.

The invention relates to a motor filtering speed measurement method based on an FPGA, and belongs to the technical field of motor speed measurement. The filtering speed measurement method comprises the following steps: detecting rotation of a motor through a Hall encoder and outputting a pulse signal, outputting the pulse signal to a digital quantity input interface of an FPGA (Field Programmable Gate Array), and realizing a filtering speed measurement algorithm in the FPGA in a hardware form; and performing data operation processing on the pulse signal by using an FPGA based on a filtering speed measurement algorithm to realize measurement of the rotating speed of the motor. Compared with a speed measurement method in the prior art, the method has the advantages that the FPGA is combined with a filtering speed measurement algorithm, so that the rotation speed of the motor can be measured, the problem of low speed measurement precision of the motor in an unstable state can be effectively solved, the anti-interference capability of motor speed measurement can be improved, and the response speed of a speed measurement system can be increased.

The invention discloses a gas leakage detection imaging device and method based on a single photon detection technology, and belongs to the technical field of gas detection and imaging. Aiming at the limitation problems of the existing gas leakage detection technology in the aspects of sensitivity, response speed, space imaging capability and anti-interference capability, nanosecond modulation control and synchronous photon counting are realized by utilizing an FPGA (Field Programmable Gate Array) through a visual gas detection imaging device combining an SPAD (Single Program Amplifier) array detector and a WMS modulation-demodulation mechanism; and the second harmonic of the absorption signal is further extracted by combining digital phase-locked amplification, so that gas leakage three-dimensional imaging with high spatial resolution, ppb-level sensitivity, strong background suppression capability and high time response is realized. The system has the advantages of high detection sensitivity, real-time imaging capability with high spatial resolution, high background light interference resistance and high signal-to-noise ratio, the demodulation method is novel, and the modular design has multi-gas compatibility and system expansibility.

The invention relates to the technical field of power system monitoring and protection, and discloses an FPGA (Field Programmable Gate Array)-based strong current system real-time monitoring fault intelligent processing system, which comprises a pulse coding module used for converting a monitored voltage or current signal into a time domain pulse sequence; the hardware pulse neural network module is used for processing the pulse sequence to generate a local early warning state vector; the distributed consensus engine module is used for generating a global early warning state vector through consensus in combination with the local vectors of the plurality of nodes; the parameter adaptive adjustment module is used for adjusting the response characteristics of the neural network according to the global vector feedback; and the collaborative decision-making and intelligent control module is used for executing a collaborative strategy to process potential faults when the global early warning reaches a threshold value. According to the invention, weak fault precursor can be detected with extremely low delay and high sensitivity, and the global reliability and intelligent processing capability for coping with systematic risks are improved through distributed cooperation.

The invention discloses an FPGA-based sound wave multiple reflection sediment concentration measurement method. The method comprises the following steps: constructing an ultrasonic underwater measurement system capable of realizing ultrasonic multiple reflection and driving the ultrasonic underwater measurement system to work; an ultrasonic transducer is driven by the FPGA to emit ultrasonic waves; echo signals of the ultrasonic waves passing through the turbid liquid are collected, subjected to analog-to-digital conversion and then transmitted to the FPGA; digital filtering and peak detection are carried out on the echo data based on the FPGA; according to a peak value detection result, an ultrasonic attenuation coefficient is calculated based on the FPGA in combination with numerical integration; for a plurality of turbid liquid bodies of the same type with known sediment concentrations, the second step to the fifth step are executed respectively, ultrasonic attenuation coefficients under different concentrations are obtained, and then fitting is conducted on the ultrasonic attenuation coefficients and the concentrations to obtain a regression equation of the attenuation coefficients and the sediment concentrations; and executing the second step to the sixth step to obtain an ultrasonic attenuation coefficient aiming at a to-be-detected turbid liquid body, and substituting the ultrasonic attenuation coefficient into the regression equation to obtain the sediment concentration of the to-be-detected turbid liquid body. According to the method, the defects of the traditional method in real-time performance and precision are overcome, and the real-time performance and accuracy of sediment concentration measurement are remarkably improved.

The invention discloses a 2-FSK (Frequency Shift Keying) signal frequency amplitude detection method based on an FPGA (Field Programmable Gate Array), which relates to the field of communication systems and comprises the steps of signal acquisition, frequency analysis, amplitude spectrum conversion and amplitude estimation, frequency estimation, data output, signal preprocessing and frequency detection result calibration. In the acquisition step, signals are acquired by an eight-channel synchronous or sequential sampling technology; in the analysis step, frequencies are analyzed by a different-point FFT algorithm; in the conversion step, amplitude spectrums are obtained by processing spectrum conversion; in the estimation step, frequencies are calculated, verification and correction are carried out by a phase difference method; in the preprocessing step, a hardware filter is used to preprocess a signal, and in the calibration step, a detection result is calibrated and optimized according to a calibration formula. The method is high in detection precision, strong in real-time performance, high in detection speed, good in adaptability, low in cost, small in power consumption, beneficial to system integration and miniaturization and wide in application prospect in the field of communication and the like.