5341 results about "Field-programmable gate array" patented technology

A state machine gesture recognition algorithm for interpreting streams of coordinates received from a touch sensor. The gesture recognition code can be written in a high level language such as C and then compiled and embedded in a microcontroller chip, or CPU chip as desired. The gesture recognition code can be loaded into the same chip that interprets the touch signals from the touch sensor and generates the time series data, e.g. a microcontroller, or other programmable logic device such as a field programmable gate array.

An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).

The Field Programmable Instrument Controller (FPIC) is a stand-alone low to high performance, clocked or unclocked multi-processor that operates as a microcontroller with versatile interface and operating options. The FPIC can also be used as a concurrent processor for a microcontroller or other processor. A tightly coupled Multiple Chip Module design incorporates non-volatile memories, a large field programmable gate array (FPGA), field programmable high precision analog to digital converters, field programmable digital to analog signal generators, and multiple ports of external mass data storage and control processors. The FPIC has an inherently open architecture with in-situ reprogrammability and state preservation capability for discontinuous operations. It is designed to operate in multiple roles, including but not limited to, a high speed parallel digital signal processing; co-processor for precision control feedback during analog or hybrid computing; high speed monitoring for condition based maintenance; and distributed real time process control. The FPIC is characterized by low power with small size and weight.

The invention discloses a continuous Doppler US imaging system orthogonal intrinsic signal generation device, which comprise a field programmable gate array (FPGA), a crystal oscillator, a first digital-analog converter and a second digital-analog converter. The output end of the field programmable gate array (FPGA) is connected with the input ends of the first digital-analog converter and the second digital-analog converter; the crystal oscillator is respectively connected with the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the crystal oscillator is used for supplying synchronizing clock signals to the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the field programmable gate array (FPGA) is used for outputting the sine value corresponding to the phase value to the first digital-analog converter according to the input phase value and outputting the cosine value corresponding to the phase value to the second digital-analog converter; the first digital-analog converter is used for converting the sine value into the corresponding analog signals; the second digital-analog converter is used for converting the cosine value into the corresponding analog signals.

A network tap for enabling attached devices, such as an intrusion detection system, to transmit information into a communication line of the network without disrupting the network traffic on the communication line. When the attached device is an intrusion detection device, the network tap is connected to a firewall. An Ethernet switch or field programmable gate array (FPGA) is incorporated in the network tap to coordinate the transmission of device data to avoid data collisions with data transmissions already existing in the communication line. The network tap may be operated in various modes to accommodate different capabilities of attached devices. In addition, the network tap has various port configurations to allow a user to connect various attached devices through a single cable or dual cables and to connect various combinations of attached devices.

A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises the steps of providing a serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of the configuration SRAM and the user assignable SRAM by the row and column counters; performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T₀ trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.

A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

An FPGA is readily connectable to a high-speed fiber optic link by snap fitting an external fiber optic cable into an accommodating duplex fiber optic connector of a low-profile packaged FPGA integrated circuit. The low-profile packaged FPGA integrated circuit includes a die-bonded assembly disposed within a co-fired multilayer ceramic integrated circuit package. The die-bonded assembly includes the optoelectronic die, the bottom surface of which is die-bonded and electrically interconnected by micropads to the upper surface of the core of an FPGA integrated circuit die. A first optical fiber communicates light from the connector, through the package, and to a photodetector on the optoelectronic die. A second optical fiber communicates light from a laser diode on the optoelectronic die, through the package, and to the connector. In some embodiments, a micromirror device is disposed within the package to redirect light between the optoelectronic die and the optical fibers.

An adaptive gate drive for an inverter includes control circuitry having a Field Programmable Gate Array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a Trench Gate Insulated Gate Bipolar Transistor (IGBT device). The control circuitry provides switching signals for operating the switching device. In addition, the control circuitry receives signals of output current of the IGBT device, temperature of the IGBT device, and DC link voltage. The FPGA has a plurality of operating points stored therein. Each operating point has corresponding parameters for a control signal that is used to control the turn-on or turn-off behavior of the IGBT device. During operation, the control circuitry compares the measured current, voltage and temperature operating points stored in the FPGA and sends the corresponding parameters to the gate drive circuit. The gate drive modifies the signal on the gate of the IGBT accordingly and thereby optimizes the turn-on and/or turn-off behavior of the device based on actual operating conditions.

The invention discloses an extensible multichannel parallel real-time data acquisition device and method. The device comprises a PXIe (PCI (Peripheral Component Interconnect) Extensions for Instrumentation Express) backboard, a CPU (Central Processing Unit) board card and a plurality of FPGA (Field-Programmable Gate Array) acquisition cards; the PXIe backboard comprises a CPU motherboard slot, a clock board slot, a plurality of FPGA board card slots and a PCIe (Peripheral Component Interface Express)/PCI switching bridge; the data transmission between the CPU board card and the FPGA acquisition cards is achieved by PCIe switches, and the P2P (Peer-to-Peer) data transmission is carried out among the FPGA acquisition cards; a clock module provides a system differential clock, differential synchronization signals and differential star-shaped triggers through a clock bus and is downwardly compatible with a PXI clock; and the FPGA board card slots realize the compatibility between a PXI and a Compact PCIe board card through a PCI bus and the PCIe/PCI switching bridge. The invention further provides the method based on the device. The device and the method have the advantages of high sampling rate, fast data transmission and easiness for the large-scale extension of a plurality of board cards.

A user-configurable and/or self-configurable System on a Chip (SoC) device and corresponding remote programming method enabling the SoC to be reprogrammed multiple times from a remote chip file server. Once programmed with the desired SoC design, the device can be debugged remotely in real-time by one or more users. The device includes a helper microcontroller/programmer, and a Field Programmable Gate Array (FPGA) fabric which is divided into a plurality of programmable logic and clock driver domains that may be independently programmed by way of the helper microcontroller. Once programmed, the helper microcontroller can serve as a real-time monitor/data exchange sub-controller and/or may be used by the end application.

The invention discloses a system for updating an FPGA (Field Programmable Gate Array) configuration program from a long distance based on the control of a processor and a method for updating the FPGA configuration program from a long distance based on the control of the processor. The system comprises a processor module, an FPGA module, an SPI (Serial Peripheral Interface) memory module and a buffer module, wherein the processor module is connected with the SPI memory module and is connected with a communication interface, the SPI memory module is connected with the FPGA module, and the processor module is connected with the SPI memory module by the buffer module. When the configuration program of an FPGA requires to be updated, an upper computer or a terminal downloads the FPGA configuration program into the SPI memory module through the communication interface and the processor module, and the FPGA module can automatically load the configuration program memorized in the SPI memory module in a MasterSPI mode. According to the system and the method, the FPGA configuration program is updated from a long distance, the function of updating the configuration program on line under the non-outage situation is realized, and therefore, the system and the method are particularly suitable for on-site application.

The invention provides a test system and method for a single event effect of an SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array). The test system comprises a single chip microcomputer processor, an RS232 interface circuit, a USB (Universal Serial Bus) interface circuit, a test FPGA and a storage unit. The test system and method can be used for fault injection tests of a configuration memory and a BRAM (Battery Random Access Memory) of the SRAM type FPGA, and single event function interrupting detection, single event locking detection and single event turning detection including single event turning detection for a configuration storage region, the BRAM and a trigger of the SRAM type FPGA are realized. The invention has the advantages of simplicity in operation, entirety in detection, high accuracy, good real-time property and strong universality.

An image processing system whose circuit size is small, and whose dissipation power is small is provided. The image processing system executes digital image processing of an interval of active pixel in the condition that a first internal logic description is written in a field programmable gate array. Subsequently, in interval of non-active pixel with the exception of the interval of active pixel, the image processing system executes digital control processing in the condition that the first internal logic description of the field programmable gate array is rewritten to a second internal logic description. The image processing system executes again the digital image processing in the condition that the second internal logic description of the field programmable gate array is rewritten to the first internal logic description.