821 results about "Field-programmable gate array" patented technology

The invention provides a data packet analyzer and method based on an FPGA (Field Programmable Gate Array). The analyzer comprises a first-stage configurable packet analysis module and a secondary configurable packet analysis module which are connected in sequence, wherein the first-stage configurable packet analysis module is used for extracting a protocol field at the bottommost layer of a message, and outputting a matching field, a header, a packet header vector and an initial offset to the second-stage configurable packet analysis module; the plurality of secondary configurable packet analysis modules are connected in sequence; and the secondary configurable packet analysis module is used for analyzing the message according to the analysis action configured by the dynamic configuration message. The method has the advantages that processing requirements of different protocols can be met, the bit width of an interface between extraction units is reduced, and resource consumption is reduced; the matching rule and the field set of each stage are allowed to be flexibly adjusted according to requirements; free combination of a plurality of parallel protocol field extraction units is supported, and the analysis performance is greatly improved; different message analysis requirements can be met, and higher customization and adaptability are provided.

The invention discloses an unmanned aerial vehicle radio communication frequency band countering method for automatic frequency identification and frequency writing, and relates to the technical field of unmanned aerial vehicle interference, and the method comprises a frequency band identification module which is used for scanning a 300MHz-6GHz frequency band in real time and identifying an enemy unmanned aerial vehicle communication signal; the signal analysis module is connected with the frequency band identification module, comprises a digital signal processor and an FPGA (Field Programmable Gate Array), and is used for analyzing signal modulation types and spectrum characteristics; the automatic frequency writing module is used for adjusting an interference frequency band through a direct digital frequency synthesis technology according to an analysis result; the multi-frequency-band interference transmitter supports synchronous interference in frequency bands of 1.2 GHz, 2.4 GHz, 5.2 GHz and 5.8 GHz; the intelligent control terminal integrates an adaptive interference algorithm, and the response time is less than or equal to 1 second. According to the unmanned aerial vehicle radio communication frequency band countering method capable of automatically identifying and writing the frequency, the radio communication frequency band used by the enemy unmanned aerial vehicle is automatically identified, and the corresponding frequency band is written in real time for accurate interference, so that the interference effect of an interference system facing the enemy unmanned aerial vehicle is improved.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

The invention relates to the technical field of signal encryption, in particular to an aviation data bus signal encryption method and system based on a field programmable gate array (FPGA), which comprises the following steps of: based on input three-dimensional tensor signal data, extracting slices from a time index of an aviation data bus according to a fixed interval, progressively sequencing amplitudes of signal channels, and then segmenting; according to the method, through processing logic of matrix decomposition and feature curve generation, the feature extraction and dimension reduction process is optimized, the distinction degree and the expression capacity of feature information are improved, the randomness and the anti-cracking capacity of a key are enhanced through a key generation mode combining a dynamic disturbance factor and an encryption parameter, and the safety of signal transmission is guaranteed; through combination of amplitude superposition and frame-by-frame storage, dynamism and high efficiency of a signal encryption process are realized, signal tampering and eavesdropping risks are reduced, and through feature reconstruction and point-by-point matching processing in a decryption stage, accurate restoration of signal amplitude is ensured, and data integrity and anti-interference capability are guaranteed.

The invention discloses a control method and system of an automatic dispenser, and relates to the technical field of automatic control, and the control method comprises the following steps: collecting and preprocessing a dielectric loss factor and a temperature change rate of glue, calculating the dynamic viscosity, the shear temperature rise and the phase change rate of the glue through a time-frequency conjoint analysis method, and generating a phase change parameter matrix; inputting the phase change parameter matrix into a soliton kinetic model, obtaining a soliton waveform of the colloid under a nonlinear effect and a dissipation effect, optimizing the soliton waveform in combination with real-time viscosity, generating a pulse parameter and a dispersion compensation coefficient, and forming a soliton driving instruction set; loading the soliton driving instruction set to an FPGA (Field Programmable Gate Array) controller of the electric valve, generating a high-voltage pulse waveform, executing high-precision dispensing, monitoring a jet waveform and carrying out dynamic calibration; according to the method, the waveform is optimized through the soliton kinetic model and the step-by-step Fourier method, and accurate balance between the colloid dissipation effect and the nonlinear effect is achieved.

The invention discloses a high-speed camera data self-adaptive two-stage caching system and method and a storage medium, and relates to the technical field of machine vision high-speed imaging and high-speed data storage, a preprocessing unit is used for performing deserialization and parallel connection, ROI cutting and gain adjustment on collected item number data, and writing incremental FrameID and cyclic redundancy check codes into each frame; the DDR annular cache unit comprises a monitoring module, a decision module and an execution module; the decision module is used for calculating an instantaneous cache demand Cnew and a dynamic cache occupancy U; the execution module expands and shrinks an annular buffer space in a single shot through a DDR4 controller, and outputs a Hi / Lo mark in real time through an occupancy rate comparator to drive an NVMe queue manager. According to the invention, on the premise of zero extra burden in a normal working condition, millisecond-level automatic capacity expansion and high-speed flood discharge can be realized in a sudden working condition, and real-time frame-level integrity verification can be completed on a local FPGA (Field Programmable Gate Array) side. The patent is subsidized by national key research and development plans, and the project number is 2023YFF0719700.

The invention discloses a circuit for simultaneously switching transimpedances of multiple channels by adopting a shift register. The circuit is characterized in that an FPGA (Field Programmable Gate Array) is connected with a signal acquisition and conversion circuit module through an analog-to-digital converter and a clock generation and distribution module; the signal acquisition and conversion circuit module comprises a bias voltage setting module, a pi-type filter, a photoelectric sensor and a transimpedance amplification module which are connected in series; the input end of a transimpedance amplifier in the transimpedance amplification module is connected with a transimpedance gain access circuit, the transimpedance gain access circuit is connected with the output end of the transimpedance amplifier through an analog switch, and the control end of the analog switch is connected with the FPGA through a shifting register. According to the circuit and the method for simultaneously switching the transimpedances of the multiple channels by adopting the shift register, the transimpedance gain of the transimpedance amplifier is judged and switched according to the size of the signal, the range of the input signal is expanded, the resolution is improved, and the IO resources of the FPGA are saved and the cost is reduced by utilizing the storage function and the serial-parallel conversion function of the shift register.

The invention discloses a low-rank DCT (Discrete Cosine Transform) compressed sensing algorithm realized based on an FPGA (Field Programmable Gate Array), and relates to the technical field of image data processing, and the compressed sensing algorithm comprises the following specific steps: carrying out blocking processing on an input signal, dynamically adjusting the blocking granularity based on a calculation result of a signal local gradient entropy, and when the gradient entropy is higher than a set threshold value, adopting fine granularity blocking, when the frequency is lower than a threshold value, coarse granularity partitioning is adopted, the partitioning granularity is dynamically adjusted within a preset range, discrete cosine transform is conducted on the partitioned signals, the spectrum entropy of coefficients after transform is calculated, and the number of the reserved low-frequency coefficients is dynamically adjusted according to the magnitude of the spectrum entropy. According to the dynamic blocking strategy based on the gradient entropy, the compressed sensing algorithm can automatically adjust the blocking granularity according to the local features of signals, so that the compression ratio of a complex texture region and a smooth region is improved, the blocking boundary is dynamically judged through the gradient entropy, it is ensured that pixel affiliation of an edge region is more accurate, and the blocking effect is reduced; and complete structure information is reserved for subsequent reconstruction.

The invention relates to a flexible multi-channel multi-mode sensor data acquisition system. The system comprises a signal collector for collecting multi-channel signals, a pin header interface for providing multi-channel signal access, a plurality of analog switches for realizing switching and collection of the multi-channel signals and improving the flexibility and expandability of signal collection, a sensor part meeting multi-dimensional data collection requirements, and an analog-to-digital conversion chip, the control unit adopts an FPGA (Field Programmable Gate Array) to control switching of an analog switch and time sequence management, and the wireless transmission module is provided with a Wi-Fi chip; one end of the pin header interface is connected with the signal collector and the other end is connected with the analog switch; the sensor part is connected to the analog-to-digital conversion chip; the analog switch, the analog-to-digital conversion chip and the wireless transmission module are all connected to the controller. The system is a modularized multi-sensor data acquisition system with high precision and high bandwidth, and can realize dynamic sampling, efficient processing and wireless transmission of multi-sensor signals in a limited size.

According to the large-scale real-time data link layer simulation method, a data link layer simulation system based on an FPGA (Field Programmable Gate Array) is composed of a wireless channel simulation module, a media access control module and a logic link control module; the wireless channel simulation module is used for carrying out modeling simulation on a physical channel transmitted in reality in an FPGA (Field Programmable Gate Array), and the channel distributes control signals to different nodes according to the control signals of the media access control module and transmits high-speed data transmitted by an upper-layer transmitting end back to the media access control module after passing through the simulated channel; the wireless channel simulation module has two functions of quantizing a channel model and quantizing an error rate model; in the quantization implementation of channel simulation, the quantization implementation of a channel model is completed, and the FPGA calculates the SNR in the transmission process through the sending frequency, the distance and the system transmission loss parameters transmitted by the upper layer; and randomly carrying out packet loss on the data according to the PER in quantization implementation of the error rate model so as to simulate real communication.

The invention belongs to the technical field of multi-camera cooperative imaging, and discloses a multi-camera cooperative anti-shake control system and method. The method comprises the following steps: generating a global hardware trigger signal by using an FPGA (Field Programmable Gate Array), synchronizing IMU and multi-camera acquisition, and combining motion parameters to obtain a space-time aligned multi-view image; obtaining a global jitter component through feature extraction, motion vector field generation, depth map analysis and the like; fusing the data with IMU data to generate a trajectory, and inputting the trajectory into LSTM to obtain future compensation amount; and cutting based on deep layered transformation to obtain an EIS optimized frame, dynamically electing a main camera for super-resolution reconstruction, and outputting a final anti-shake video stream. Through multi-source information fusion, layered precise compensation and dynamic optimization, the accuracy and stability of motion estimation are remarkably improved, the jitter influence of the finally output video stream is effectively weakened, and the reliability and visual coherence of the image stabilization effect in a complex scene are ensured.

The invention relates to the technical field of real-time kernel performance testing of special chips, in particular to a special chip real-time performance evaluation method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: (1) aiming at a real-time system on an ASIC (Application Specific Integrated Circuit) chip, setting an external interrupt source and an interrupt service program through a hardware interrupt controller; (2) two tasks with the same priority are created, scheduling of the tasks is achieved through time slice rotation, and a real dynamic load scene is simulated; (3) configuring an external FPGA (Field Programmable Gate Array) to generate a square wave signal to trigger external interruption of the ASIC chip, receiving a feedback signal, and connecting the FPGA and the GPIO through an external physical connecting line to form a hardware interruption triggering-response closed loop; and (4) realizing nanosecond timestamp capture through a counter built in the FPGA, acquiring time delay data, calculating interrupt response time, and transmitting the time delay data to a PC (Personal Computer) through a UART (Universal Asynchronous Receiver / Transmitter) to calculate a maximum value, a minimum value, an average value and a data jitter range of test data. The method can effectively solve the problem that the traditional internal closed-loop test cannot reflect the real interruption randomness and the dynamic load.

The invention relates to the technical field of serial deserializer design, and discloses an FPGA-based direct-current balanced digital audio and video signal serial deserializer, which comprises a serializer, a deserializer, a control configuration module, a power management module, a configuration storage module and a time sequence control module, the serializer is used for converting parallel digital audio and video data into high-speed serial data streams; the deserializer is used for detecting and repairing abnormal data in the high-speed serial data stream by using a machine learning technology, and converting the repaired high-speed serial data stream back to parallel digital audio and video data; the control configuration module is used for configuring working parameters of the serializer and the deserializer through an external interface; the time sequence control module is used for managing the time sequence relation in the system and ensuring synchronization of data flow between different modules. According to the method, the defects of a traditional deserializer in the aspects of anomaly detection and repair, signal quality evaluation and parameter optimization are overcome, and the stability and quality of high-resolution digital audio and video data transmission are improved.

The embodiment of the invention provides a computing resource configuration method and device of FPGA equipment and the FPGA equipment. The method comprises the steps that a heterogeneous query execution plan is generated according to a query request of a user, and the heterogeneous query plan comprises heterogeneous operators and non-heterogeneous operators; and determining a first number of resource blocks required to be configured for executing the heterogeneous operator based on the calculation throughput for processing a non-heterogeneous operator adjacent to the heterogeneous operator and the calculation throughput which can be provided by a single resource block in a programmable array logic FPGA (Field Programmable Gate Array) device. Through the embodiment of the invention, the problems that the throughput of the FPGA equipment is not matched with the calculation throughput of the CPU and the resources of the FPGA equipment cannot be reasonably utilized in the current dynamic configuration scheme in the related technology are solved, and the effect of ensuring that the resources of the FPGA equipment are reasonably utilized in the query acceleration process of the database is achieved.

The invention provides a vehicle-mounted passive optical network area gateway and a protocol conversion method. The gateway comprises an interface module which comprises a plurality of communication interfaces, wherein the communication interfaces are used for receiving messages of a low-speed network protocol; the data processing module adopts an FPGA (Field Programmable Gate Array) core board and is used for receiving a message, extracting effective information from the message, packaging the effective information to obtain an Ethernet protocol frame and converting the Ethernet protocol frame into an SDU (Service Data Unit); and the ONU optical module is used for performing data link layer processing on the SDU to obtain an uplink FS burst frame, and performing physical layer processing on the uplink FS burst frame to obtain a burst mode optical signal frame. The gateway can realize data access of multiple paths of CAN nodes, LIN nodes and vehicle-mounted Ethernet nodes at the same time, meets the communication protocol conversion function of low-speed nodes in each region in a real vehicle environment, and is integrated into a whole vehicle all-optical backbone network. The method is used for converting data complying with a low-speed network protocol into data complying with an XGS-PON protocol.

The invention discloses an FPGA (Field Programmable Gate Array) implementation method of a DVB (Digital Video Broadcasting) high-speed demodulator. A digital signal enters a parallel DDC (Direct Digital Control) module and is re-adapted to multiple symbol rates; the parallel AGC module adjusts the power of the digital signal to a fixed power value; the method comprises the following steps: passing through Oamp; m algorithm: completing symbol synchronization; related peaks are extracted, and frame synchronization is completed; correcting the frequency to enable the frequency to reach participation frequency deviation; performing frequency compensation on the digital signal after loop filtering; after error information is calculated and filtered, the digital signal is compensated; and restoring the original information of the digital signal. According to the invention, by adopting the parallel processing module, the real-time performance and the parallelism degree of digital signal processing can be greatly improved, and the performance of the whole demodulator is enhanced. Each module is designed to be adaptive to the change of a digital signal, for example, the AGC module can dynamically adjust the power of the digital signal to ensure that the output digital signal is always kept at a fixed power level so as to adapt to different receiving conditions.

The invention provides a method for predicting a single event effect induced failure rate of an FPGA (Field Programmable Gate Array) system in radiation. The method comprises the following specific steps: representing a radiation environment of the FPGA system; determining the sensitivity of the single particle effect of the FPGA system in the radiation environment; and establishing a fluence domain reliability model of the FPGA system in the radiation environment: converting the characteristics of the single event effect cross section sigma SEE into a corresponding average fault-free fluence MFTF, and establishing an FPGA system reliability model of each energy spectrum band or LET spectrum band in a given radiation fluence according to the average fault-free fluence MFTF and the total number phi of particles passing through a unit area in a radiation field. According to the method, physical process analysis and data driving means are combined, and the fluence domain reliability model is established, so that the reliability of related equipment in a special physical environment is improved.

The invention relates to the technical field of data processing, in particular to an FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) cooperative network data processing system, which comprises a network interface module for receiving and forwarding an external data flow, and a protocol analysis module for distinguishing a service message and a protocol message based on a message header characteristic and a load mode; the service processing module executes protocol format conversion, security encryption and data extraction in the FPGA; the protocol stack interaction module transmits a protocol message to the CPU through the MAC layer communication interface; the protocol stack module activates necessary protocol services in the CPU and generates a resource allocation instruction; and the data integration module receives the service data flow and the protocol processing result, and dynamically adjusts the encryption rule. According to the invention, FPGA business data closed-loop processing and CPU protocol service physical isolation are realized, a double-processing-unit architecture supports financial signature and industrial filtering cascade operation, the MAC layer interface is additionally provided with cyclic redundancy check to guarantee transmission reliability, and equipment processing efficiency and anti-attack capability under a fusion scene are improved.

The invention relates to the technical field of Ethernet communication, in particular to an automatic negotiation and link training architecture based on an FPGA and a control method, and the architecture comprises a PMA physical medium connection module which comprises a plurality of channels, and each channel is provided with an AN / LT unit; the SWH exchange and processing module is used for receiving a plurality of channel data and distributing the channel data to the corresponding PCS physical coding sub-layer modules so as to carry out coding operation and decoding operation on the channel data; the AN auxiliary logic module and the AN / LT channel control logic module are mutually independent from the PCS physical coding sub-layer module, the AN auxiliary logic module is used for assisting the automatic negotiation function of an AN / LT unit, and the AN / LT channel control logic module is used for controlling the automatic negotiation and link training process of the AN / LT unit and channel rebinding processing. The invention provides a more flexible AN / LT architecture, and the capability of coping with complex and changeable working conditions is improved.

The invention discloses a digital oscilloscope adaptive time width triggering and time width anomaly detection method, which comprises the following steps: after an ADC (Analog to Digital Converter) acquires a signal, uploading sampling data to an upper computer, obtaining a proper time width triggering condition by utilizing a time width triggering setting adaptive algorithm and a time width anomaly detection adaptive algorithm on the upper computer, and designing a time width triggering module in an FPGA (Field Programmable Gate Array) to realize time width anomaly detection. And then the trigger conditions are issued to a time width trigger module in the FPGA, real-time detection and storage of signals meeting the conditions are completed, and finally the signals meeting the set time width trigger conditions and the signals with abnormal time widths are displayed on the upper computer.

The invention provides a PCIe (Peripheral Component Interconnect Express)-Ethernet high-speed data transmission system based on an FPGA (Field Programmable Gate Array), which belongs to the field of communication of digital circuits and comprises a PCIe interface module, a gigabit Ethernet interface module, a DDR3 (Double Data Rate 3) cache module and an AXI (Advanced eXtensible Interface) bus control module. The high-speed data transmission capability of the PCIe interface and the flexible port expansion capability of the gigabit Ethernet interface are integrated, and a user datagram protocol (UDP)-based control logic is constructed to realize data interaction between the PCIe and the gigabit Ethernet, so that high-speed and reliable data transmission is realized; and the high requirements of a high-speed signal acquisition and playback system and the like on the data transmission rate and reliability are met.

The invention relates to a system for realizing real-time complex radar pulse generation based on an FPGA (Field Programmable Gate Array), which comprises a plurality of groups of digital complex radar data generation modules, a pulse switch matrix module, an IQ (In-phase Quadrature) modulation path module and a radio frequency path module, each group comprises a carrier generation module, a pulse generation module, an intra-pulse modulation generation module, a complex number multiplication module and a power regulation module, and the output end of the pulse generation module is connected with the intra-pulse modulation generation module; the output end of the carrier generation module and the output end of the intra-pulse modulation generation module are connected with the complex number multiplication module, and the output end of the complex number multiplication module is connected with the power regulation module. By adopting the system for realizing real-time complex radar pulse generation based on the FPGA, the time consumed by the whole system for generating a multi-target complex radar modulation signal is within a us level, and the problem that software generated data is limited by the duration of a radar signal is avoided.

The invention provides a dynamic high-precision PTP (Precision Time Protocol) time synchronization system realized based on an FPGA (Field Programmable Gate Array), which comprises a master device and a slave device, and the master device and the slave device are connected through a PHY (Physical Layer) to carry out PTP time synchronization; the master device and the slave device have the same structure and comprise an FPGA and a voltage-controlled crystal oscillator; in the master device, the FPGA obtains the frequency difference and the phase difference between the master device and an externally input reference source, further adjusts the frequency of a voltage-controlled crystal oscillator, corrects a local time mark, and sends a PTP message to the slave device; and in the slave equipment, the FPGA obtains the frequency difference and the phase difference between the slave equipment and the master equipment based on the received PTP message, so that the frequency of the voltage-controlled crystal oscillator is adjusted, and the local time scale is corrected. According to the invention, low-cost and high-precision PTP time synchronization is realized.

The embodiment of the invention relates to the technical field of communication, in particular to a TSN network switch for data monitoring cache multiplexing based on an FPGA, which comprises n ports, a network switching module and a network monitoring module, each port is connected with a TSN network node, the network switching module is connected with each port and the network monitoring module, and the network monitoring module is connected with the n ports. The network monitoring module, the TSN network monitoring equipment necklace, the network switching module and the network monitoring module are jointly operated in an FPGA (Field Programmable Gate Array); the network switching module is simultaneously used for inputting 2n data streams generated by the n ports to the network monitoring module; a cache multiplexing unit is arranged in the network monitoring module, and n FPGA caches are reserved for 2n data streams by the cache multiplexing unit; and the network monitoring module is used for screening the 2n data streams based on a preset monitoring strategy and outputting the screened data streams to the TSN network monitoring equipment. Therefore, the occupation of FPGA resources is effectively reduced, and the flexibility and practicability of network monitoring are improved.

The invention discloses a method for deploying a flame detection spiking neural network on an FPGA (Field Programmable Gate Array). According to the method, codes of the flame detection spiking neural network are written by using a Viis HLS tool, an IP (Internet Protocol) core file is generated and burnt on the FPGA, a related digital circuit is generated, the processing speed of the flame detection spiking neural network is accelerated, and the operation power consumption is reduced. And in the design process, the technical means such as ATAN arc tangent activation function calculation and short-circuit logic calculation strategies are realized by utilizing a lookup table, so that unnecessary calculation and power consumption can be reduced, the use amount of a DSP (Digital Signal Processor) is remarkably reduced, the hardware calculation operation process is simplified, and the pulse neural network can run on an FPGA (Field Programmable Gate Array) with relatively low power consumption. Therefore, the method provided by the invention provides a set of solution for implementing effective deployment on the low-power-consumption edge equipment based on the FPGA for a flame detection application scene.

The invention discloses a low-resource and low-energy-consumption remote sensing image brain-like computing system based on an FPGA (Field Programmable Gate Array), which belongs to the cross technical field of brain-like computing and remote sensing information processing, and comprises a data interaction module which is used for high-speed data transmission between a PC (Personal Computer) end and the FPGA and comprises a PCIe (Peripheral Component Interconnect Express) interface sub-module and a data transmission control sub-module; the storage control module is used for data interaction control of the off-chip DDR and the on-chip BRAM and providing efficient data supply for the processing engine; the processing engine module is used for simulating a brain-like pulse neural network to complete convolution calculation of the remote sensing image; comprising a convolution processing sub-module, a data storage sub-module, an input buffer sub-module and an output buffer sub-module. According to the low-resource and low-energy-consumption remote sensing image brain-like computing system based on the FPGA, the brain-like pulse neural network is adopted, the BRAM is allocated to store the intermediate computing result, and the computing unit is designed in combination with SNN characteristics, so that energy consumption and resource waste are effectively reduced, and computing efficiency is improved.

The invention discloses a method for realizing real-time simulation on an FPGA (Field Programmable Gate Array) by using fixed-point operation. The method comprises the following steps: carrying out per-unit processing on a differential equation of a simulated system to obtain a per-unit differential equation; performing discretization processing on the per unit differential equation to obtain a per unit differential equation; converting the per-unit difference equation into corresponding hardware description based on fixed-point operation; and integrating the hardware description, and deploying the hardware description on an FPGA for operation. Therefore, simulated systems with different numerical scales can be converted into a unified numerical scale through per unit, and simulation calculation is realized on the FPGA based on fixed-point operation, so that the cost of real-time simulation is greatly reduced, and the simulation frequency and the simulation precision are improved.

The invention provides a method for rapidly determining the center position of an electron cloud cluster of a reading circuit in an XS anode detector, and aims to solve the problems that the existing method for calculating the center position of the electron cloud cluster of the reading circuit in the XS anode detector cannot realize higher spatial resolution, or easily causes image distortion, and is inconvenient to use. The software processing speed is slow, the FPGA is not easy to implement, or the calculation error at the edge strip is relatively large. The method for rapidly determining the center position of the electronic cloud cluster of the reading circuit in the XS anode detector is realized by adopting an FPGA (Field Programmable Gate Array), the peak value of effective data of each channel is obtained through single-channel processing, and then a corresponding drop point distribution index code is generated through table look-up and cross-channel processing; and then adaptive weight selection is carried out according to the drop point distribution index code, so that the weight accuracy of weighted average operation is ensured, key support is provided for rapid and accurate calculation of the center position of the electronic cloud cluster, and high efficiency and accuracy of the whole data processing flow are ensured.

The invention relates to a data transmission processing system, method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps of: transmitting received storage data from a host to a rear end through a storage data forwarding module in an FPGA (Field Programmable Gate Array) chip; the method comprises the following steps: controlling a stored data forwarding module to be initialized through an SOC chip under the condition that transmission of stored data is detected to be abnormal; controlling the register module to obtain queue pointer information of the host; the obtained queue pointer information is stored in the initialized storage data forwarding module; sending a retransmission instruction to the initialized storage data forwarding module; and further executing a data retransmission operation of the stored data according to the received retransmission instruction through the initialized stored data forwarding module so as to transmit the stored data to a rear end in a lossless manner. By adopting the method, lossless data transmission can be realized, and the stability and robustness of the system are improved.

The invention discloses an FPGA (Field Programmable Gate Array) and an interference suppression method based on the FPGA. The FPGA comprises an eigenvalue decomposition IP (Intellectual Property) core, an interference range expansion module, a matrix inversion IP core and an interference suppression module. According to the interference range expansion module, the virtual interference source is arranged near the real interference source, the null width of a received signal can be expanded, angle diffusion interference in a wide range can be covered, interference energy leakage is suppressed, and the interference suppression effect is enhanced; by customizing two IP cores (an eigenvalue decomposition IP core and a matrix inversion IP core) realized based on HLS and performing eigenvalue decomposition and matrix inversion operation based on the two IP cores, the phenomenon of iteration delay in an FPGA of a traditional structure can be slowed down, the operation speed of the FPGA is improved, and the real-time performance of interference suppression is enhanced.