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2469 results about "Field-programmable gate array" patented technology

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an Application-Specific Integrated Circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools.

Device for producing orthogonal local oscillation signal in continuous Doppler ultrasound imaging system

The invention discloses a continuous Doppler US imaging system orthogonal intrinsic signal generation device, which comprise a field programmable gate array (FPGA), a crystal oscillator, a first digital-analog converter and a second digital-analog converter. The output end of the field programmable gate array (FPGA) is connected with the input ends of the first digital-analog converter and the second digital-analog converter; the crystal oscillator is respectively connected with the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the crystal oscillator is used for supplying synchronizing clock signals to the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the field programmable gate array (FPGA) is used for outputting the sine value corresponding to the phase value to the first digital-analog converter according to the input phase value and outputting the cosine value corresponding to the phase value to the second digital-analog converter; the first digital-analog converter is used for converting the sine value into the corresponding analog signals; the second digital-analog converter is used for converting the cosine value into the corresponding analog signals.
Owner:SHENZHEN LANDWIND IND

Three-dimensional ladar module with alignment reference insert circuitry

ActiveUS7436494B1Minimize layer-to-layerMinimize channel-to-channel “ jitter ”Optical rangefindersElectromagnetic wave reradiationShift registerSignal processing circuits
A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.
A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.
Owner:NYTELL SOFTWARE LLC

Extensible multichannel parallel real-time data acquisition device and method

ActiveCN102521182AEasy to scale massivelyGood parallel data processing capabilityElectric digital data processingComputer moduleData transmission
The invention discloses an extensible multichannel parallel real-time data acquisition device and method. The device comprises a PXIe (PCI (Peripheral Component Interconnect) Extensions for Instrumentation Express) backboard, a CPU (Central Processing Unit) board card and a plurality of FPGA (Field-Programmable Gate Array) acquisition cards; the PXIe backboard comprises a CPU motherboard slot, a clock board slot, a plurality of FPGA board card slots and a PCIe (Peripheral Component Interface Express)/PCI switching bridge; the data transmission between the CPU board card and the FPGA acquisition cards is achieved by PCIe switches, and the P2P (Peer-to-Peer) data transmission is carried out among the FPGA acquisition cards; a clock module provides a system differential clock, differential synchronization signals and differential star-shaped triggers through a clock bus and is downwardly compatible with a PXI clock; and the FPGA board card slots realize the compatibility between a PXI and a Compact PCIe board card through a PCI bus and the PCIe/PCI switching bridge. The invention further provides the method based on the device. The device and the method have the advantages of high sampling rate, fast data transmission and easiness for the large-scale extension of a plurality of board cards.
Owner:SOUTH CHINA NORMAL UNIVERSITY

System for updating FPGA (Field Programmable Gate Array) configuration program from a long distance based on control of processor and method therefor

The invention discloses a system for updating an FPGA (Field Programmable Gate Array) configuration program from a long distance based on the control of a processor and a method for updating the FPGA configuration program from a long distance based on the control of the processor. The system comprises a processor module, an FPGA module, an SPI (Serial Peripheral Interface) memory module and a buffer module, wherein the processor module is connected with the SPI memory module and is connected with a communication interface, the SPI memory module is connected with the FPGA module, and the processor module is connected with the SPI memory module by the buffer module. When the configuration program of an FPGA requires to be updated, an upper computer or a terminal downloads the FPGA configuration program into the SPI memory module through the communication interface and the processor module, and the FPGA module can automatically load the configuration program memorized in the SPI memory module in a MasterSPI mode. According to the system and the method, the FPGA configuration program is updated from a long distance, the function of updating the configuration program on line under the non-outage situation is realized, and therefore, the system and the method are particularly suitable for on-site application.
Owner:ZHUZHOU CSR TIMES ELECTRIC CO LTD

ARM (advanced RISC (reduced instruction set computer) machines) and FPGA (field-programmable gate array) based navigation and flight control system for unmanned helicopter

The invention discloses an ARM (advanced RISC (reduced instruction set computer) machines) and FPGA (field-programmable gate array) based navigation and autonomous flight control system for an unmanned helicopter. The system comprises a PC (personal computer), an integrated navigation subsystem, a power supply module and controllers, wherein the integrated navigation subsystem comprises a sensor group; the sensor group comprises a GPS (global positioning system), a gyroscope, an accelerometer, a magnetoresistive sensor, a barometric altimeter and a sonar altimeter; the controllers include a main controller and a steering engine controller; the main controller adopts an ARM microprocessor to operate the integrated navigation algorithm and flight control PID (proportion integration differentiation) algorithm and simultaneously completes data acquisition of the GPS, the barometric altimeter and the sonar altimeter; and the steering engine controller adopts an FPGA to realize data acquisition of the gyroscope, the accelerometer and the magnetoresistive sensor and transfers the data to the main controller via a concurrent bus to carry out attitude calculation and control operation on the unmanned helicopter. With the unmanned helicopter as a carrier, the hardware environment of a whole set of flight control system integrating study of the aircraft navigation and control theory problem, data acquisition, information transfer and embedded control is set up.
Owner:TIANJIN UNIV

Microelectronic package having stacked semiconductor devices and a process for its fabrication

A packaged microelectronic device having a first and second electrically interconnected microelectronic elements and a method for its manufacture. Conductive posts extend from one major surface of the first microelectronic element. The first microelectronic element is electrically interconnected to the second microelectronic element via the conductive posts. The first microelectronic element preferably has an interposer element from which the conductive posts extend. The second microelectronic element is interconnected to the interposer element via contacts on the second microelectronic element via the conductive posts. The so interconnected microelectronic elements have coordinated functionality, such as a programmable logic device wherein one microelectronic element is a field programmable gate array and the other microelectronic element is a memory device. The packaged microelectronic device is formed by using a transfer substrate to transfer solder masses onto at least some of the conductive posts extending from the first major surface of the first microelectronic element or contacts on the second microelectronic element. The solder masses are then used to electrically interconnect the conductive posts with the contacts disposed on the surface of the second microelectronic element.
Owner:TESSERA INC

Design method of hardware accelerator based on LSTM recursive neural network algorithm on FPGA platform

The invention discloses a method for accelerating an LSTM neural network algorithm on an FPGA platform. The FPGA is a field-programmable gate array platform and comprises a general processor, a field-programmable gate array body and a storage module. The method comprises the following steps that an LSTM neural network is constructed by using a Tensorflow pair, and parameters of the neural networkare trained; the parameters of the LSTM network are compressed by adopting a compression means, and the problem that storage resources of the FPGA are insufficient is solved; according to the prediction process of the compressed LSTM network, a calculation part suitable for running on the field-programmable gate array platform is determined; according to the determined calculation part, a softwareand hardware collaborative calculation mode is determined; according to the calculation logic resource and bandwidth condition of the FPGA, the number and type of IP core firmware are determined, andacceleration is carried out on the field-programmable gate array platform by utilizing a hardware operation unit. A hardware processing unit for acceleration of the LSTM neural network can be quicklydesigned according to hardware resources, and the processing unit has the advantages of being high in performance and low in power consumption compared with the general processor.
Owner:SUZHOU INST FOR ADVANCED STUDY USTC

Pipeline detection robot

InactiveCN104565675ADetect CorrosivityDetect cracksPigs/molesEngineeringMotor controller
The invention relates to a pipeline detection robot. The pipeline detection robot mainly comprises a laser detection mechanism (1), a traction mechanism (2), an electromagnetic ultrasonic detection mechanism (3) and an electronic cabin (4), all of which are connected through connecting hinge shafts; the traction mechanism (1) adopts a single-motor all-drive mode and is driven by a turbo-worm synchronous belt to supply a walking power to the robot; the laser detection mechanism (2) comprises a laser displacement sensor, a rotating arm, a counterweight, a support body and the like and is used for measuring surface corrosion and deformation of a pipeline; the electromagnetic ultrasonic detection mechanism (3) comprises a support assembly, a probe and a fixing plate and is used for measuring the wall thickness and the crack defect of the pipeline; the electronic cabin (4) is used for carrying auxiliary components, such as a stepping motor controller, a servo motor driver, a power supply and an FPGA (Field Programmable Gate Array) control panel. The pipeline detection robot disclosed by the invention can be used for finding the defects, such as pipeline corrosion, cracks and deformation, carrying out in-service detection on an oil and gas pipeline in a working process, carrying out targeted repair, maintenance and replacement according to a detection result, reducing the maintenance cost and guaranteeing safe and stable operation of the oil and gas pipeline.
Owner:BEIJING INSTITUTE OF PETROCHEMICAL TECHNOLOGY
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