147 results about "Field-programmable gate array" patented technology

The invention relates to a full-unloading regular matching system and method based on an FPGA (Field Programmable Gate Array). The system comprises a regular rule compiling unit and an FPGA full matching unit, the regular rule compiling unit is used for receiving a regular rule set, extracting each rule fixed feature substring, compiling the uniform format isomorphic NFA, and constructing a mapping relation table of the substrings and the corresponding NFA; the FPGA full matching unit comprises a parallel high-speed character string matching engine array, a character string-NFA mapping table module, a full-quantity regular data memory, a reconfigurable general NFA engine module and a matching result output module; and the reconfiguration engine module is used for executing full unloading regular matching on the input network traffic: scanning the traffic through the engine array, screening to-be-verified traffic containing a fixed feature substring and outputting a substring identifier, querying the NFA identifier through the mapping table module, and loading NFA matching by the reconfiguration engine module. By adopting the method, low delay and high throughput performance of regular matching in a high-speed network environment can be ensured.

The invention discloses a lining pipeline interface contact pressure distribution testing device and method, relates to the technical field of pipeline detection, and aims at solving the problem that in the prior art, interface contact pressure distribution is difficult to represent in a lossless and quantitative mode. The device comprises a testing machine moving platform, an overground control moving platform, a lining pipe wall testing claw, an ultrasonic signal transceiver and a three-dimensional imaging module, the testing claw carries four curved-surface ultrasonic probes, and signals are collected in a one-transmitting-multiple-receiving mode controlled by an FPGA (Field Programmable Gate Array); according to the method, a contact pressure characterization model is constructed through self-adaptive positioning and signal excitation and processing, and interface pressure distribution visualization is achieved in combination with a three-dimensional imaging technology. The method does not need to damage the pipeline structure, can accurately capture the spatial distribution characteristics of the contact pressure, is adaptive to the conventional detection of long-distance pipelines, provides a scientific basis for lining repair quality evaluation and pipeline operation safety, and is convenient to operate and high in applicability.

The invention discloses a multi-dimensional metering system and metering method based on an FPGA, and belongs to the technical field of electronic data processing, and the system comprises a data collection module which is used for obtaining and preprocessing multi-source sensing data; the simulator construction module is used for constructing a multi-physics field interference simulator and loading a geometric model and a physical response coefficient of a reference shadow workpiece, the reference shadow workpiece is digital representation of an actual measured workpiece, and the geometric model and the physical response coefficient of the reference shadow workpiece are mutually decoupled data sets; the vector field generation module is used for generating a pre-distortion vector field based on the output of the interference simulator and the reference shadow workpiece; and the interference identification module is used for extracting primary features from the multi-source sensing data. Through constructing a multi-physical field interference simulator and generating a pre-distortion vector field, physical state drift of a cross-sensing channel is accurately modeled, a multi-sensor data fusion error is reduced, and data consistency and reliability in a high-speed dynamic measurement scene are improved.

The invention discloses a temperature-pressure-resistant vibration methane carbon isotope detection system for oil and gas logging, which belongs to the technical field of oil and gas logging and comprises a gas sample pretreatment module, an optical sensing module, a driving and temperature control module and a core control and algorithm module. The core control module is realized by an FPGA (Field Programmable Gate Array) and is integrated with a self-adaptive multi-resolution scanning and compressed sensing reconstruction algorithm. The method comprises the following steps: performing current segmented scanning and wavelength modulation on the laser; light path anti-vibration coupling is realized through closed-loop control of the MEMS galvanometer; acquiring sparse sampling spectrum data; reconstructing a high-resolution spectrum by using compressed sensing; and inversing CH4 and CH4 concentrations by adopting Voigt linear fitting, and calculating a delta C value. The precision, the speed and the long-term stability of methane carbon isotope detection in a logging site temperature-pressure vibration coupling disturbance environment are remarkably improved.

The invention relates to a frame format online reconstruction system and method based on an FPGA (Field Programmable Gate Array) external memory, belongs to the technical field of carrier rockets, and solves the problems of long development period and code compatibility of single-task software. The system comprises a TOP module, a RESET function module, an MLVDS communication function module, an EEPROM storage function module and a frame format reconstruction function module, the EEPROM storage function module is used for performing write operation on configuration parameters sent by a main module according to function division of a storage space and solidifying the configuration parameters in an EEPROM, and after power-off restart reset is finished, the EEPROM storage function module is used for performing write operation on the configuration parameters sent by the main module. Reading operation is executed on the EEPROM, and read configuration parameters are distributed to a frame format reconstruction module according to functional area division; and the frame format reconstruction function module is used for executing reconstruction logic operation of the frame format. By means of the system, productization and generalization design of multi-task model software is achieved, and the software reuse rate is remarkably increased.

The invention discloses an encryption burst communication receiving method based on an FPGA, and belongs to the technical field of burst communication. According to the invention, the problems of poor synchronization performance and poor anti-interference capability at the receiving end in the existing method are solved. According to the method, the carrier synchronization range is expanded by introducing the pilot frequency to enable the synchronization heads to be '1', the limitation that a conventional frequency offset estimation algorithm can only work under the condition that the Doppler frequency shift is smaller than 0.5 times of the symbol rate is broken through, and the capacity of the system for adapting to the high-dynamic environment is improved. A spreading code continuous tracking working mode is designed, coarse estimation and synchronization are carried out in a frame header part, spreading codes are still adopted in an information part, and continuous tracking is carried out, so that the system can adjust the phase of the spreading codes in real time in the whole frame to solve the problem of phase error accumulation caused by adopting a low-precision clock; the problems that when one frame of data at the sending end is long, the synchronization performance is reduced when a low-precision clock is adopted, and even effective synchronization cannot be achieved are solved. The method can be applied to the field of burst communication.

The invention discloses a portable anti-interference medium-wave TACAN station evaluation system, which comprises a radio frequency front-end module and a digital signal processor, and is characterized in that the radio frequency front-end module is used for transmitting, receiving and frequency conversion of radio frequency signals; the digital signal processing module comprises an FPGA (Field Programmable Gate Array), a built-in digital signal processing module, an inquiry pulse generation module and a time sequence control and data rejection module; according to the invention, through designing the integrated evaluation system, deep sharing and multiplexing of hardware resources such as a radio frequency channel, a signal processing unit and a power supply module are realized; the data rejection module based on the emission time sequence automatically activates a protection window when the equipment emits an inquiry pulse, identifies and rejects generated invalid navigation information in real time, and ensures that a final evaluation result completely depends on valid data of a receiving time period, so that the accuracy and reliability of station evaluation data are improved.

The invention discloses an umbrella-type adaptive sound source positioning device, which belongs to the field of acoustics, and comprises a measurement system, which is of an umbrella-type power connecting rod structure carrying a microphone array, a temperature sensor and a displacement sensor; the positioning system is an integrated unit which takes an FPGA (Field Programmable Gate Array) as a core and is connected with a sampling module, a feedback module and a display module; wherein the sampling module synchronously digitizes a sound signal, a temperature signal and a displacement signal and then transmits the signals to the FPGA; the FPGA executes a generalized cross-correlation TDOA algorithm based on the received signal to obtain sound source azimuth information, and outputs a control signal; the feedback module receives the control signal and drives the power connecting rod structure so as to change the relative spatial position of each microphone in the microphone array; and the display module displays sound source azimuth information in real time. According to the invention, an umbrella type mechanical structure is used, a proper structure can be adaptively adjusted so as to more accurately position a sound source, the real-time performance is good, and the anti-noise performance is strong.

The invention discloses a real-time compiling interpreter system capable of running on an MCU (Microprogrammed Control Unit), an FPGA (Field Programmable Gate Array), a GPU (Graphics Processing Unit) or a universal CPU (Central Processing Unit), and belongs to the technical field of embedded systems and computer compiling. According to the system, hardware decoupling is achieved through a modular architecture, and C / C + +, Python and LLVM intermediate codes are supported to be converted into unified intermediate byte codes; a byte code interpreter and an instant compiling module are integrated, both quick starting and efficient execution are considered, and starting can be completed within 1 millisecond; an event driving and periodic scheduling mechanism is provided, and the real-time response requirement is met; a segmented memory model and a security policy are adopted, low-power-consumption edge equipment is adapted, and domestic instruction sets such as RISC-V and LoongArch are compatible. The system solves the problems that a traditional embedded system is poor in flexibility, difficult in cross-platform, insufficient in real-time performance and the like, can achieve unified execution of heterogeneous platform codes, is suitable for the fields of industrial control, Internet of Things edge AI and the like, and has remarkable technical progress and industrial value.

The invention belongs to the technical field of chip algorithms, and particularly relates to a circular array beam forming method and system based on a domestic FPGA. Comprising the following steps: receiving multiple paths of array element signals, and performing frequency mixing and filtering to obtain baseband I / Q data; the base band I / Q data is unpacked to be distributed and stored in a plurality of distributed memories in an FPGA (Field Programmable Gate Array) processing unit; the method comprises the following steps: reading baseband I / Q data of a plurality of channels and corresponding phase shift coefficients in parallel, and carrying out multiplication, accumulation, summation and modulo operation to generate data of a beam point; repeating the calculation step of generating the beam point data by updating the phase shift coefficient so as to generate beam domain data; reordering the calculated sequence of the beam domain data, and adjusting the output sequence of the beam domain data; the method has the advantages of being high in processing speed, high in anti-noise capacity and the like on the basis of meeting domestic substitution.

The invention provides an FPGA remote updating method and a related device, and belongs to the technical field of FPGA remote updating. After a first FPGA board card receives a remote updating command, the state of a jump control area synchronization head is obtained from a jump control area, and which application bit stream area is updated is determined based on the state of the jump control area synchronization head; the first FPGA board card erases data in the first application bit stream area or the second application bit stream area; after the data of the first application bit stream area or the second application bit stream area is erased, the second FPGA board card transmits the update data to the first FPGA board card; the first FPGA board card reads back the updated data from the Flash memory, and performs CRC (Cyclic Redundancy Check) on the read-back updated data to obtain a CRC result; and based on a CRC result, determining whether remote updating of the first FPGA board card is completed or not. The method solves the problems that after FPGA logic codes are modified, programming needs to be conducted block by block, a large amount of time and manpower are occupied, and the project progress is seriously affected.

The invention provides an FPGA (Field Programmable Gate Array) device, a test system and a test method, the FPGA device comprises at least two signal acquisition modules, and the signal acquisition modules are used for synchronously sampling received input signals based on a synchronous sampling clock to obtain corresponding sampling data; the processing module is used for allocating a storage address to the sampling data obtained by sampling of each signal acquisition module according to different storage address intervals of the external storage particles; the interconnection module is used for receiving the sampling data of different clock frequencies transmitted by each signal acquisition module and the corresponding storage addresses, and transmitting the sampling data and the corresponding storage addresses at the working clock frequency of the controller; and the controller is used for receiving the sampling data transmitted by the interconnection module and the corresponding storage address, and writing the sampling data into the external storage particles according to the storage address corresponding to the sampling data. According to the FPGA device, the bandwidth utilization rate of written data and the storage capacity utilization rate can be improved.

The embodiment of the invention relates to the technical field of simulation testing, and provides an FPGA online differential testing method and device, equipment and a storage medium, and the method comprises the steps: controlling a to-be-tested FPGA platform to execute a target program; after each instruction is executed, if the current instruction is of a first target instruction type, acquiring register state information when the FPGA platform to be tested executes the current instruction as first to-be-compared state information; according to the offline tracking data, acquiring register state information when the reference platform executes the current instruction as first reference state information; comparing the first state information to be compared with the first reference state information; and outputting a differential test result of the FPGA platform to be tested according to a comparison result. According to the embodiment of the invention, on-line differential testing can be carried out on the FPGA, so that errors can be quickly positioned.

The invention discloses an efficient method for realizing Turbo coding by an FPGA (Field Programmable Gate Array), which comprises the following steps of: before data enters a Turbo coding module, firstly introducing a dual-port RAM (Random Access Memory) and a rate grouping processing module, preprocessing and reasonably segmenting the data, saving time delay, reducing hardware resource consumption, better adapting to the Turbo coding module, and greatly compressing the processing and queuing time of the data in a Turbo coder; after Turbo coding is completed, serial-to-parallel processing is carried out on coded data, and it is ensured that the coded data can be continuously and stably output in a serial mode. According to the method, the problems that a traditional Turbo encoder is large in encoding delay and large in resource consumption are solved, the operation complexity is low, and the Turbo code can be applied to a new wireless communication system.

The invention particularly relates to a complex modulation signal generation method based on multiphase fitting modeling, belongs to the field of radars, and is applied to a radar frequency synthesizer. The method comprises the following steps: by taking an FPGA (Field Programmable Gate Array) and a DAC (Digital-to-Analog Converter) as core hardware, generating an n-phase phase increment sequence through multi-phase fitting modeling according to the phase change characteristics of CW, LFM and NLFM signals and the phase-to-amplitude conversion IP instantiation number of the FPGA; amplitude codes are output through multiple paths of IPs, and after cross sorting is carried out according to the phase relation, the amplitude codes are transmitted to a DAC through an LVDS or JESD204B / C high-speed interface to generate a target signal. According to the method, signal phase characteristics are fitted in a targeted manner, phase increment can be calculated in real time through LFM signal generation, storage is not occupied additionally, the three types of signals are consistent in processing flow, high in universality and easy to transplant, and high-stability and high-precision complex modulation signals can be generated efficiently.

The invention relates to a TSN (Time Sensitive Network) timestamp recovery method based on an FPGA (Field Programmable Gate Array), which belongs to the technical field of TSNs and comprises the following steps of: S1, collecting synchronous messages of different TSN nodes in parallel by multiple ports of the FPGA, and analyzing timestamp data by taking a message serial number as an anchor point; s2, constructing an incomplete timestamp matrix and a mask matrix by adopting a time sliding window mechanism, and automatically marking missing data; s3, a random index set is generated through LFSR, and matrix sparse sampling is achieved through a bitmap judgment unit; and S4, based on an FPGA accelerated CUR matrix decomposition algorithm, solving a pseudo-inverse matrix through parallel MGS-QR decomposition, and reconstructing a complete timestamp matrix through block parallel matrix chain multiplication. The FPGA parallel architecture, ping-pong cache and fixed-point number processing are adopted, microsecond-level low-delay recovery is achieved, hardware resource occupation is greatly reduced, robustness in a severe network environment is improved, and the method is suitable for a high-precision clock synchronization scene of an industrial TSN node.

The invention provides a cloud computing trusted execution environment construction method of an FPGA intelligent network card, which comprises the following steps: encrypting a bit stream by using a user private key to obtain a user network function bit stream, and sending a challenge to a security management software module of the FPGA intelligent network card by a host application; after the security management software module receives the challenge, the public key share is calculated, key data containing the guide mirror image hash value, the challenge and the public key share are signed by using a temporary private key, and a signature is generated; verifying the correctness of the signature by using the temporary public key, and if the verification is passed, determining that the software and hardware environment of the intelligent network card is credible; the host application generates a random number, calculates a public key share of the random number and sends the public key share to the security management software module; the host application and security management software module calculates a session key according to a key exchange protocol; the host application securely transmits the encrypted user network function bit stream to the security management software module.

The invention discloses a converter FPGA (Field Programmable Gate Array) small-step real-time simulation device and method based on a per unit fixed-point reconfigurable state space solution core. The upper computer processing unit carries out per-unit processing on converter model parameters according to the per-unit reference of the introduced margin coefficient, discretization and fixed-point word length configuration are completed under the preset step length, and a discrete fixed-point matrix coefficient table is generated for different switch / topology states and is downloaded to the FPGA. A universal fixed-point matrix operation array is arranged in the FPGA simulation unit, a pre-stored matrix coefficient is called according to a switch combination index obtained through real-time analysis during operation, and per unit fixed-point state updating and output inverse per unit are completed in a fixed time sequence prediction; therefore, on-line reconstruction and small-step real-time simulation of topology and parameters of the converter are realized under the condition that the FPGA bit stream is not updated.

The application discloses a five-tuple rule matching method and device based on FPGA (Field Programmable Gate Array) multi-rule templates, and a plurality of rule templates are stored in a high-bandwidth memory, the rule templates are cascaded, and when rule matching is performed on five-tuple information in a to-be-processed message, a non-cascaded / cascaded mode is adopted to match the rule templates, so that an action strategy of the to-be-processed message is acquired. Each template matching information is flexible and configurable, complex matching functions are realized through inter-template cascading, the number of templates is effectively reduced, and system resources are reduced.

The invention belongs to the technical field of PET (positron emission tomography), and relates to a PET probe extensive field image multi-model adaptive deformation and FPGA (field programmable gate array) curing method, which comprises the following steps of: acquiring single-lift event data of a PET probe; generating an original extensive field image based on the single-lift event data; performing coordinate traversal transformation on the original extensive field images by adopting an image deformation model in a preset multi-model transformation library; performing off-line analysis on each model and the parameters thereof in the multi-model transformation library by utilizing a preset evaluation index, and screening out an optimal model and an optimal parameter; and transforming the original pan-field image by using the optimal model and the optimal parameters to generate an enhanced image and a crystal position lookup table, and solidifying the enhanced image and the crystal position lookup table to the FPGA. The method has the beneficial effects that the local adhesion area can be stretched in a targeted manner through the nonlinear transformation model, the distinction degree of crystal event clusters is remarkably improved, and the LUT calibration precision is fundamentally improved.

The invention provides an approximate multiplier based on a field programmable gate array (FPGA), which comprises an asymmetric partial product generation module, a signal processing module and a signal processing module, and is characterized in that the asymmetric partial product generation module is used for processing a received N-bit multiplier and a received N-bit multiplicand to generate an asymmetric approximate partial product matrix of which the line number is halved; the single-step compression module is used for compressing the asymmetric approximate partial product matrix into two rows at one time; and the final summing module is used for summing the two rows of compressed data and outputting a final product. Through the collaborative design of asymmetric partial product generation and single-step compression, high-energy-efficiency and low-delay approximate multiplication is realized on an FPGA platform, and the method is suitable for application scenes such as resource-limited edge calculation and the like.

The invention discloses a fault-tolerant method, system and device for preventing FPGA program solidification updating failure and a medium. The method comprises the steps that a register address skipped by a golden mirror image address is adjusted to be an initial address of a Timer1 mirror image; in the Timer1 mirror image, back-off enabling is started, meanwhile, a countdown register is started to start countdown counting, in the constraint file for updating the mirror image, back-off enabling and countdown counting are started, and the counting length exceeds the normal loading time of the FPGA program; in the Timer2 mirror image, back-off enabling is started, a countdown counter is started, when an address jump instruction exists in the updated mirror image, a countdown register is reset to be zero, and value assignment is carried out again in the Timer2 mirror image; in a development platform, the golden mirror image, the Timer1 mirror image, the updating mirror image and the Timer2 mirror image are used for generating an MCS file used for FPGA solidification according to corresponding addresses. The method can ensure that the equipment normally returns to the golden mirror image after the equipment fails to update the curing program.

The utility model discloses a high-order FIR (Finite Impulse Response) filter based on an FPGA (Field Programmable Gate Array), relates to the technical field of digital signal processing, and solves the technical problems of low resource utilization rate and higher energy consumption caused by the fact that an adder of an existing distributed FIR filter occupies a large number of resources. The device comprises an input register module, a lookup table address generation module, a lookup table module and a shift accumulation module which are connected in sequence, the lookup table address generation module is used for splicing the two pieces of data with the same filter coefficient and decomposing the two pieces of data according to bits, and the data on the same bit form a lookup table address vector; the lookup table module groups the address vectors according to five bits and outputs corresponding partial products through a cascaded LUT6 lookup table, and the LUT6 is configured to be of a five-input and double-output structure; and the shift accumulation module is used for shifting the obtained partial products according to the weight corresponding to each partial product and accumulating all shifted results. The device has the advantages of high resource utilization rate and the like.

The invention provides a low-delay feedback communication system and a low-delay feedback communication method based on an FPGA (Field Programmable Gate Array), which allow data transmission to be started under any master clock without dead time. Meanwhile, received data are allowed to be automatically used for correcting the delay shift value in real time, manual setting is not needed, appropriate calibration parameters can be obtained only through two-layer circulation in the calibration process used for achieving delay self-calibration, the logic occupation amount is small, applicability is high, use is easy, convenient and reliable, and the method is suitable for large-scale popularization and application. The low-delay feedback is allowed to be realized in a simple and reliable manner. Particularly, by means of a specific calibration parameter valuing mode, the stability of correctly receiving data is further improved, and implementation of the low-delay feedback process is facilitated. Besides, in the invention, the transmission requirement of communication data can be met only by using a pair of differential signal lines, and a source synchronous clock (namely a channel associated clock) does not need to be sent.

The embodiment of the invention discloses an FPGA (Field Programmable Gate Array) model reasoning hardware adaptation method based on a Qwen-2 low-bit quantization technology. According to the embodiment of the invention, quantitative perception training is carried out on a Transform layer of a Qwen-2 model so as to keep reasoning precision; converting the quantized weight and activation value into a fixed-point format supported by the FPGA and generating a quantization parameter table; according to DSP and BRAM resource distribution of the FPGA, mapping low-bit matrix operation to a DSP unit, storing quantization parameters in the BRAM, and planning a task scheduling sequence; a parallel pipeline is designed for an attention layer and a feed-forward layer, low-bit storage optimization is carried out on key value cache, and dynamic quantization adjustment is carried out on an activation value; and finally, deploying to an FPGA for testing, and performing closed-loop optimization on a hardware mapping strategy or quantization granularity based on delay and resource data. According to the method, the model precision is effectively maintained while the storage and calculation overhead is remarkably reduced.

The invention relates to an FPGA (Field Programmable Gate Array)-based ADC (Analog to Digital Converter) verification device and a verification method thereof. The FPGA-based ADC verification device comprises an ADC board card interface module, a clock module, an FPGA module and a power module, the output end of the ADC board card interface module is connected with the FPGA module; the output end of the clock module is connected with the FPGA module; and the output end of the power supply module is connected with the FPGA module. According to the method, the batch full-automatic test of the verification parameters of the ADC sampling board card is realized, and the final channel verification parameter value is calculated and sent to the upper computer, so that the test complexity is simplified, the test efficiency is greatly improved, and the labor cost is reduced.

The invention provides a self-adaptive hybrid scheduling accelerator based on an FPGA (Field Programmable Gate Array) and an implementation method thereof. The accelerator comprises a control interface unit (CIU), a multi-level priority queue array (MPQA) and an adaptive scheduling core (ASH). The method aims at solving the problems of large task scheduling delay, slow interrupt response, system throughput bottleneck and the like caused by a traditional software scheduler in a heterogeneous multi-core SoC, a high-requirement embedded system and an edge computing node.

The utility model discloses a data acquisition network transmission system based on an FPGA (Field Programmable Gate Array) detector, which comprises a signal receiving and preprocessing module, a signal routing and switching module, a signal conditioning and amplifying module, an analog-to-digital conversion module, a core processing and control module, a data transmission module and a PC (Personal Computer) control and display module, the signal receiving and preprocessing module, the signal routing and switching module, the signal conditioning and amplifying module and the analog-to-digital conversion module are electrically connected in sequence, and the core processing and control module, the data transmission module and the PC control and display module are electrically connected in sequence. And the signal routing and switching module and the analog-to-digital conversion module are electrically connected with the core processing and control module respectively. According to the utility model, the core processing and control module is used as a data processing core, so that high-speed data acquisition is realized, the real-time requirement is met, the processing capability is improved, the complex signal processing requirement is met, the flexible configuration of the system structure is realized, and the system is suitable for different application scenes.

The utility model discloses a multi-source heart rate data acquisition device, which comprises a controller, a work indicating lamp, a power indicating lamp, a switch, a millimeter wave radar heart rate data interface, a millimeter wave radar heart rate data amplifier, an FPGA (Field Programmable Gate Array) compression memory, a video heart rate data amplifier, a video heart rate data interface, a communication module, a display, a shell and a power interface, according to the utility model, the first heart rate data measured by the millimeter wave radar and the second heart rate data acquired by the camera can be obtained at the same time, so that comprehensive understanding of the heart rate data is facilitated; non-contact heart rate data acquisition is carried out through the millimeter wave radar and the camera, heart rate monitoring is carried out on a user, privacy of the user can be protected, contact with the user is avoided, great convenience is brought to crowds needing long-term continuous heart rate monitoring, the risk of cross infection is avoided, monitoring instrument operation is reduced, and the monitoring efficiency is improved. The security is high, and the management efficiency is improved.

The invention relates to a multi-beam data screening optimization processing method based on image sonar. Aiming at the problems of weak target signal annihilation and insufficient image sharpness caused by a traditional arithmetic average method, the method adopts a maximum value screening strategy to carry out multi-beam data fusion. The method comprises the following specific steps: carrying out preprocessing and TVG compensation on sonar original echo data; obtaining a plurality of beam data through parallel beam forming; for each distance unit, traversing and comparing the signal intensity of all beams, and selecting the maximum value as the final pixel value of the unit; and then median filtering noise reduction and configurable point picking processing are carried out. According to the method, the detection probability of a weak target and a point target can be remarkably improved, a sonar image with high contrast and high sharpness is generated, and meanwhile, different detection tasks are flexibly adapted by integrating multiple fusion and point selection modes. The method is efficient in calculation, is easy to realize on embedded platforms such as a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array) and the like, and has good engineering application value.