368 results about "Application-specific integrated circuit" patented technology

The invention relates to the technical field of chip task allocation, and discloses a task allocation optimization method and device for a multi-core heterogeneous ASIC (Application Specific Integrated Circuit) computing mainboard. Computing core setting information of the computing mainboard is collected, a mainboard computing performance model is generated through digital feedback processing, an executable task set is obtained, and the computing requirement of each task is analyzed; performing simulation analysis on the calculation demand set based on the performance model by using an optimization algorithm, generating a task allocation plan, identifying and generating task execution characteristics of a currently executed task, allocating the task execution characteristics according to the task allocation plan, and scheduling calculation resources to process the current task. The resource performance is accurately simulated through the performance model, the optimization algorithm ensures efficient resource allocation, responds to task changes in real time, maximizes the utilization of heterogeneous computing resources, improves the overall computing efficiency, and solves the problem of execution delay when real-time task allocation is carried out on the multi-core heterogeneous ASIC computing mainboard in the prior art.

The invention relates to the technical field of computing task balancing, and discloses a dynamic load balancing method and system for a multi-core heterogeneous ASIC computing mainboard, which comprises the following steps: collecting performance data of each computing core on the multi-core heterogeneous mainboard, generating a computing core information set, analyzing the load adaptability of the computing cores based on the performance data, and obtaining load adaptation feature distribution; the load condition of the calculation core is monitored in real time to obtain a load change trend, the future load condition is predicted, load adaptive feature distribution and load prediction are combined, balance optimization is carried out, a load balancing scheme is generated to adjust load distribution of the calculation core, dynamic load balancing is achieved, the utilization rate of calculation resources is improved, and overload or idling of the calculation core is avoided. The system performance and the response speed are improved, different load requirements are met, load changes are dynamically adapted, task scheduling and energy efficiency management are optimized, and the problem that in the prior art, a task allocation scheme is dynamically and continuously changed in a balanced mode in real time, and consequently the execution effect of a mainboard is poor is solved.

An application specific integrated circuit (ASIC) for computing a convolutional neural network (CNN) has a first input bus that receives a stream of ordered values from an array, each location in the array having one or more channels, and a plurality of kernel processing blocks that receive inputs through a configurable multiplexer. The arrangement and connection of the kernel processing blocks and the bus enable the ASIC to operate as a pipeline system and transmit the output stream in a manner synchronized with the input stream.

Blockchain environments may mix-and-match different encryption, difficulty, and / or proof-of-work schemes when mining blockchain transactions. Each encryption, difficulty, and / or proof-of-work scheme may be separate, stand-alone programs, files, or third-party services. Blockchain miners may be agnostic to a particular coin's or network's encryption, difficulty, and / or proof-of-work schemes, thus allowing any blockchain miner to process or mine data in multiple blockchains. GPUs, ASICs, and other specialized processing hardware components may be deterred by forcing cache misses, cache latencies, and processor stalls. Hashing, difficulty, and / or proof-of-work schemes require less programming code, consume less storage space / usage in bytes, and execute faster. Blockchain mining schemes may further randomize byte or memory block access, further improve cryptographic security.

The invention relates to the technical field of real-time kernel performance testing of special chips, in particular to a special chip real-time performance evaluation method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: (1) aiming at a real-time system on an ASIC (Application Specific Integrated Circuit) chip, setting an external interrupt source and an interrupt service program through a hardware interrupt controller; (2) two tasks with the same priority are created, scheduling of the tasks is achieved through time slice rotation, and a real dynamic load scene is simulated; (3) configuring an external FPGA (Field Programmable Gate Array) to generate a square wave signal to trigger external interruption of the ASIC chip, receiving a feedback signal, and connecting the FPGA and the GPIO through an external physical connecting line to form a hardware interruption triggering-response closed loop; and (4) realizing nanosecond timestamp capture through a counter built in the FPGA, acquiring time delay data, calculating interrupt response time, and transmitting the time delay data to a PC (Personal Computer) through a UART (Universal Asynchronous Receiver / Transmitter) to calculate a maximum value, a minimum value, an average value and a data jitter range of test data. The method can effectively solve the problem that the traditional internal closed-loop test cannot reflect the real interruption randomness and the dynamic load.

The invention discloses a finger-storage-multiply-accumulate three-stacked floating-point number in-memory computing system, and belongs to the field of application-specific integrated circuit design. According to the system, a three-stack type floating-point number calculation framework is designed, a pointing shift and mantissa multiply-accumulate module is designed, and floating-point number multiply-accumulate calculation of global pointing is supported. Compared with a traditional parallel floating-point multiply-accumulate circuit, the parallel floating-point multiply-accumulate circuit has the advantages that a calculation process of global alignment shifting and mantissa multiply-accumulate in sequence and a three-stack type calculation framework are adopted, similar calculation precision is achieved with smaller hardware overhead, low hardware overhead and high calculation precision are both considered, and the comprehensive performance of the calculation framework and the circuit is improved.

The invention discloses a pair of intelligent eyesight monitoring and eye disease prediction glasses, and aims to solve the problems that most of existing eye health monitoring devices are used for regular inspection, cannot monitor and predict the eye health condition in real time and are difficult to take intervention measures in time, the glasses comprise glasses legs and a glasses main body, and the glasses main body is provided with an inner side facing a wearer; the glasses body further comprises a miniature camera, an optical sensor, a master control system and a battery system. The miniature camera is connected with the main control system through an application-specific integrated circuit, and the miniature camera is installed on the inner side of the glasses body facing the eyes of a wearer and used for shooting eye images of the wearer in real time and capturing the pupil size, eyeball movement and sight line direction of the wearer; the optical sensor is connected with the main control system and is used for detecting the ambient light intensity and color and adjusting the brightness of the lenses of the glasses main body; the eye health condition of the teenagers can be monitored and predicted in real time, and accurate health data support is provided for parents, teachers and ophthalmologists.

The invention provides an OIO core particle and an AI computing cluster, which are applied to the technical field of photoelectric transmission, and the OIO core particle comprises an optical chip, an electric chip and a micro-control chip or a micro-control application-specific integrated circuit. An optical chip, an electric chip and a control unit are packaged into an OIO core particle, the core particle works independently as an OIO, and the bandwidth and linearity of a system are improved by adopting an analog light and electric equalization technology in the optical chip and the electric chip. And the core particles are applied to a Scale-up network in the node and are used for interconnection between GPUs (Graphics Processing Unit). Compared with a copper cable interconnection scheme, the method has the advantages that the interconnection distance can be greatly increased, and the scale of a Scale-up network for GPU interconnection is expanded; compared with the existing optical module interconnection scheme, the optical module interconnection method has the advantages of low time delay, low power consumption, high bandwidth density and high reliability; the chip particle interconnection can adapt to the diversity requirements of AI chips and systems, and can be integrated into their systems by clients according to their own requirements.

In one embodiment, a method may receive a request to upgrade software for a switch. The method may use an application-specific integrated circuit (ASIC) simulator to generate a digital twin to store a first image and a first configuration of the switch. The method may use the digital twin to generate a second image and a second configuration by replaying the first configuration on the first image. The method may communicate the second image and the second configuration from the digital twin to an ASIC memory of an ASIC associated with the switch by applying batch direct memory access (DMA).

This disclosure describes techniques for an isolated Root of Trust (RoT) component of a System on Chip (SoC), such as an SoC associated with a networking-related application, to: (i) enforce access to one or more protected addresses associated with the SoC using a secure communication channel, (ii) limit access to one or more restricted addresses to authorized external devices, and / or (iii) detect an operational environment within which the SoC operates based on access rates associated with special addresses associated with the SoC and modify operation of the SoC based on the detected operational environment. The RoT component may be implemented as a dedicated security subsystem with an isolated processor and memory regions that are inaccessible to the rest of the SoC.

The invention discloses an MEMS (Micro Electro Mechanical System) chip, a preparation method of the MEMS chip, a micro electro mechanical system gas sensor and a gas detection device. The MEMS chip comprises a first pole plate and a second pole plate, a cavity is formed between the first pole plate and the second pole plate, a dielectric substance in the cavity is gas, the first pole plate is provided with a first vent hole, the cavity is communicated with the outside through the first vent hole, and the second pole plate is provided with a second vent hole. The mechanical resonant frequency of the first polar plate is far greater than the frequency of sending voltage excitation to the MEMS chip by an ASIC (Application Specific Integrated Circuit) chip, or both the mechanical resonant frequency of the first polar plate and the frequency of sending voltage excitation to the MEMS chip by the ASIC chip are 60 kHz to 100 kHz; the first pole plate and the second pole plate form a variable capacitor, and the dielectric substance of the variable capacitor is gas, so that the sensitivity of the MEMS gas sensor using the MEMS chip can be improved.

This disclosure describes techniques for an isolated Root of Trust (RoT) component associated with a system-on-chip (SoC), such as a networking-related SoC, to enforce a persona on the SoC and / or control the operation of the SoC based on the enforced persona. In some cases, the RoT component is configured to: (i) determine a persona associated with the SoC based on firmware associated with the RoT component that defines a persona associated with the SoC, (ii) modifies one or more configurations associated with the SoC based on the defined persona, (iii) modifies the operation of the SoC based on determining that the SoC is operating in an operational environment that is different from the operational environment associated with the defined persona, and / or (iv) switches between two or more available personas associated with the SoC based on determining a change in an operational environment associated with the operation of the SoC.

Various example embodiments for supporting network security for a communication network are presented herein. Various example embodiments for supporting network security for a communication network may be configured to support programming of security functions, including security rules, into network devices. Various example embodiments for supporting programming of security functions into network devices may be configured to support programming of security functions into high performance application-specific integrated circuits (ASICs) of the network device. Various example embodiments for supporting programming of security functions into network devices may be configured to support programming of security functions into various types of network device, such as routers, switches, servers, or the like.

The invention belongs to the technical field of space environment detection, and relates to an ASIC (application specific integrated circuit)-based multichannel parallel charge detection device for space charged particle detection, which comprises an anode plate, a front placing plate and a digital acquisition and processing plate, and signal transmission is performed between the anode plate and the front placing plate as well as between the front placing plate and the digital acquisition and processing plate through inter-plate connectors; the anode plate is an annular anode and is divided into a plurality of anodes, the output of each anode is connected with a current-limiting resistor in series, and a charge signal output by each anode is transmitted to the front amplifier plate through the inter-plate connector; the pre-amplification board adopts an integrated charge sensitive amplifier ASIC to amplify multiple paths of charge signals output by the anode plate, and outputs multiple paths of digital pulses to be input into the digital acquisition processing board through an inter-board connector; and the digital acquisition and processing board is used for detecting and counting multiple paths of digital pulses output by the pre-amplification board in parallel, and periodically packaging and outputting the digital pulses to a PC (Personal Computer) end.

A system and method for deploying machine learning models with consistent fixed-point arithmetic processing. A computing device in a vehicle receives a trained machine learning model that was trained using training images processed with fixed-point arithmetic operations. The computing device receives images from a camera and processes the received images using fixed-point arithmetic operations that are consistent with those used during training. The machine learning model is executed using the processed images to detect objects such as vehicles, pedestrians, persons on bikes, stop lights, or stop signs. The computing device may comprise specialized hardware including a graphics processing unit (GPU), digital signal processing hardware decoder, or single-purpose hardware decoder such as an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The system may generate alerts or determine vehicle operation changes based on detected objects, and may operate in surveillance mode when the vehicle is parked.

A sensor module for Raman spectroscopy includes a sensor package which encloses an application specific integrated circuit (ASIC), a light emitter arrangement, a light detector arrangement and a filter arrangement. The light emitter arrangement is electrically connected to the ASIC and operable to emit light with multiple excitation wavelengths to excite Raman scattering in an external probe to be placed outside of the sensor module. The light detector arrangement is operable to generate sensor signals from incident light emitted back from the external probe due to the Raman scattering. The filter arrangement is operable to filter the incident light according to a target passband. The ASIC is operable to drive the light emitter arrangement at the excitation wavelengths to shift a Raman spectral band of the external probe into the passband of the filter arrangement.

The invention discloses a current sensor, a current detection method and a chip. The current sensor comprises a diversion module, a magnetic sensing module, an application-specific integrated circuit module and a magnetic field compensation module, the diversion module is configured to introduce and export a detection current, and the application-specific integrated circuit module is configured to drive the magnetic field compensation module to drive an electric signal to operate according to the detection current; the application-specific integrated circuit module is further configured to output a driving electric signal under the condition that the first magnetic field component of the diversion module and the second magnetic field component of the magnetic field compensation module reach a balance state at the magnetic sensing module. According to the current sensor, the magnetic sensing module is adopted to sense the magnetic field generated by the detection current, the circuit signal output by the magnetic sensing module based on the change of the magnetic field is processed through the application-specific integrated circuit, and the magnetic field compensation module is controlled according to the processing result to form the balanced magnetic field so as to realize the closed-loop detection of the detection current. Therefore, the accuracy of current detection is improved, and the null drift phenomenon of the current sensor is improved.

The invention discloses an X: M dynamic attention sparseness method and device, and the method comprises the steps: carrying out the prediction of an attention score matrix, and carrying out the X: M structured pruning based on a prediction result, so as to obtain a pruning result; and updating the minimum line number and the index line number in the cache based on a pruning result, adjusting a scheduling threshold, and storing the index block number meeting the condition into a priority queue so as to map the corresponding index to a PEA processing unit array for execution. According to the method, the storage and calculation overhead of attention prediction is greatly reduced, and meanwhile, X: M is combined with a scheduling algorithm, so that a processing unit in an application-specific integrated circuit can keep an extremely high utilization rate under different sparseness.

Described herein is a novel approach that leverages a 3D stacked die complex with an active optical interposer integrated with an I / O chiplet including high-speed serializer / deserializer (SerDes). By integrating silicon in this way, shoreline constraints are eliminated, allowing for the SerDes macros to be placed virtually anywhere on the I / O chiplet. The photonic-based interconnects described herein improve upon conventional approaches based on co-packaged optics (CPO), Linear-drive Pluggable Optics (LPO) and copper-based solutions in terms of bandwidth and power consumption. The interconnects described herein rely on photonic-electronic packages in which a PIC provides processing units (e.g., XPU), electronic switching chips or other types of application-specific integrated circuits (ASIC) with access to optical fiber-based networks while multiple SerDes provide high-speed serialization and deserialization.

According to the remotely-controllable pressurization type electric sprayer, any infrared remote control transmitter for an original television and an electromagnetic pump for a coffee machine are adopted, the sprayer is low in cost and convenient to use, pressurization spraying is far, a one-way thyristor VTH, a diode VD2-5 and an electromagnetic pump F form a remote control main loop, and therefore when an integrated circuit of the one-way thyristor VTH loses trigger voltage, the remote control electric sprayer can be started and stopped. The alternating current is switched off when passing zero; the infrared receiving tuned amplifier A1 adopts an infrared amplification special circuit mu PC1373; the infrared receiving tuned amplifier A1 is also provided with a buffer inverter A2 which adopts a common hex inverter digital integrated circuit CD4069, and only two intact NOT gates are arranged in the common hex inverter digital integrated circuit CD4069; the dimming amplifier A3 adopts an integrated circuit HT7700A special for dimming; therefore, a load of a unidirectional thyristor VTH of the infrared light receiving circuit, namely an electromagnetic pump F, is controlled to pressurize the water path.

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.

Provided are a method, a system, a computer program product, an Application Specific Integrated Circuit, and a cryptographic module, where a partitioning is performed of a SHA-2 state update into three blocks. A set of operations associated with the three blocks are executed in a pipelined manner, where each block feeds back for computation into itself.

An artificial intelligence-based business management system for real-time decision optimization, consisting of: a data acquisition unit configured to ingest structured, semi-structured and unstructured data streams from enterprise resource planning (ERP) systems, customer relationship management (CRM) platforms, Internet of Things (IoT) devices, external market feeds and financial transaction systems, encrypting, timestamping and verifying the data prior to further processing; a graph processing unit that is communicatively connected to the said acquisition layer, wherein the unit is configured to encode heterogeneous data into dynamic graph structures comprising nodes representing business entities and edges representing transaction or relationship dependencies, wherein the unit is further configured to perform deduplication, metadata tagging and real-time data synchronization; a decision optimization unit operationally linked to the graph processing unit, wherein the decision optimization unit includes modules for reinforcement learning, modules for Bayesian optimization and multi-objective solvers configured to simulate multiple alternative decision paths and select an optimal path based on performance indicators such as cost efficiency, resource utilization, customer satisfaction and risk minimization; a real-time inference control unit with specialized hardware cores, including at least one graphics processing unit (GPU), a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), wherein the accelerator performs inference tasks of the decision optimization unit with a latency in the millisecond range; a diagnostic processing unit configured to generate causal diagrams, feature mapping maps, and interpretable result summaries according to the optimization outputs; and a control interface unit configured to transmit optimized decisions to process controls within the enterprise, robot actuators, planning systems or interactive dashboards, with the interface supporting bidirectional communication for higher-level interventions, error feedback and triggers for re-optimization.

[Problem] An object is to provide a lead sulfate coating removal device that has low power consumption and does not damage an electrode of a lead-acid battery.[Solution]A lead sulfate coating removal device implemented by an application specific integrated circuit (ASIC) that removes a lead sulfate coating generated on an electrode of a lead-acid battery includes: a generation unit that generates, on the basis of a signal extracted from the lead-acid battery, a removal signal of the lead sulfate coating having a peak value of 550 mA to 1000 mA, a pulse width of 5 nsec to 100 nsec, and a frequency of 5 kHz to 50 kHz; and a supply unit that supplies the removal signal generated by the generation unit to the electrode of the lead-acid battery.

The invention relates to a power consumption optimization method and device for a multi-core heterogeneous ASIC (Application Specific Integrated Circuit) computing mainboard. The method comprises the following steps: in combination with task attribute information of each calculation task in a multi-core heterogeneous ASIC calculation mainboard and heterogeneous attribute information of each heterogeneous processing unit, performing calculation resource allocation processing on each calculation task in a chemical reaction optimization algorithm to obtain a calculation resource allocation result of each calculation task; obtaining the task path length and task relaxation time of each calculation task by combining the calculation resource allocation result of each calculation task and the running state of each heterogeneous processing unit; and in combination with the task path length and the task relaxation time of each calculation task, obtaining each adjusted heterogeneous processing unit under the condition of meeting the deadline constraint of the calculation task, so as to execute each calculation task according to the optimal energy consumption ratio. By adopting the method, high-efficiency and low-power-consumption computing resource scheduling can be realized.

A system for integrated data provenance and reconciliation across heterogeneous financial systems, the system includes: a data ingestion module implemented as a hardware interface and configured with high-throughput adapters for structured and unstructured data ingestion from multiple heterogeneous financial subsystems, including bank ledgers, securities trading platforms, risk management databases, and regulatory reporting systems; a schema harmonization processing unit consisting of a dedicated FPGA (Field Programmable Gate Array) structure configured to perform real-time schema alignment, metadata normalization, and semantic mapping across different data models; a lineage tracking processor array implemented on application-specific integrated circuits (ASICs) and configured to encode dataflow transitions into a graph-encoded structure in which each node represents a transformation and each edge represents a dependency; a reconciliation computation cluster unit embodied as a set of graphics processing units (GPUs) configured to execute parallelized reconciliation techniques, anomaly detection routines, and balance verification processes between transformed financial records and reference records; a cryptographic verification unit comprising secure key storage hardware, quantum-resistant encryption modules, and tamper-resistant enclaves configured to generate, anchor, and verify cryptographic signatures for provenance and reconciliation events; a secure storage subsystem configured in a WORM (write-once, read-many) configuration with hardware-based integrity locks for storing immutable provenance and reconciliation logs; a controller with a dedicated visualization processor configured to generate interactive dashboards and drill-down analyses of lineage charts and voting results; and a modular chassis structure consisting of a high-speed backplane interconnect, secure power distribution modules, and tamper-evident enclosures, enabling the system to achieve real-time scalability, hardware-level security, and auditability of financial data flows across heterogeneous infrastructures.

The present invention provides systems and methods for utilizing an application-specific integrated circuit (ASIC) for an artificial neural network connected to the memory, the ASIC comprising: a plurality of neurons organized in an array, wherein each neuron comprises a register, a processing element and at least one input, and a plurality of synaptic circuits, each synaptic circuit including a memory for storing a synaptic weight, wherein each neuron is connected to at least one other neuron via one of the plurality of synaptic circuits, wherein the array is configured to analyze said business sale transaction information trained on historical datasets relating to asset utilization, wherein the AI / ML categorization engine makes a prediction regarding the most efficient use(s) of an asset.

The present disclosure describes a system and method for preempting a long-running process with a higher priority process in a machine learning system, such as a hardware accelerator. The machine learning hardware accelerator can be a multi-chip system including semiconductor chips that can be application-specific integrated circuits (ASIC) designed to perform machine learning operations. An ASIC is an integrated circuit (IC) that is customized for a particular use.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.