118 results about "Application-specific integrated circuit" patented technology

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.

An artificial intelligence-based business management system for real-time decision optimization, consisting of: a data acquisition unit configured to ingest structured, semi-structured and unstructured data streams from enterprise resource planning (ERP) systems, customer relationship management (CRM) platforms, Internet of Things (IoT) devices, external market feeds and financial transaction systems, encrypting, timestamping and verifying the data prior to further processing; a graph processing unit that is communicatively connected to the said acquisition layer, wherein the unit is configured to encode heterogeneous data into dynamic graph structures comprising nodes representing business entities and edges representing transaction or relationship dependencies, wherein the unit is further configured to perform deduplication, metadata tagging and real-time data synchronization; a decision optimization unit operationally linked to the graph processing unit, wherein the decision optimization unit includes modules for reinforcement learning, modules for Bayesian optimization and multi-objective solvers configured to simulate multiple alternative decision paths and select an optimal path based on performance indicators such as cost efficiency, resource utilization, customer satisfaction and risk minimization; a real-time inference control unit with specialized hardware cores, including at least one graphics processing unit (GPU), a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), wherein the accelerator performs inference tasks of the decision optimization unit with a latency in the millisecond range; a diagnostic processing unit configured to generate causal diagrams, feature mapping maps, and interpretable result summaries according to the optimization outputs; and a control interface unit configured to transmit optimized decisions to process controls within the enterprise, robot actuators, planning systems or interactive dashboards, with the interface supporting bidirectional communication for higher-level interventions, error feedback and triggers for re-optimization.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

Circuitry and method are described for enabling multiple loads on a differential low voltage differential signaling pair (M-LVDS). A printed circuit board (PCB) contains a M-LVDS driver and leads that route a main channel that carries a differential signal from the driver to an area in which loads are populated. The main channel is split into branches that contain application-specific integrated circuits (ASICs) as the loads. The branches have the same characteristic impedance as the main channel. Filters are disposed in each branch and are coupled between the driver and the ASICs. Each filter is a first order or higher filter. Fewer filters than ASICs are on each branch, with the filters being disposed between the driver and ASICs closest to the driver (with smaller propagation delay). The filters are configured differently at each ASIC input to compensate for the delay.

A radiation detector unit including an interposer configured to electrically connect a pixelated radiation sensor positioned on a front side of the interposer to an application-specific integrated circuit (ASIC) positioned on a back side of the interposer, where the interposer has at least one feature which equalizes the energy resolution (ER) response of edge and center pixel detectors of the pixelated radiation sensor within 10% of one another.

The invention discloses a robot anti-interference integrated circuit system based on multi-sensor fusion, relates to the technical field of automatic control, and aims to solve the problems that in ultra-precision hole machining, due to the fact that complex multi-mode vibration of a boring rod cannot be decoupled and accurately compensated in real time, and the machining precision is high. The system comprises a sensor array which is configured on a key structure of an end effector of an industrial robot and is used for collecting multi-dimensional physical signals related to mechanical vibration in real time; the application-specific integrated circuit is in signal connection with the sensor array and the robot controller, and the application-specific integrated circuit comprises a vibration reconstruction and compensation amount determination module which is used for receiving, fusing and processing multi-dimensional physical signals collected by the sensor array; according to the method, a real-time vibration deformation modal reconstruction and mapping system based on a spatial distributed sensing array and a special integrated circuit is constructed, so that the complex dynamic deformation of the boring rod in the machining process is identified.

A silicon photonic bridge and method of manufacturing an integrated circuit semiconductor package may be provided. The system may include an interposer layer formed from a combination of organic and inorganic materials. The silicon photonic bridge may be embedded within the interposer layer. The silicon photonic bridge may include an electrical integrated circuit (IC) configured to process electrical signals and drive the photonic IC (PIC), and a PIC configured to process optical signals, an optical connector element(s) configured to interface the PIC with fiber and a silicon bridge configured to interface between an ASIC integrated on top of the interposer with the EIC. A silicon photonic bridge may be electrically and optically enabled to convert the electrical signal from the ASIC above the interposer to an optical signal going into fiber, and vice versa. Through-silicon vias (TSVs) may extend through the optical engine.

This application provides a tensor computation method and related apparatus. Through this method, a unified preprocessing is used to obtain the corresponding sign bit, exponent part, and mantissa part for tensors of different data types. Then, through subsequent general exponent accumulation, mantissa multiplication, comparison, shifting, and addition processing, the above unified processing logic can be adapted to the computational needs of different data tensors. Compared with the design idea of ​​equipping each data type with dedicated integrated circuits, this fundamentally eliminates circuit redundancy, thereby reducing chip area, reducing power consumption, and improving flexibility.

A system including multiple processing devices such as application-specific integrated circuits (ASICs). Each processing device is provided with light at one or more wavelengths. Each processing device outputs data, at the wavelength of the optical signal received, to one or more interfaces. Each interface outputs a multiplexed signal containing data from each of the processing devices on a single optic fiber.

The utility model relates to the technical field of MEMS device packaging, and particularly discloses a strip-shaped clamp for an MEMS device, and the MEMS device comprises an MEMS sensor and a special integrated circuit needing to be subjected to an injection molding process; the strip-shaped clamp comprises a frame part and a central part; the central part comprises a plurality of parallel long strip parts which are arranged at intervals; the two ends of each long strip part in the plurality of long strip parts are respectively connected with the frame part so as to form a plurality of strip-shaped openings; the corners of the strip-shaped opening are arranged to be fillets; and under the condition that the MEMS device is arranged below the strip-shaped clamp, the strip-shaped opening is used for exposing an application-specific integrated circuit of the MEMS device so as to carry out an injection molding process, and the strip-shaped part is used for covering an MEMS sensor of the MEMS device. According to the strip-shaped clamp, the cleaning difficulty can be reduced, the manufacturing cost can be reduced, the influence of sputtered resin points in the injection molding process on the performance of the MEMS device can be effectively prevented, and the packaging yield of the MEMS device is effectively improved.

Micromechanical sensor device with: an ASIC substrate (10) with a first front side (VSa) and a first back side (RSa); a rewiring device (20) formed on the first front side (VSa) with a plurality of stacked conductor track levels (LB0, LB1) and insulation layers (I); a MEMS substrate (9) with a second front (VS) and a second back (RS); a first micromechanical functional layer (16) formed above the second front surface (VS); a second micromechanical functional layer (17) formed above the first micromechanical functional layer (16), which is connected to the rewiring device (20) via a bond connection (50); wherein a movable sensor structure (MS) is formed in the second micromechanical functional layer (17) which is anchored on one side to the MEMS substrate (9) via a first anchoring area (17b') formed in the second micromechanical functional layer (17); wherein in the second micromechanical functional layer (17) an electrical connection element formed in a second anchoring area (17d; 17d'; 17d'') is anchored on one side via a contact area (52) of the bond connection (50) on the ASIC substrate (10); and wherein the first anchoring area (17b') and the second anchoring area (17d; 17d'; 17d'') are elastically connected to each other via a spring element (17c) formed in the second micromechanical functional layer (17).

A nano-scale capacitive pressure sensor formed of an array of capacitive pressure cells is disclosed. The capacitive pressure sensor is integrated with an ASIC working as a pressure sensor and a PUF. Each of capacitive pressure cells is a hermetically sealed cavity and includes a first stationary conductive membrane and a second conductive membrane that deflects due to a force (pressure change) applied on the array of capacitive pressure sensor cells. A method of manufacturing the nano-scale capacitive pressure sensor is also disclosed.

A state estimation method for mobile robot navigation is provided which includes: step S1, initializing the processing module, and then controlling the field-programmable gate array to obtain measurement values of a moment k collected by the inertial measurement unit and the localization apparatus in a constant sampling period; step S2, controlling the application-specific integrated circuit to send the measurement values to the processing module; step S3, controlling the processing module to, based on the measurement values, sequentially perform vector padding, additional inertial vector acquisition, normalization processing, alignment error computation, filter measurement value computation, bias estimation value computation, velocity estimation value computation, pose estimation value computation and orthogonalization processing to obtain state estimation values of the moment k; step S4, controlling the processing module to send the state estimation values to the human-machine interface for visual display.

An RF device may include an RF antenna, and an ASIC downstream from the RF antenna. The ASIC may include ADCs configured to generate replica digitized input signals, a DSP core downstream from the ADCs and having first complex coefficient multipliers, first band pass filters respectively coupled to the first complex coefficient multipliers, and a summer downstream from the first band pass filters. The ASIC may also include DACs configured to generate analog output signals, and a feedback loop coupled between the DACs and the ADCs. The RF device may further include a processor configured to control the first complex coefficient multipliers and associated delay circuits.

To provide a method and system for ultrasound imaging and beamforming using a novel matrix array of transducer elements.SOLUTION: The received signal of each transducer array element is amplified. The amplified receive signal of each transducer array element is digitized. Delays and weights are applied to the amplified and digitized received signals. The amplified, digitized, delayed, and weighted receive signals are summed across all transducer elements of the matrix array to form a dynamically focused receive beam. An applicationspecificintegratedcircuit (ASIC) integrated with a matrix array of transducer elements performs such steps.SELECTED DRAWING: Figure 1

Encryption system with an application-specific integrated circuit (ASIC) which has a permanent memory for the non-volatile storage of the operating system (OS) of a processor and software modules for encrypting the data memory of the processor and which has a hardware-implemented encryption algorithm, characterized in that a security module (SM) is integrated in the ASIC for autonomous booting of the operating system (OS), consisting of: - a symmetric cryptosystem (SK) for processing symmetric keys, - an asymmetric cryptosystem (AK) for the use of public and private keys, - a module for generating cryptographic hash functions (KH), - a module for the secure exchange of keys using hardware-implemented key exchange protocols (SP), - a key storage (SS) for the secure storage of root keys (WS), which are protected by appropriate measures in the physical structures of the ASIC and - a key management system (SMS) for the secure introduction of authenticated-encrypted key packets, and that the security module (SM) communicates with a central processing unit (CPU) via a communication interface (CS1), and that the central processing unit (CPU) communicates with at least one internal storage (IS) and one external storage (ES), as well as with at least one internal persistent storage (IP) and one external persistent storage (EP), such that the operating system (OS) is loaded by a second-stage bootloader (SSB) stored in the external persistent storage (EP), and then the operating system (OS) loads the applications, the second-stage bootloader (SSB) itself being decrypted and loaded by a first-stage bootloader (FSB) stored in the internal persistent storage (IP), and a public key (PUBOS) to verify the operating system (OS).and a symmetric key (KOS) to decrypt the operating system (OS), and that the contents of the internal memory (IS) and the external memory (ES) are decrypted by the security module (SM) during read accesses by the central management unit (CMU) or other modules integrated on the ASIC, and re-encrypted during write accesses by the same.

A specialized integrated circuit for artificial neural networks is integrated with high bandwidth memory. The neural network includes a systolic array of interconnected processing elements, including upstream processing elements and downstream processing elements. Each processing element includes a pair of input / output ports for concurrent forward and backward propagation. The processing elements can be used for convolution, in which case the pair of input / output ports can support fast and efficient scanning of a kernel over activations.

In one implementation, a switch tray for a fabric rack includes internal connectors configured to communicatively couple the switch tray to processors located within the fabric rack via a cable backplane. The switch tray also includes a plurality of switch application-specific integrated circuits (ASICs) coupled to the internal connectors and configured to switch intra-rack traffic between the processors located within the fabric rack. The switch tray further includes external connectors coupled to the plurality of switch ASICs, whereby the plurality of switch ASICs are further configured to switch inter-rack traffic between the processors located within the fabric rack and external processors located in one or more external fabric racks.

Optical component (100), comprising: a component substrate (102); a chip of an application-specific integrated circuit (110; 310) arranged on the component substrate (102), wherein the chip of the application-specific integrated circuit (110; 310) includes a detector (112; 312); at least one non-optical sensor chip (116; 316) arranged on the component substrate (102); a preformed polymer field unit cell (128; 328) arranged on the component substrate (102), wherein the preformed polymer field unit cell (128; 328) has at least one cavity (122; 322) and at least one side wall (124; 324) is configured to limit crosstalk between the application-specific integrated circuit (110; 310) and the at least one non-optical sensor chip (116; 316); and a glass cover (134; 334) arranged on the preformed polymer field unit cell (128; 328).

This disclosure describes a system and method for compiling and executing machine learning inferences in an array of multi-core computing devices. Each multi-core computing device can be an application specific integrated circuit (ASIC) or group of ASICS. In many applications, the array of computing devices changes from inference to inference, and can be adjusted based on the requirements of the inference. Additionally, each ASIC can have multiple processing cores, and multiple types of processing cores. Therefore, performing optimizations and scheduling at compile time, can dramatically increase the efficiency of the array in executing the inference. In some implementations, it is possible to select an amount of time or effort to be spent optimizing during compiling, giving the user flexibility in determining whether to spend time during compilation or during execution.

The invention belongs to the field of large-scale application-specific integrated circuit design, and particularly relates to a phase-locked loop circuit. The phase-locked loop circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider; the voltage-controlled oscillator comprises a common-source amplifier, a multi-stage delay unit and a level conversion unit; the control end of the common source amplifier serves as the input end of the voltage-controlled oscillator, and the output end of the common source amplifier is connected with the voltage end of the multi-stage delay unit. The output end of the multi-stage delay unit is connected with the input end of the level conversion unit; the output end of the level conversion unit is used as the output end of the voltage-controlled oscillator; according to the voltage-controlled oscillator, the common-source amplifier is used for controlling the multi-stage delay unit along with the change of the control voltage output by the charge pump so as to adjust the oscillation frequency, and a multi-phase clock signal is output through the level conversion unit, so that the power consumption of the phase-locked loop is reduced, and the output clock has relatively small clock jitter.

An application specific integrated circuit (ASIC) package for use in an electrical or electronic device is disclosed, the ASIC package comprising a plurality of functional units and a plurality of terminals. Each functional unit is configured with control logic operable to provide a discrete monitoring and / or control function associated with an aspect of operation of the electrical or electronic device. Each terminal comprises a plurality of input and / or output terminals, each input and / or output terminal being connected to at least one of the functional units. An operating status of each of the functional units is independently configurable into one of an enabled and non-enabled operational state, and the ASIC package is configured to be set into a target functional configuration selected from a plurality of different functional configurations. Each of the plurality of functional configurations comprises a different combination of operating states associated with respective ones of the plurality of functional units. In this way, the ASIC package provides a degree of customisability of supported functions, enabling the same ‘master’ ASIC package (e.g. the as-fabricated ASIC package) to be modified after manufacture to tailor the supported function set to a specific one of a plurality of devices.

Integrated circuit devices, systems, machine-readable media, and methods are provided to reduce power consumption by supplying a lower voltage to an embedded application-specific integrated circuit (ASIC) block of a programmable logic device than an overall supply voltage while still achieving target performance. An integrated circuit device according this disclosure may include programmable logic circuitry configurable to be set to operate at a first voltage and a first ASIC block configurable to be set to operate at a second voltage different than the first voltage.

An optoelectrical package may include at least one electrical switch application-specific integrated circuit (ASIC) and at least one optical engine. The electrical ASIC may be disposed at a central portion of a communication interface. The electrical ASIC may incorporate a crossbar functionality. The optical engine may be arranged relative to the communication interface. The optical engine may be electrically connected to the at least one electrical ASIC. The optical engine may be disposed adjacent to the at least one electrical ASIC. The optical engine may include a fiber connector for one or more fibers, a photonic integrated circuit, and an electronic integrated circuit. The optical engine may be configured to convert an optical signal obtained from the fiber connector to an electrical signal for use by the electrical ASIC and vice versa.

A marker device embodiment may include separate concentrically-oriented receive and transmit antenna elements coupled to an ASIC which includes electronics to receive an input signal at a first frequency from a transmitter, convert the input signal to a power supply to power the electronic circuit, generate, in response to the input signal, an output signal at a second frequency different from the first frequency, and provide the output signal, via the transmit antenna element, to an above-ground receiver for assistance in determining the location of a buried utility.

In one embodiment, a software and hardware development method include providing a software-hardware interface to provide a data interface between hardware of an application specific integrated circuit (ASIC) and software running on a processor, providing control of a given part of the software-hardware interface to a software feature thereby yielding a more stable software-hardware interface, receiving a request to change the controlled given part of the software-hardware interface, and providing a message responsively to the request to change the controlled given part of the software-hardware interface.

The invention relates to a battery pack, in particular a replaceable battery pack for an electric bicycle, with electronics, wherein the electronics comprise at least one printed circuit board (PCB) on which a control module, a power switch module, and a current sensing module are arranged, the control module comprising at least one processing unit, in particular a microcontroller. It is proposed that the control module comprise at least one ASIC, wherein at least six of the following functions are integrated into the at least one ASIC: a cell voltage monitoring function, a cell balancing function, a current measurement function, a control or regulation function for external compute / digital fetched transistors (CFTs), a power supply function, a communication transceiver, a pre-charging circuit, a temperature sensing function, a wake-up function, and a charge level indicator control function.

A Security System comprises (1) a Wearable Edge Computing AI Chipset (Edge AI) interoperating with one or more Cameras into a Wearable Security System, In-Vehicle Security System, and a Home Security System as part of the Unified AI (Artificial Intelligence) Security System. The security system contains one or more GPS tracked devices that utilizes either an Edge Computing AI Chipset containing a System-on-Chip (SOC) or a custom design Application-Specific Integrated Circuit (ASIC). The Wearable, In-Vehicle and Home Security Systems are controlled by a common Application Programming Interface (API) residing in the Cloud. Each camera video stream is analyzed by the Wearable Edge AI Chipset to detect objects, behaviors, or patterns of interest. When the required conditions are met, alerts are then triggered and sent to the user's mobile app on the cell phone for user review and display, and to his / her trusted contacts.

A semiconductor wafer is provided including: processing cores; and die structures each including at least one processing core. Each processing core includes a set of first input output (I / O) interfaces configured for communication between the processing core and a second processing core, wherein the processing core and the second processing core are included in a first die structure of the die structures. Each processing core includes a second input output (I / O) interface configured for communication between the processing core and a third processing core, wherein the third processing core is included in a second die structure of the die structures. The processing cores are spaced apart by a target distance associated with separating one or more processing cores or one or more die structures from the semiconductor wafer.

The invention relates to the technical field of control circuits, and discloses a multifunctional switching control circuit and method for a car lamp based on a 555 timer, and the circuit comprises a car lamp which comprises a 555 timer chip U5 which works in an astable multivibrator mode and outputs signals with different pulse frequencies, duty ratios and modes by receiving signals of a peripheral resistance-capacitance network, and the 555 timer chip U5 is used for switching the car lamp to the mode of the 555 timer chip U5; the function switching of the vehicle lamp is realized; one end of the resistor RA1 is connected with a power supply pin of the 555 timer chip U5; one end of the resistor RB1 is connected with the resistor RA1, and the other end of the resistor RB1 is connected with a threshold pin of the 555 timer chip U5; and one end of the capacitor C35 is connected with the resistor RA1 and the resistor RB1, and the other end of the capacitor C35 is grounded. According to the multifunctional switching control circuit and method for the vehicle lamp based on the 555 timer, the 555 timer chip which is low in cost and high in stability is adopted to replace a single chip microcomputer or a special integrated circuit in the prior art, the cost of the vehicle lamp control circuit is effectively reduced, and the economical efficiency of a low-cost vehicle type or a specific module is improved.