214 results about "Application-specific integrated circuit" patented technology

The invention discloses a finger-storage-multiply-accumulate three-stacked floating-point number in-memory computing system, and belongs to the field of application-specific integrated circuit design. According to the system, a three-stack type floating-point number calculation framework is designed, a pointing shift and mantissa multiply-accumulate module is designed, and floating-point number multiply-accumulate calculation of global pointing is supported. Compared with a traditional parallel floating-point multiply-accumulate circuit, the parallel floating-point multiply-accumulate circuit has the advantages that a calculation process of global alignment shifting and mantissa multiply-accumulate in sequence and a three-stack type calculation framework are adopted, similar calculation precision is achieved with smaller hardware overhead, low hardware overhead and high calculation precision are both considered, and the comprehensive performance of the calculation framework and the circuit is improved.

A system and method for deploying machine learning models with consistent fixed-point arithmetic processing. A computing device in a vehicle receives a trained machine learning model that was trained using training images processed with fixed-point arithmetic operations. The computing device receives images from a camera and processes the received images using fixed-point arithmetic operations that are consistent with those used during training. The machine learning model is executed using the processed images to detect objects such as vehicles, pedestrians, persons on bikes, stop lights, or stop signs. The computing device may comprise specialized hardware including a graphics processing unit (GPU), digital signal processing hardware decoder, or single-purpose hardware decoder such as an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The system may generate alerts or determine vehicle operation changes based on detected objects, and may operate in surveillance mode when the vehicle is parked.

A sensor module for Raman spectroscopy includes a sensor package which encloses an application specific integrated circuit (ASIC), a light emitter arrangement, a light detector arrangement and a filter arrangement. The light emitter arrangement is electrically connected to the ASIC and operable to emit light with multiple excitation wavelengths to excite Raman scattering in an external probe to be placed outside of the sensor module. The light detector arrangement is operable to generate sensor signals from incident light emitted back from the external probe due to the Raman scattering. The filter arrangement is operable to filter the incident light according to a target passband. The ASIC is operable to drive the light emitter arrangement at the excitation wavelengths to shift a Raman spectral band of the external probe into the passband of the filter arrangement.

Described herein is a novel approach that leverages a 3D stacked die complex with an active optical interposer integrated with an I / O chiplet including high-speed serializer / deserializer (SerDes). By integrating silicon in this way, shoreline constraints are eliminated, allowing for the SerDes macros to be placed virtually anywhere on the I / O chiplet. The photonic-based interconnects described herein improve upon conventional approaches based on co-packaged optics (CPO), Linear-drive Pluggable Optics (LPO) and copper-based solutions in terms of bandwidth and power consumption. The interconnects described herein rely on photonic-electronic packages in which a PIC provides processing units (e.g., XPU), electronic switching chips or other types of application-specific integrated circuits (ASIC) with access to optical fiber-based networks while multiple SerDes provide high-speed serialization and deserialization.

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.

An artificial intelligence-based business management system for real-time decision optimization, consisting of: a data acquisition unit configured to ingest structured, semi-structured and unstructured data streams from enterprise resource planning (ERP) systems, customer relationship management (CRM) platforms, Internet of Things (IoT) devices, external market feeds and financial transaction systems, encrypting, timestamping and verifying the data prior to further processing; a graph processing unit that is communicatively connected to the said acquisition layer, wherein the unit is configured to encode heterogeneous data into dynamic graph structures comprising nodes representing business entities and edges representing transaction or relationship dependencies, wherein the unit is further configured to perform deduplication, metadata tagging and real-time data synchronization; a decision optimization unit operationally linked to the graph processing unit, wherein the decision optimization unit includes modules for reinforcement learning, modules for Bayesian optimization and multi-objective solvers configured to simulate multiple alternative decision paths and select an optimal path based on performance indicators such as cost efficiency, resource utilization, customer satisfaction and risk minimization; a real-time inference control unit with specialized hardware cores, including at least one graphics processing unit (GPU), a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), wherein the accelerator performs inference tasks of the decision optimization unit with a latency in the millisecond range; a diagnostic processing unit configured to generate causal diagrams, feature mapping maps, and interpretable result summaries according to the optimization outputs; and a control interface unit configured to transmit optimized decisions to process controls within the enterprise, robot actuators, planning systems or interactive dashboards, with the interface supporting bidirectional communication for higher-level interventions, error feedback and triggers for re-optimization.

[Problem] An object is to provide a lead sulfate coating removal device that has low power consumption and does not damage an electrode of a lead-acid battery.[Solution]A lead sulfate coating removal device implemented by an application specific integrated circuit (ASIC) that removes a lead sulfate coating generated on an electrode of a lead-acid battery includes: a generation unit that generates, on the basis of a signal extracted from the lead-acid battery, a removal signal of the lead sulfate coating having a peak value of 550 mA to 1000 mA, a pulse width of 5 nsec to 100 nsec, and a frequency of 5 kHz to 50 kHz; and a supply unit that supplies the removal signal generated by the generation unit to the electrode of the lead-acid battery.

A system for integrated data provenance and reconciliation across heterogeneous financial systems, the system includes: a data ingestion module implemented as a hardware interface and configured with high-throughput adapters for structured and unstructured data ingestion from multiple heterogeneous financial subsystems, including bank ledgers, securities trading platforms, risk management databases, and regulatory reporting systems; a schema harmonization processing unit consisting of a dedicated FPGA (Field Programmable Gate Array) structure configured to perform real-time schema alignment, metadata normalization, and semantic mapping across different data models; a lineage tracking processor array implemented on application-specific integrated circuits (ASICs) and configured to encode dataflow transitions into a graph-encoded structure in which each node represents a transformation and each edge represents a dependency; a reconciliation computation cluster unit embodied as a set of graphics processing units (GPUs) configured to execute parallelized reconciliation techniques, anomaly detection routines, and balance verification processes between transformed financial records and reference records; a cryptographic verification unit comprising secure key storage hardware, quantum-resistant encryption modules, and tamper-resistant enclaves configured to generate, anchor, and verify cryptographic signatures for provenance and reconciliation events; a secure storage subsystem configured in a WORM (write-once, read-many) configuration with hardware-based integrity locks for storing immutable provenance and reconciliation logs; a controller with a dedicated visualization processor configured to generate interactive dashboards and drill-down analyses of lineage charts and voting results; and a modular chassis structure consisting of a high-speed backplane interconnect, secure power distribution modules, and tamper-evident enclosures, enabling the system to achieve real-time scalability, hardware-level security, and auditability of financial data flows across heterogeneous infrastructures.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

The invention provides a packaging structure and a manufacturing method thereof. The package structure includes a circuit board, a glass interposer, a first thin film redistribution layer, a second thin film redistribution layer, an application specific integrated circuit component, a photonic integrated circuit component, an electronic integrated circuit component, and an optical fiber component. The glass interposer includes a recess and at least one glass via. The first thin film redistribution layer and the second thin film redistribution layer are respectively arranged on the upper surface and the lower surface of the glass interposer and are electrically connected with the glass through hole. The application-specific integrated circuit component is disposed on and electrically connected to the first thin film redistribution layer. The photonic integrated circuit component is disposed in the recess of the glass interposer and electrically connected to the first thin film redistribution layer. The electronic integrated circuit component is stacked on and electrically connected with the photonic integrated circuit component. The optical fiber assembly is disposed on the glass interposer and optically connected to the photonic integrated circuit assembly. The packaging structure provided by the invention can solve the problems in the prior art, and has lower cost and higher density and performance.

Circuitry and method are described for enabling multiple loads on a differential low voltage differential signaling pair (M-LVDS). A printed circuit board (PCB) contains a M-LVDS driver and leads that route a main channel that carries a differential signal from the driver to an area in which loads are populated. The main channel is split into branches that contain application-specific integrated circuits (ASICs) as the loads. The branches have the same characteristic impedance as the main channel. Filters are disposed in each branch and are coupled between the driver and the ASICs. Each filter is a first order or higher filter. Fewer filters than ASICs are on each branch, with the filters being disposed between the driver and ASICs closest to the driver (with smaller propagation delay). The filters are configured differently at each ASIC input to compensate for the delay.

A radiation detector unit including an interposer configured to electrically connect a pixelated radiation sensor positioned on a front side of the interposer to an application-specific integrated circuit (ASIC) positioned on a back side of the interposer, where the interposer has at least one feature which equalizes the energy resolution (ER) response of edge and center pixel detectors of the pixelated radiation sensor within 10% of one another.

The invention discloses a robot anti-interference integrated circuit system based on multi-sensor fusion, relates to the technical field of automatic control, and aims to solve the problems that in ultra-precision hole machining, due to the fact that complex multi-mode vibration of a boring rod cannot be decoupled and accurately compensated in real time, and the machining precision is high. The system comprises a sensor array which is configured on a key structure of an end effector of an industrial robot and is used for collecting multi-dimensional physical signals related to mechanical vibration in real time; the application-specific integrated circuit is in signal connection with the sensor array and the robot controller, and the application-specific integrated circuit comprises a vibration reconstruction and compensation amount determination module which is used for receiving, fusing and processing multi-dimensional physical signals collected by the sensor array; according to the method, a real-time vibration deformation modal reconstruction and mapping system based on a spatial distributed sensing array and a special integrated circuit is constructed, so that the complex dynamic deformation of the boring rod in the machining process is identified.

A silicon photonic bridge and method of manufacturing an integrated circuit semiconductor package may be provided. The system may include an interposer layer formed from a combination of organic and inorganic materials. The silicon photonic bridge may be embedded within the interposer layer. The silicon photonic bridge may include an electrical integrated circuit (IC) configured to process electrical signals and drive the photonic IC (PIC), and a PIC configured to process optical signals, an optical connector element(s) configured to interface the PIC with fiber and a silicon bridge configured to interface between an ASIC integrated on top of the interposer with the EIC. A silicon photonic bridge may be electrically and optically enabled to convert the electrical signal from the ASIC above the interposer to an optical signal going into fiber, and vice versa. Through-silicon vias (TSVs) may extend through the optical engine.

This application provides a tensor computation method and related apparatus. Through this method, a unified preprocessing is used to obtain the corresponding sign bit, exponent part, and mantissa part for tensors of different data types. Then, through subsequent general exponent accumulation, mantissa multiplication, comparison, shifting, and addition processing, the above unified processing logic can be adapted to the computational needs of different data tensors. Compared with the design idea of ​​equipping each data type with dedicated integrated circuits, this fundamentally eliminates circuit redundancy, thereby reducing chip area, reducing power consumption, and improving flexibility.

A system including multiple processing devices such as application-specific integrated circuits (ASICs). Each processing device is provided with light at one or more wavelengths. Each processing device outputs data, at the wavelength of the optical signal received, to one or more interfaces. Each interface outputs a multiplexed signal containing data from each of the processing devices on a single optic fiber.

A memory device includes a set of memory dies, each memory die of the set of memory dies including a memory array and first control logic operatively coupled to the memory array, and an application-specific integrated circuit (ASIC) including a general-purpose input / output component (GPIO) including at least one digital pad communicably coupled to each memory die of the set of memory dies, and second control logic, operatively coupled to memory, to perform operations related to peak power management (PPM).

The utility model relates to the technical field of MEMS device packaging, and particularly discloses a strip-shaped clamp for an MEMS device, and the MEMS device comprises an MEMS sensor and a special integrated circuit needing to be subjected to an injection molding process; the strip-shaped clamp comprises a frame part and a central part; the central part comprises a plurality of parallel long strip parts which are arranged at intervals; the two ends of each long strip part in the plurality of long strip parts are respectively connected with the frame part so as to form a plurality of strip-shaped openings; the corners of the strip-shaped opening are arranged to be fillets; and under the condition that the MEMS device is arranged below the strip-shaped clamp, the strip-shaped opening is used for exposing an application-specific integrated circuit of the MEMS device so as to carry out an injection molding process, and the strip-shaped part is used for covering an MEMS sensor of the MEMS device. According to the strip-shaped clamp, the cleaning difficulty can be reduced, the manufacturing cost can be reduced, the influence of sputtered resin points in the injection molding process on the performance of the MEMS device can be effectively prevented, and the packaging yield of the MEMS device is effectively improved.

Micromechanical sensor device with: an ASIC substrate (10) with a first front side (VSa) and a first back side (RSa); a rewiring device (20) formed on the first front side (VSa) with a plurality of stacked conductor track levels (LB0, LB1) and insulation layers (I); a MEMS substrate (9) with a second front (VS) and a second back (RS); a first micromechanical functional layer (16) formed above the second front surface (VS); a second micromechanical functional layer (17) formed above the first micromechanical functional layer (16), which is connected to the rewiring device (20) via a bond connection (50); wherein a movable sensor structure (MS) is formed in the second micromechanical functional layer (17) which is anchored on one side to the MEMS substrate (9) via a first anchoring area (17b') formed in the second micromechanical functional layer (17); wherein in the second micromechanical functional layer (17) an electrical connection element formed in a second anchoring area (17d; 17d'; 17d'') is anchored on one side via a contact area (52) of the bond connection (50) on the ASIC substrate (10); and wherein the first anchoring area (17b') and the second anchoring area (17d; 17d'; 17d'') are elastically connected to each other via a spring element (17c) formed in the second micromechanical functional layer (17).

A nano-scale capacitive pressure sensor formed of an array of capacitive pressure cells is disclosed. The capacitive pressure sensor is integrated with an ASIC working as a pressure sensor and a PUF. Each of capacitive pressure cells is a hermetically sealed cavity and includes a first stationary conductive membrane and a second conductive membrane that deflects due to a force (pressure change) applied on the array of capacitive pressure sensor cells. A method of manufacturing the nano-scale capacitive pressure sensor is also disclosed.

An ultrasound imaging probe arranged to perform receive beamforming operation from ultrasound signals received by said probe, wherein said probe comprises: - a two-dimensional array of transducer elements wherein said elements are arranged to receive said ultrasound signals; - an Application Specific Integrated Circuit, ASIC, in electric connection with said two-dimensional array for receiving said ultrasound signals, and wherein said ASIC is configured to perform beamforming on said received signals; wherein said array of transducer elements is arranged in a plurality of groups of transducer elements; wherein said ASIC is arranged for performing a first stage beamforming on each of said plurality of groups, to generate a first stage beamformed signal for a respective group; wherein said ASIC is arranged for performing a second stage beamforming on each of said plurality groups, to generate a second stage beamformed signal for forwarding said second stage beamformed signals; and wherein both said first and second stage beamforming are performed in the analog domain, for generating an analog first stage beamformed signal and analog second stage beamformed signal, respectively for forwarding to an ultrasound system for being further processed and / or being displayed.

A state estimation method for mobile robot navigation is provided which includes: step S1, initializing the processing module, and then controlling the field-programmable gate array to obtain measurement values of a moment k collected by the inertial measurement unit and the localization apparatus in a constant sampling period; step S2, controlling the application-specific integrated circuit to send the measurement values to the processing module; step S3, controlling the processing module to, based on the measurement values, sequentially perform vector padding, additional inertial vector acquisition, normalization processing, alignment error computation, filter measurement value computation, bias estimation value computation, velocity estimation value computation, pose estimation value computation and orthogonalization processing to obtain state estimation values of the moment k; step S4, controlling the processing module to send the state estimation values to the human-machine interface for visual display.

An RF device may include an RF antenna, and an ASIC downstream from the RF antenna. The ASIC may include ADCs configured to generate replica digitized input signals, a DSP core downstream from the ADCs and having first complex coefficient multipliers, first band pass filters respectively coupled to the first complex coefficient multipliers, and a summer downstream from the first band pass filters. The ASIC may also include DACs configured to generate analog output signals, and a feedback loop coupled between the DACs and the ADCs. The RF device may further include a processor configured to control the first complex coefficient multipliers and associated delay circuits.

To provide a method and system for ultrasound imaging and beamforming using a novel matrix array of transducer elements.SOLUTION: The received signal of each transducer array element is amplified. The amplified receive signal of each transducer array element is digitized. Delays and weights are applied to the amplified and digitized received signals. The amplified, digitized, delayed, and weighted receive signals are summed across all transducer elements of the matrix array to form a dynamically focused receive beam. An applicationspecificintegratedcircuit (ASIC) integrated with a matrix array of transducer elements performs such steps.SELECTED DRAWING: Figure 1

Encryption system with an application-specific integrated circuit (ASIC) which has a permanent memory for the non-volatile storage of the operating system (OS) of a processor and software modules for encrypting the data memory of the processor and which has a hardware-implemented encryption algorithm, characterized in that a security module (SM) is integrated in the ASIC for autonomous booting of the operating system (OS), consisting of: - a symmetric cryptosystem (SK) for processing symmetric keys, - an asymmetric cryptosystem (AK) for the use of public and private keys, - a module for generating cryptographic hash functions (KH), - a module for the secure exchange of keys using hardware-implemented key exchange protocols (SP), - a key storage (SS) for the secure storage of root keys (WS), which are protected by appropriate measures in the physical structures of the ASIC and - a key management system (SMS) for the secure introduction of authenticated-encrypted key packets, and that the security module (SM) communicates with a central processing unit (CPU) via a communication interface (CS1), and that the central processing unit (CPU) communicates with at least one internal storage (IS) and one external storage (ES), as well as with at least one internal persistent storage (IP) and one external persistent storage (EP), such that the operating system (OS) is loaded by a second-stage bootloader (SSB) stored in the external persistent storage (EP), and then the operating system (OS) loads the applications, the second-stage bootloader (SSB) itself being decrypted and loaded by a first-stage bootloader (FSB) stored in the internal persistent storage (IP), and a public key (PUBOS) to verify the operating system (OS).and a symmetric key (KOS) to decrypt the operating system (OS), and that the contents of the internal memory (IS) and the external memory (ES) are decrypted by the security module (SM) during read accesses by the central management unit (CMU) or other modules integrated on the ASIC, and re-encrypted during write accesses by the same.

The invention discloses an SIFT (Scale Invariant Feature Transform) algorithm hardware circuit implementation, which optimizes the hardware circuit implementation of an original SIFT algorithm, and solves the problems of slow operation of the SIFT algorithm and large resource consumption when the SIFT algorithm is deployed on an FPGA (Field Programmable Gate Array). According to the specific implementation scheme, the method comprises the steps that a one-layer six-group Gaussian pyramid is built, and an independent precalculated 21 * 21 Gaussian filtering kernel is used in each group; extreme points of three adjacent groups of differential pyramids are detected by adopting a threshold method, and edge response points are eliminated; a CORDIC algorithm is adopted to calculate the gradient direction and amplitude of a Gaussian image where the feature points are located, and a 16-row 16-column calculation result is output for gradient histogram statistics and descriptor generation; and normalization of a 128-dimensional descriptor is realized by using a single divider. The method has the advantages of low resource consumption, high real-time performance and the like, and is suitable for scenes, such as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit) and the like, needing hardware acceleration of the SIFT algorithm.

A specialized integrated circuit for artificial neural networks is integrated with high bandwidth memory. The neural network includes a systolic array of interconnected processing elements, including upstream processing elements and downstream processing elements. Each processing element includes a pair of input / output ports for concurrent forward and backward propagation. The processing elements can be used for convolution, in which case the pair of input / output ports can support fast and efficient scanning of a kernel over activations.

A diagnostic Electrochemical Impedance Spectroscopy (EIS) procedure is applied to measure values of impedance-related parameters for one or more sensing electrodes. The parameters may include real impedance, imaginary impedance, impedance magnitude, and / or phase angle. The measured values of the impedance-related parameters are then used in performing sensor diagnostics, calculating a highly-reliable fused sensor glucose value based on signals from a plurality of redundant sensing electrodes, calibrating sensors, detecting interferents within close proximity of one or more sensing electrodes, and testing surface area characteristics of electroplated electrodes. Advantageously, impedance-related parameters can be defined that are substantially glucose-independent over specific ranges of frequencies. An Application Specific Integrated Circuit (ASIC) enables implementation of the EIS-based diagnostics, fusion algorithms, and other processes based on measurement of EIS-based parameters.

A spinal cord machine interface (SCMI) device is described. The SCMI includes an intraspinal probe, composed of at least one implantable shank. The implantable shank include a sensing electrode array and a stimulating electrode array. The SCMI also includes an application specific integrated circuit (ASIC). The ASIC is configured to detect action potentials from a patient's spine using the sensing electrode array and to stimulate a target action of the patent using the stimulating electrode array according to a location of the action potentials in a spinal cord and a learned mapping of the location of the action potentials to the target action.

A memory device comprises a storage component for Logic Built-In Self-Test (LBIST) pattern seed information and an In-System Test (IST) controller. The IST controller receives a host command to initiate self-test, loads pattern seed information, triggers test execution, and provides status information to the host. The storage component may be random access memory, allowing dynamic modification of test patterns. This on-demand LBIST architecture enables fault detection during device operation and allows flexible test pattern generation that can adapt to changing requirements.