296 results about "Application-specific integrated circuit" patented technology

Blockchain environments may mix-and-match different encryption, difficulty, and / or proof-of-work schemes when mining blockchain transactions. Each encryption, difficulty, and / or proof-of-work scheme may be separate, stand-alone programs, files, or third-party services. Blockchain miners may be agnostic to a particular coin's or network's encryption, difficulty, and / or proof-of-work schemes, thus allowing any blockchain miner to process or mine data in multiple blockchains. GPUs, ASICs, and other specialized processing hardware components may be deterred by forcing cache misses, cache latencies, and processor stalls. Hashing, difficulty, and / or proof-of-work schemes require less programming code, consume less storage space / usage in bytes, and execute faster. Blockchain mining schemes may further randomize byte or memory block access, further improve cryptographic security.

The invention relates to the technical field of real-time kernel performance testing of special chips, in particular to a special chip real-time performance evaluation method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: (1) aiming at a real-time system on an ASIC (Application Specific Integrated Circuit) chip, setting an external interrupt source and an interrupt service program through a hardware interrupt controller; (2) two tasks with the same priority are created, scheduling of the tasks is achieved through time slice rotation, and a real dynamic load scene is simulated; (3) configuring an external FPGA (Field Programmable Gate Array) to generate a square wave signal to trigger external interruption of the ASIC chip, receiving a feedback signal, and connecting the FPGA and the GPIO through an external physical connecting line to form a hardware interruption triggering-response closed loop; and (4) realizing nanosecond timestamp capture through a counter built in the FPGA, acquiring time delay data, calculating interrupt response time, and transmitting the time delay data to a PC (Personal Computer) through a UART (Universal Asynchronous Receiver / Transmitter) to calculate a maximum value, a minimum value, an average value and a data jitter range of test data. The method can effectively solve the problem that the traditional internal closed-loop test cannot reflect the real interruption randomness and the dynamic load.

The invention discloses a finger-storage-multiply-accumulate three-stacked floating-point number in-memory computing system, and belongs to the field of application-specific integrated circuit design. According to the system, a three-stack type floating-point number calculation framework is designed, a pointing shift and mantissa multiply-accumulate module is designed, and floating-point number multiply-accumulate calculation of global pointing is supported. Compared with a traditional parallel floating-point multiply-accumulate circuit, the parallel floating-point multiply-accumulate circuit has the advantages that a calculation process of global alignment shifting and mantissa multiply-accumulate in sequence and a three-stack type calculation framework are adopted, similar calculation precision is achieved with smaller hardware overhead, low hardware overhead and high calculation precision are both considered, and the comprehensive performance of the calculation framework and the circuit is improved.

The invention provides an OIO core particle and an AI computing cluster, which are applied to the technical field of photoelectric transmission, and the OIO core particle comprises an optical chip, an electric chip and a micro-control chip or a micro-control application-specific integrated circuit. An optical chip, an electric chip and a control unit are packaged into an OIO core particle, the core particle works independently as an OIO, and the bandwidth and linearity of a system are improved by adopting an analog light and electric equalization technology in the optical chip and the electric chip. And the core particles are applied to a Scale-up network in the node and are used for interconnection between GPUs (Graphics Processing Unit). Compared with a copper cable interconnection scheme, the method has the advantages that the interconnection distance can be greatly increased, and the scale of a Scale-up network for GPU interconnection is expanded; compared with the existing optical module interconnection scheme, the optical module interconnection method has the advantages of low time delay, low power consumption, high bandwidth density and high reliability; the chip particle interconnection can adapt to the diversity requirements of AI chips and systems, and can be integrated into their systems by clients according to their own requirements.

In one embodiment, a method may receive a request to upgrade software for a switch. The method may use an application-specific integrated circuit (ASIC) simulator to generate a digital twin to store a first image and a first configuration of the switch. The method may use the digital twin to generate a second image and a second configuration by replaying the first configuration on the first image. The method may communicate the second image and the second configuration from the digital twin to an ASIC memory of an ASIC associated with the switch by applying batch direct memory access (DMA).

This disclosure describes techniques for an isolated Root of Trust (RoT) component of a System on Chip (SoC), such as an SoC associated with a networking-related application, to: (i) enforce access to one or more protected addresses associated with the SoC using a secure communication channel, (ii) limit access to one or more restricted addresses to authorized external devices, and / or (iii) detect an operational environment within which the SoC operates based on access rates associated with special addresses associated with the SoC and modify operation of the SoC based on the detected operational environment. The RoT component may be implemented as a dedicated security subsystem with an isolated processor and memory regions that are inaccessible to the rest of the SoC.

This disclosure describes techniques for an isolated Root of Trust (RoT) component associated with a system-on-chip (SoC), such as a networking-related SoC, to enforce a persona on the SoC and / or control the operation of the SoC based on the enforced persona. In some cases, the RoT component is configured to: (i) determine a persona associated with the SoC based on firmware associated with the RoT component that defines a persona associated with the SoC, (ii) modifies one or more configurations associated with the SoC based on the defined persona, (iii) modifies the operation of the SoC based on determining that the SoC is operating in an operational environment that is different from the operational environment associated with the defined persona, and / or (iv) switches between two or more available personas associated with the SoC based on determining a change in an operational environment associated with the operation of the SoC.

A system and method for deploying machine learning models with consistent fixed-point arithmetic processing. A computing device in a vehicle receives a trained machine learning model that was trained using training images processed with fixed-point arithmetic operations. The computing device receives images from a camera and processes the received images using fixed-point arithmetic operations that are consistent with those used during training. The machine learning model is executed using the processed images to detect objects such as vehicles, pedestrians, persons on bikes, stop lights, or stop signs. The computing device may comprise specialized hardware including a graphics processing unit (GPU), digital signal processing hardware decoder, or single-purpose hardware decoder such as an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The system may generate alerts or determine vehicle operation changes based on detected objects, and may operate in surveillance mode when the vehicle is parked.

A sensor module for Raman spectroscopy includes a sensor package which encloses an application specific integrated circuit (ASIC), a light emitter arrangement, a light detector arrangement and a filter arrangement. The light emitter arrangement is electrically connected to the ASIC and operable to emit light with multiple excitation wavelengths to excite Raman scattering in an external probe to be placed outside of the sensor module. The light detector arrangement is operable to generate sensor signals from incident light emitted back from the external probe due to the Raman scattering. The filter arrangement is operable to filter the incident light according to a target passband. The ASIC is operable to drive the light emitter arrangement at the excitation wavelengths to shift a Raman spectral band of the external probe into the passband of the filter arrangement.

The invention discloses a current sensor, a current detection method and a chip. The current sensor comprises a diversion module, a magnetic sensing module, an application-specific integrated circuit module and a magnetic field compensation module, the diversion module is configured to introduce and export a detection current, and the application-specific integrated circuit module is configured to drive the magnetic field compensation module to drive an electric signal to operate according to the detection current; the application-specific integrated circuit module is further configured to output a driving electric signal under the condition that the first magnetic field component of the diversion module and the second magnetic field component of the magnetic field compensation module reach a balance state at the magnetic sensing module. According to the current sensor, the magnetic sensing module is adopted to sense the magnetic field generated by the detection current, the circuit signal output by the magnetic sensing module based on the change of the magnetic field is processed through the application-specific integrated circuit, and the magnetic field compensation module is controlled according to the processing result to form the balanced magnetic field so as to realize the closed-loop detection of the detection current. Therefore, the accuracy of current detection is improved, and the null drift phenomenon of the current sensor is improved.

Described herein is a novel approach that leverages a 3D stacked die complex with an active optical interposer integrated with an I / O chiplet including high-speed serializer / deserializer (SerDes). By integrating silicon in this way, shoreline constraints are eliminated, allowing for the SerDes macros to be placed virtually anywhere on the I / O chiplet. The photonic-based interconnects described herein improve upon conventional approaches based on co-packaged optics (CPO), Linear-drive Pluggable Optics (LPO) and copper-based solutions in terms of bandwidth and power consumption. The interconnects described herein rely on photonic-electronic packages in which a PIC provides processing units (e.g., XPU), electronic switching chips or other types of application-specific integrated circuits (ASIC) with access to optical fiber-based networks while multiple SerDes provide high-speed serialization and deserialization.

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.

An artificial intelligence-based business management system for real-time decision optimization, consisting of: a data acquisition unit configured to ingest structured, semi-structured and unstructured data streams from enterprise resource planning (ERP) systems, customer relationship management (CRM) platforms, Internet of Things (IoT) devices, external market feeds and financial transaction systems, encrypting, timestamping and verifying the data prior to further processing; a graph processing unit that is communicatively connected to the said acquisition layer, wherein the unit is configured to encode heterogeneous data into dynamic graph structures comprising nodes representing business entities and edges representing transaction or relationship dependencies, wherein the unit is further configured to perform deduplication, metadata tagging and real-time data synchronization; a decision optimization unit operationally linked to the graph processing unit, wherein the decision optimization unit includes modules for reinforcement learning, modules for Bayesian optimization and multi-objective solvers configured to simulate multiple alternative decision paths and select an optimal path based on performance indicators such as cost efficiency, resource utilization, customer satisfaction and risk minimization; a real-time inference control unit with specialized hardware cores, including at least one graphics processing unit (GPU), a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), wherein the accelerator performs inference tasks of the decision optimization unit with a latency in the millisecond range; a diagnostic processing unit configured to generate causal diagrams, feature mapping maps, and interpretable result summaries according to the optimization outputs; and a control interface unit configured to transmit optimized decisions to process controls within the enterprise, robot actuators, planning systems or interactive dashboards, with the interface supporting bidirectional communication for higher-level interventions, error feedback and triggers for re-optimization.

[Problem] An object is to provide a lead sulfate coating removal device that has low power consumption and does not damage an electrode of a lead-acid battery.[Solution]A lead sulfate coating removal device implemented by an application specific integrated circuit (ASIC) that removes a lead sulfate coating generated on an electrode of a lead-acid battery includes: a generation unit that generates, on the basis of a signal extracted from the lead-acid battery, a removal signal of the lead sulfate coating having a peak value of 550 mA to 1000 mA, a pulse width of 5 nsec to 100 nsec, and a frequency of 5 kHz to 50 kHz; and a supply unit that supplies the removal signal generated by the generation unit to the electrode of the lead-acid battery.

A system for integrated data provenance and reconciliation across heterogeneous financial systems, the system includes: a data ingestion module implemented as a hardware interface and configured with high-throughput adapters for structured and unstructured data ingestion from multiple heterogeneous financial subsystems, including bank ledgers, securities trading platforms, risk management databases, and regulatory reporting systems; a schema harmonization processing unit consisting of a dedicated FPGA (Field Programmable Gate Array) structure configured to perform real-time schema alignment, metadata normalization, and semantic mapping across different data models; a lineage tracking processor array implemented on application-specific integrated circuits (ASICs) and configured to encode dataflow transitions into a graph-encoded structure in which each node represents a transformation and each edge represents a dependency; a reconciliation computation cluster unit embodied as a set of graphics processing units (GPUs) configured to execute parallelized reconciliation techniques, anomaly detection routines, and balance verification processes between transformed financial records and reference records; a cryptographic verification unit comprising secure key storage hardware, quantum-resistant encryption modules, and tamper-resistant enclaves configured to generate, anchor, and verify cryptographic signatures for provenance and reconciliation events; a secure storage subsystem configured in a WORM (write-once, read-many) configuration with hardware-based integrity locks for storing immutable provenance and reconciliation logs; a controller with a dedicated visualization processor configured to generate interactive dashboards and drill-down analyses of lineage charts and voting results; and a modular chassis structure consisting of a high-speed backplane interconnect, secure power distribution modules, and tamper-evident enclosures, enabling the system to achieve real-time scalability, hardware-level security, and auditability of financial data flows across heterogeneous infrastructures.

The present invention provides systems and methods for utilizing an application-specific integrated circuit (ASIC) for an artificial neural network connected to the memory, the ASIC comprising: a plurality of neurons organized in an array, wherein each neuron comprises a register, a processing element and at least one input, and a plurality of synaptic circuits, each synaptic circuit including a memory for storing a synaptic weight, wherein each neuron is connected to at least one other neuron via one of the plurality of synaptic circuits, wherein the array is configured to analyze said business sale transaction information trained on historical datasets relating to asset utilization, wherein the AI / ML categorization engine makes a prediction regarding the most efficient use(s) of an asset.

The present disclosure describes a system and method for preempting a long-running process with a higher priority process in a machine learning system, such as a hardware accelerator. The machine learning hardware accelerator can be a multi-chip system including semiconductor chips that can be application-specific integrated circuits (ASIC) designed to perform machine learning operations. An ASIC is an integrated circuit (IC) that is customized for a particular use.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

The invention provides a packaging structure and a manufacturing method thereof. The package structure includes a circuit board, a glass interposer, a first thin film redistribution layer, a second thin film redistribution layer, an application specific integrated circuit component, a photonic integrated circuit component, an electronic integrated circuit component, and an optical fiber component. The glass interposer includes a recess and at least one glass via. The first thin film redistribution layer and the second thin film redistribution layer are respectively arranged on the upper surface and the lower surface of the glass interposer and are electrically connected with the glass through hole. The application-specific integrated circuit component is disposed on and electrically connected to the first thin film redistribution layer. The photonic integrated circuit component is disposed in the recess of the glass interposer and electrically connected to the first thin film redistribution layer. The electronic integrated circuit component is stacked on and electrically connected with the photonic integrated circuit component. The optical fiber assembly is disposed on the glass interposer and optically connected to the photonic integrated circuit assembly. The packaging structure provided by the invention can solve the problems in the prior art, and has lower cost and higher density and performance.

Circuitry and method are described for enabling multiple loads on a differential low voltage differential signaling pair (M-LVDS). A printed circuit board (PCB) contains a M-LVDS driver and leads that route a main channel that carries a differential signal from the driver to an area in which loads are populated. The main channel is split into branches that contain application-specific integrated circuits (ASICs) as the loads. The branches have the same characteristic impedance as the main channel. Filters are disposed in each branch and are coupled between the driver and the ASICs. Each filter is a first order or higher filter. Fewer filters than ASICs are on each branch, with the filters being disposed between the driver and ASICs closest to the driver (with smaller propagation delay). The filters are configured differently at each ASIC input to compensate for the delay.

The invention relates to a cloud mobile phone terminal decoding chip architecture and a collaborative optimization method thereof, processing equipment and a storage medium, the chip architecture adopts an ASIC (Application Specific Integrated Circuit) chip and comprises a video decoding module, a communication interface module, a touch processing module, a dynamic power management module and a communication protocol switching module; the video decoding module is used for performing motion compensation processing and entropy decoding on input video data and determining a power gating driving signal of the dynamic power management module; the touch control processing module is used for carrying out wavelet processing and Kalman filtering processing on an input touch control signal; the dynamic power management module is used for dynamically adjusting the power supply voltage and frequency according to the power consumption information and cutting off power supply according to the power gating driving signal and / or the detected temperature; the communication protocol switching module is used for controlling switching of communication protocols; the communication interface module is used for determining power consumption information; and sending the decoded video data and the filtered touch signal to the cloud. The method and the device can be widely applied to the technical field of cloud mobile phones.

The present invention relates to an integrated circuit (22), for example an application-specific integrated circuit, for connecting a headlight light source module (21) of a vehicle to a bus (3) of the vehicle, wherein - the circuit has an interface (221) for connection to the bus (3) and that this first interface (221) is an Ethernet interface and - the circuit has at least one interface (222) for connection to the headlight light source module (21) and that this at least one second interface (222) is a video interface.

A radiation detector unit including an interposer configured to electrically connect a pixelated radiation sensor positioned on a front side of the interposer to an application-specific integrated circuit (ASIC) positioned on a back side of the interposer, where the interposer has at least one feature which equalizes the energy resolution (ER) response of edge and center pixel detectors of the pixelated radiation sensor within 10% of one another.

The invention discloses a robot anti-interference integrated circuit system based on multi-sensor fusion, relates to the technical field of automatic control, and aims to solve the problems that in ultra-precision hole machining, due to the fact that complex multi-mode vibration of a boring rod cannot be decoupled and accurately compensated in real time, and the machining precision is high. The system comprises a sensor array which is configured on a key structure of an end effector of an industrial robot and is used for collecting multi-dimensional physical signals related to mechanical vibration in real time; the application-specific integrated circuit is in signal connection with the sensor array and the robot controller, and the application-specific integrated circuit comprises a vibration reconstruction and compensation amount determination module which is used for receiving, fusing and processing multi-dimensional physical signals collected by the sensor array; according to the method, a real-time vibration deformation modal reconstruction and mapping system based on a spatial distributed sensing array and a special integrated circuit is constructed, so that the complex dynamic deformation of the boring rod in the machining process is identified.

A silicon photonic bridge and method of manufacturing an integrated circuit semiconductor package may be provided. The system may include an interposer layer formed from a combination of organic and inorganic materials. The silicon photonic bridge may be embedded within the interposer layer. The silicon photonic bridge may include an electrical integrated circuit (IC) configured to process electrical signals and drive the photonic IC (PIC), and a PIC configured to process optical signals, an optical connector element(s) configured to interface the PIC with fiber and a silicon bridge configured to interface between an ASIC integrated on top of the interposer with the EIC. A silicon photonic bridge may be electrically and optically enabled to convert the electrical signal from the ASIC above the interposer to an optical signal going into fiber, and vice versa. Through-silicon vias (TSVs) may extend through the optical engine.

This application provides a tensor computation method and related apparatus. Through this method, a unified preprocessing is used to obtain the corresponding sign bit, exponent part, and mantissa part for tensors of different data types. Then, through subsequent general exponent accumulation, mantissa multiplication, comparison, shifting, and addition processing, the above unified processing logic can be adapted to the computational needs of different data tensors. Compared with the design idea of ​​equipping each data type with dedicated integrated circuits, this fundamentally eliminates circuit redundancy, thereby reducing chip area, reducing power consumption, and improving flexibility.

A system including multiple processing devices such as application-specific integrated circuits (ASICs). Each processing device is provided with light at one or more wavelengths. Each processing device outputs data, at the wavelength of the optical signal received, to one or more interfaces. Each interface outputs a multiplexed signal containing data from each of the processing devices on a single optic fiber.

A memory device includes a set of memory dies, each memory die of the set of memory dies including a memory array and first control logic operatively coupled to the memory array, and an application-specific integrated circuit (ASIC) including a general-purpose input / output component (GPIO) including at least one digital pad communicably coupled to each memory die of the set of memory dies, and second control logic, operatively coupled to memory, to perform operations related to peak power management (PPM).

The utility model relates to the technical field of MEMS device packaging, and particularly discloses a strip-shaped clamp for an MEMS device, and the MEMS device comprises an MEMS sensor and a special integrated circuit needing to be subjected to an injection molding process; the strip-shaped clamp comprises a frame part and a central part; the central part comprises a plurality of parallel long strip parts which are arranged at intervals; the two ends of each long strip part in the plurality of long strip parts are respectively connected with the frame part so as to form a plurality of strip-shaped openings; the corners of the strip-shaped opening are arranged to be fillets; and under the condition that the MEMS device is arranged below the strip-shaped clamp, the strip-shaped opening is used for exposing an application-specific integrated circuit of the MEMS device so as to carry out an injection molding process, and the strip-shaped part is used for covering an MEMS sensor of the MEMS device. According to the strip-shaped clamp, the cleaning difficulty can be reduced, the manufacturing cost can be reduced, the influence of sputtered resin points in the injection molding process on the performance of the MEMS device can be effectively prevented, and the packaging yield of the MEMS device is effectively improved.