31 results about "Circuit performance" patented technology

This disclosure provides a state switching method, apparatus, and electronic device. The state switching method includes: generating and maintaining a state switching signal when a preset state switching condition is met; switching the state of a target object using the state switching signal; calculating the time interval between the current time and the end time of a synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal; and ending the state switching signal when the time interval meets a preset condition, thus completing the state switching of the target object; the preset condition includes the time interval being an even multiple of a first clock cycle. This embodiment ensures that the output signal of the target object after state switching is synchronized with the synchronization alignment signal, solving the problem of timing disorder and improving circuit performance.

The utility model relates to verification fixture, specifically relates to a general integrated circuit performance verification fixture, including PCB board, and the product fixed base of setting in the middle part of PCB board upper surface, still be equipped with a plurality of groups with product fixed base pin number same's BNC joint, single -pole double -throw switch, banana plug and equipment welding tray on PCB board, in any group BNC joint, single -pole double -throw switch, banana plug and equipment welding tray, single -pole double -throw switch's common end is linked with the pin of product fixed base, and equipment welding tray is connected between single -pole double -throw switch's common end and the pin of product fixed base, single -pole double -throw switch's two signal ends are linked with BNC joint, banana plug respectively. Compared with prior art integrated circuit performance verification mode, the utility model can be applicable to the performance verification of common multiple integrated circuits, need not design corresponding integrated circuit performance verification fixture for specific kind of integrated circuit, and the verification cost is reduced.

This invention relates to the field of three-dimensional spatial circuit manufacturing technology, specifically disclosing an auxiliary testing device and performance testing method for three-dimensional spatial circuits. The device includes auxiliary components designed and manufactured based on the substrate prefabrication structure in an integrated three-dimensional spatial circuit product, and a base assembly for fixing and supporting the auxiliary components. The auxiliary components include a tombstone assembly, and two blocks located on either side of the tombstone assembly and connected to it. The tombstone assembly includes multiple sets of tombstone structures connected in sequence; each set of tombstone structures is equipped with a tombstone body. This invention enables the testing of the circuit performance on the surface of the three-dimensional spatial circuit without cutting or damaging the tombstone bodies that may obstruct the circuit, obtaining the required circuit fabrication process parameters, reducing testing costs, and improving the accuracy of circuit fabrication.

This application provides a method and chip for dicing and splicing a chip layout, relating to the field of semiconductor technology. It can improve the circuit performance in a chip, thereby increasing the yield and reliability of the spliced ​​chip. The method for dicing and splicing a chip layout includes: virtually dividing the chip layout according to its dimensions to determine at least one virtual dividing line; determining a cutting line based on the virtual dividing line and the structural patterns on both sides of the virtual dividing line, wherein the cutting line is used to divide the chip layout into at least two sub-layouts, the cutting line does not overlap with the structural patterns on the chip layout, and the cutting line is located in the interval region between adjacent structural patterns; preparing photomasks based on the cutting line and the at least two sub-layouts, each sub-layout corresponding to one photomask; and performing sequential photolithography on the wafer using the at least two photomasks corresponding to the chip layout, one photomask corresponding to one photolithography process.

Embodiments of the present application provide a state switching method and apparatus, and an electronic device. The state switching method comprises: when a preset state switching condition is satisfied, generating and maintaining a state switching signal; using the state switching signal to perform state switching on a target object; calculating a time interval between a current moment and an ending moment of a synchronous alignment signal, wherein the synchronous alignment signal is a signal applied to the target object and earlier than the state switching signal; and when the time interval satisfies a preset condition, ending the state switching signal to complete state switching of the target object, wherein the preset condition comprises that the time interval is an even multiple of a first clock period. The solution of the embodiments synchronizes the output signal of the target object after state switching is performed with the synchronous alignment signal, thereby solving the problem of timing sequence disorder, and improving the circuit performance.

The embodiment of the application discloses a kind of power switch drive circuit and power converter, it is related to switching power converter technical field.The power switch drive circuit includes: electromagnetic interference (EMI) detection circuit, first asynchronous sampling circuit, second asynchronous sampling circuit, comparison circuit, off-chip control circuit, first gate drive circuit, second gate drive circuit;EMI detection circuit, first / second asynchronous sampling circuit, comparison circuit, off-chip control circuit, first gate drive circuit are sequentially connected, finally through adjusting first gate drive signal, the EMI performance of adjusting power converter is realized.The circuit carries out on-chip EMI detection to switching voltage signal by EMI detection circuit, and compares the EMI detection result under different circuit states, realizes by off-chip control circuit dynamic adjustment gate drive circuit to keep the best circuit performance, to ensure high efficiency and high energy density, while, wide-area EMI suppression is realized, and the robustness and industrial applicability of circuit are improved.

The application provides a band gap reference voltage source circuit, an electronic circuit and an electronic device. Through a compensation submodule, a first current in a zero temperature condition can be determined according to a zero temperature resistor, a second current can be determined according to a positive temperature current generated in the circuit, and a compensation voltage of the circuit can be determined according to the first current and the second current, so as to reduce the influence of temperature drift on the performance of the circuit by eliminating high-order temperature drift terms. In addition, through a ripple suppression module, the voltage clamping of the compensation submodule is adjusted, the amplitude of the reference voltage is limited, the suppression of signals generated by unnecessary devices in the circuit is realized in a negative feedback manner, the ripple suppression ratio parameter of the circuit is improved, and the comprehensive performance of the circuit is improved.

The utility model discloses a compatible plug -in capacitor's packaging structure, including PCB board and the packaging area of setting on the PCB board, be equipped with n mutually overlapping setting's packaging unit in the packaging area, every packaging unit all with a plug -in capacitor adaptation, wherein, n is the integer greater than or equal to 2. Such design, in the product research and development process, can test the influence of the plug -in capacitor of different capacitance value to circuit performance to find the most adaptive plug -in capacitor parameter, need not constantly replace PCB board or carry out complex reformation to PCB board, the packaging structure of compatible plug -in capacitor that the application provides, and test personnel only need to install the plug -in capacitor of different capacitance value in corresponding packaging unit, need not make any change to PCB board layout, wiring etc. design, can quickly complete plug -in capacitor replacement and test, has improved the efficiency of test greatly, makes the research and development process can advance quickly.

The application discloses an anti-radiation carbon nanotube transistor, CMOS device, manufacturing method and integrated circuit. The anti-radiation carbon nanotube transistor comprises an anti-radiation substrate with a first surface; a gate electrode formed on the first surface; a gate dielectric layer formed on the gate electrode; a carbon nanotube channel layer formed on the gate dielectric layer; a source electrode and a drain electrode formed on the gate dielectric layer and arranged at intervals, the source electrode and the drain electrode being connected to the carbon nanotube channel layer respectively; and a passivation layer or a doped layer formed on the carbon nanotube channel layer and covering at least the carbon nanotube channel layer. The anti-radiation carbon nanotube transistor, CMOS device, manufacturing method and integrated circuit can solve the technical problems of insufficient anti-radiation capability of the carbon nanotube CMOS device and imbalance of circuit performance under radiation in the prior art.

The invention discloses a method, a device and equipment for predicting circuit performance of a transistor, relates to the technical field of computer aided design of integrated circuits and semiconductor devices, and aims to solve the problem that an existing compact model constructed based on TCAD simulation is difficult to accurately map real process fluctuation of a field effect transistor. And circuit-level power consumption and performance prediction results are not accurate. The method comprises the following steps: acquiring TCAD simulation data and actual measurement data of the field effect transistor; training a neural network model according to the TCAD simulation data to obtain a TCAD prior model; according to the measured data, a transfer learning method is adopted to carry out fine tuning on the TCAD prior model, and a target prediction model is obtained; and performing circuit-level simulation on the field effect transistor based on a Verilog-A compact model to obtain a circuit-level power consumption and performance prediction result. The method for predicting the circuit performance of the transistor is used for improving the circuit-level power consumption and the performance prediction result of the field effect transistor.

The utility model relates to three operational amplifier subtraction operation circuit device, its circuit actual object can adopt high -quality PCB welding technology to integrate each component and its connecting circuit, to ensure that circuit connection is stable and reliable, solve the time -consuming and labor -intensive problem when student builds the circuit, form the flexible and efficient special experimental circuit board of wiring. A plurality of test points are reserved on the circuit, can be convenient for student to use multimeter, oscilloscope and other instruments real -time measurement each node's voltage, current and the like parameter, be convenient for observation circuit dynamic change, and the design of gain regulator and connector makes student can conveniently adjust the gain of circuit, studies the influence of gain on circuit performance, simultaneously, this design also is convenient for teacher to demonstrate on the classroom, through the regulation gain, intuitively shows the influence of gain on output signal amplitude, deepens the understanding of gain concept of student, improves teaching use efficiency.

The utility model discloses a kind of welding auxiliary tools of MOS tube and inverter board, it is related to electronic component welding technical field, including fixed seat, detachable structure is set on fixed seat, the detachable connection of inverter board and fixed seat can be realized, multiple placing grooves are symmetrically arranged at both ends of fixed seat, MOS tube is arranged in placing groove, and the pin of MOS tube passes through inverter board;This kind of welding auxiliary tools of MOS tube and inverter board can realize the accurate positioning of multiple MOS tubes on inverter board simultaneously, to avoid the deviation of welding position in welding process, ensure welding quality and circuit performance, and can weld multiple MOS tubes in single time, improve welding efficiency.

This invention discloses a current control method and apparatus to address the problem in existing three-arm bridge topology circuits where high current generation damages switching transistors and reduces circuit performance. The method, applied to a three-arm bridge topology circuit, first acquires the input voltage information at the AC input terminal and the output voltage information at the AC output terminal of the three-arm bridge topology circuit. Then, based on the input and output voltage information, it determines that the voltage at the AC input terminal is out of phase with the voltage at the AC output terminal. Finally, according to a preset current value, it reduces the current values ​​of the second and fifth switching transistors, thereby preventing damage to the switching transistors from high current and improving the reliability of the three-arm bridge topology circuit.

The present disclosure discloses a design method and device of a radio frequency integrated circuit, a storage medium and an electronic device, the design method comprising: obtaining circuit schematic diagram information and design indexes of a radio frequency circuit, generating candidate active circuit parameters and candidate passive circuit layout based on the design indexes, and constructing an overall radio frequency circuit layout. The overall radio frequency circuit layout is subjected to design rule verification, layout and schematic diagram consistency verification, and parasitic parameter extraction; a net list of the overall radio frequency circuit is generated based on the parasitic parameters, and simulation evaluation is performed to obtain circuit performance, and it is judged whether the circuit performance meets the design indexes; if not, the candidate active circuit parameters and the candidate passive circuit layout are iteratively optimized through an optimization algorithm until the circuit performance meets the design indexes; if yes, a radio frequency circuit design scheme corresponding to a circuit performance optimal solution or a radio frequency circuit design scheme set containing a Pareto frontier solution is output. The present disclosure realizes closed-loop collaborative optimization of active parameters and passive layout, and improves performance reliability.

This invention relates to the field of integrated circuit manufacturing, and particularly to a shape-aware OPC method, apparatus, device, and storage medium. The shape-aware OPC method provided by this invention acquires design intent data and a layout to be processed; determines sensitive patterns in the layout to be processed based on the design intent data; and performs TOPC processing on the sensitive and non-sensitive patterns using DML partitions of different sizes to obtain TOPC mask correction data; the DML partition size of the sensitive patterns is smaller than that of the non-sensitive patterns. This invention precisely allocates optimized computing power and mask budget to the sensitive patterns that have the greatest impact on performance, avoiding the waste of limited computing resources and mask manufacturing budget on non-sensitive patterns that have a negligible impact on performance. This improves circuit performance indicators without significantly increasing the mask design cycle or slowing down the efficiency of shape-aware OPC.

The application provides a tri-state inverter circuit and a bus system, and belongs to the technical field of electronic circuits. The first control end of a transmission gate and the first end of a logic module are used for connecting a power supply voltage, the input end of the transmission gate and the second end of the logic module are used for connecting a control signal, and the output end of the transmission gate is connected with the third end of the logic module. The fourth end of the logic module is used for connecting an input logic level. The transmission gate is used for being turned on when the control signal is a high level, and inputting a high level to the logic module. The logic module outputs a target level under the action of the high level, the control signal and the input logic level, and the target level is opposite to the input logic level. The transmission gate is also used for being turned off when the control signal is a low level, and the logic module is suspended under the action of the control signal and the input logic level. The application can reduce the dynamic power consumption of the tri-state logic gate, and further improve the circuit performance of the tri-state logic gate.

The application belongs to the technical field of brake system performance testing, and relates to an automatic testing system and method for HCU liquid path performance of a vehicle brake system. The system is arranged in a fully-closed safety cabinet, and comprises an upper computer, a servo cylinder pressure building, HCU control, dynamic cooling and a programmable load simulation unit. The system is cooperatively controlled through a CAN bus to realize accurate cooperation of pressure building, pressure maintenance, pressure reduction and valve body driving. The dynamic cooling system adjusts air cooling parameters according to load and time length to ensure stable coil temperature rise. The programmable load unit simulates working condition load by combining multiple steel cylinders. The testing method comprises the steps of preparation, parameter configuration, automatic exhaust, automatic testing, safety monitoring and report generation. Data is collected at high frequency throughout the process, and a PDF report with diagnostic suggestions is automatically analyzed and generated for archiving and storage in a three-level structure. The application realizes full-process automation, has high testing precision, high safety and traceable data, and can efficiently complete HCU liquid path performance detection.

The application discloses an ultra-low frequency polarity adaptive circuit structure and an operation method thereof. The ultra-low frequency polarity adaptive circuit structure comprises: an ultra-low frequency signal module, which is provided with a topology structure of a polarity circuit, and circuit elements of the ultra-low frequency signal module have a nanometer order characteristic size; a core structure module, which comprises a bipolar transistor array and a quantum effect compensation unit, and the bipolar transistor array and the quantum effect compensation unit are respectively used for signal compensation and stability control; a simulation experiment module, which is used for constructing a circuit simulation model and testing circuit performance in a 0.1-10 Hz frequency band; and an improved Gilbert module, wherein input impedance of the improved Gilbert module is not less than 10 12 Ω, an equivalent noise voltage of the improved Gilbert module is not greater than 5 nV / √Hz at a 1 Hz frequency, and a temperature drift coefficient of the improved Gilbert module is less than 0.1 μV / ℃.

Provided in the present application are a computing apparatus, a chip and a method. The computing apparatus comprises at least one compression unit, the compression unit being used for summing four input signals to obtain a first carry signal and a first sum signal, and the compression unit comprising a carry logic gate and a sum logic gate, wherein the carry logic gate is used for summing two carry input signals to obtain a carry value, and inverting the carry value to obtain one carry output signal, and the sum logic gate is used for summing two sum input signals to obtain a first sum value, and obtaining one sum output signal on the basis of the magnitude of the first sum value. By introducing the carry logic gate and the sum logic gate required for carry calculation, the maximum delay path length of a circuit is reduced, such that the power-delay product of the compression unit is reduced and the circuit performance is improved.

The application discloses a spectrum sensing hypergraph partitioning method for MFS large-scale signal processing, which is used for partitioning a super large-scale integrated circuit which is comprehensively completed on an MFS platform, and comprises the following steps: hypergraph coarsening based on an LSH algorithm; performing an initialization method with spectrum sensing on the most coarsened hypergraph to obtain an initialization partition; running an FM algorithm with distance weighting on the obtained initialization partition to perform optimization, then desparsing, restoring the coarsened hypergraph to the hypergraph of the previous level, again using the FM algorithm to locally optimize, and alternately performing desparsing and the FM algorithm until the most original hypergraph, and completing the hypergraph partitioning. Compared with a traditional multi-polarized hypergraph partitioning method, the application can perform topology optimization for an MFS system, can process multi-dimensional weights, is helpful to improve the performance of the distributed circuit, and leaves more resource redundancy for subsequent wiring.

This invention discloses a low-area comparator offset calibration circuit suitable for sub-ADCs, relating to the field of integrated circuit design technology. The circuit includes a capacitive digital-to-analog converter (DAC) module, a resistive DAC module, a comparator module, and a successive approximation logic module. The capacitive DAC module is a fully differential structure, including a positive-terminal capacitor array and a negative-terminal capacitor array. This invention utilizes a high-area-efficiency R-DAC to replace the traditional large-area capacitor calibration array, and further reduces the number of resistors through a segmented structure. Comparator offset is compensated by injecting an adjustable voltage into the calibration capacitor base plate. This invention significantly reduces circuit area overhead and power consumption while maintaining calibration accuracy, with minimal impact on main circuit performance, making it particularly suitable for area-constrained sub-ADC applications.

The application relates to the technical field of circuit partitioning, and specifically discloses a partitioned balance cost calculation method and system. The application first acquires driving node arrival time and load node requirement time, establishes a key degree formula to amplify the key degree of a specific node, constructs a graph G and a balance cost formula, calculates and sorts the key degree and stores the key degree into a queue, creates a set Tree to execute a routing algorithm, and acquires a final routing path through node processing and iterative optimization. The application establishes a key degree formula, which is preferentially processed in routing, guarantees circuit performance, and comprehensively considers total routing and key node cost in the balance cost formula, so that the application adapts to different scenes and balances the relationship between the total routing and the key node cost. The application processes nodes according to the key degree, preferentially processes key nodes, accelerates routing path generation, avoids local optimization through an iterative optimization mechanism, improves circuit reliability and efficiency, effectively solves the defects of traditional methods in the background technology, and improves the accuracy of partition cost calculation and the quality of circuit design.

The application provides a kind of analog integrated circuit multi-objective parameter optimization design method, system and medium, belongs to analog integrated circuit design optimization technical field.The method includes: obtaining circuit performance index measured value and constructing constraint multi-objective optimization model;Initialize population and calculate state characteristic vector representing feasibility, convergence and diversity;Build a reinforcement learning model with state characteristic vector as state space and multiple environment selection strategies as strategy space, dynamically select the optimal strategy;Execute the selected strategy to filter the next generation population, while maintaining three archives to retain the eliminated potential excellent individuals under different preferences;Iterative optimization until the termination condition is met, and output the Pareto optimal solution set.The application realizes adaptive decision of environment selection strategy through reinforcement learning, effectively balances feasibility, convergence and diversity, improves the efficiency and solution set quality of analog integrated circuit transistor size optimization, and the output scheme can be directly used for tape-out.

This application discloses a control method, control device, and photovoltaic system for a photovoltaic system, belonging to the field of photovoltaic technology. The photovoltaic system includes at least two photovoltaic modules connected in parallel at their output terminals. The photovoltaic modules are connected to a voltage regulating circuit. The method includes: acquiring a first voltage value for each of the photovoltaic modules, where the first voltage value is the voltage value of the system neutral point relative to the photovoltaic module; determining a first reference value based on the first voltage values ​​of the at least two photovoltaic modules; and controlling the operation of the voltage regulating circuit connected to the photovoltaic modules based on the first reference value. This method addresses daytime preventative measures in parallel photovoltaic system scenarios by determining a unified control benchmark for the voltage of the positive or negative terminal of the photovoltaic module relative to ground. This allows each voltage regulating circuit to regulate voltage according to the unified control benchmark in parallel scenarios, balancing the adjustment burden among the voltage regulating circuits, effectively suppressing circuit performance degradation, and optimizing anti-PID control performance.

This invention relates to the field of analog circuit design technology and discloses a method for anomaly identification and feature selection of multi-source heterogeneous data. It involves generating and optimizing a custom multi-parameter, multi-constraint circuit topology within an analog circuit environment, using an analog integrated circuit netlist as graph theory input. This method uses a multi-constraint custom circuit, taking an initial circuit structure as graph theory input, predicting the size of the analog integrated circuit using maximum likelihood estimation, and updating the simulated netlist as the graph theory input. Through comparison, the size is continuously updated, ultimately achieving automatic generation of the circuit structure from the desired structure to the final structure. Through state observation, a graph neural network model is used to optimize the circuit topology, ultimately outputting a highly feasible circuit topology whose performance parameters can reach or even surpass those of manually designed analog integrated circuits.

The application provides a computing device, a chip and a method. The computing device comprises at least one compression unit, which is used for summing four-way input signals to obtain a first carry signal and a first sum signal; the compression unit comprises a carry logic gate and a sum logic gate; wherein the carry logic gate is used for summing two-way carry input signals to obtain a carry value, and inverting the carry value to obtain one-way carry output signal; the sum logic gate is used for summing two-way sum input signals to obtain a first sum value, and obtaining one-way sum output signal according to the size of the first sum value. By introducing the carry logic gate and the sum logic gate required for carry calculation, the maximum delay path length of the circuit is reduced, the power delay product of the compression unit is reduced, and the circuit performance is improved.

This invention discloses a method for correcting design errors in a CMOS operational amplifier. First, based on predetermined performance indicators, primarily including unity-gain bandwidth, phase margin, and slew rate, an initial design of the CMOS operational amplifier is performed using a conventional design process to obtain initial circuit parameters. The initial circuit is then simulated to obtain the simulated actual unity-gain frequency, actual phase margin, and actual slew rate. Based on the performance indicators and simulation results, an error factor is calculated. The design parameters are then corrected using the error factor. Finally, based on the corrected design parameters, the dimensions of each MOSFET are recalculated to complete the design error correction. This method, combining simulation and theoretical calculation, identifies and corrects performance errors caused by process deviations, inaccurate models, or simplifications in manual design, thereby ensuring that the final circuit performance meets or exceeds the predetermined indicators.

The embodiment of the application provides a circuit parameter optimization method and related equipment, and belongs to the technical field of circuit design. The method first initializes circuit parameters, and respectively performs circuit simulation under all PVT angles of a PVT angle set according to the circuit parameters to obtain circuit performance under the corresponding PVT angles, then repeatedly performs circuit parameter optimization and simulation operations according to the PVT angle set until a preset iteration condition is reached to obtain optimal circuit parameters. In each optimization and simulation process, an angle sampling strategy of selecting the worst N PVT angles from the PVT angle set and randomly selecting M PVT angles can not only evaluate the circuit design under the worst angles to quickly approach the robustness boundary of the design, but also introduce random angles to increase the diversity of exploration and avoid falling into a local optimal solution, thereby further improving the adaptability of the circuit parameter optimization result under different PVT conditions.

This invention relates to the field of circuit performance testing technology, specifically a method for predicting integrated circuit aging effects and assessing circuit lifetime reliability. The specific implementation process includes: acquiring the physical design netlist and basic process library; parsing the test load into transient flip-flop density and generating a time-varying excitation flow based on layout geometry information; dividing the aging-sensitive region using a dual-track aging differential mechanism; quantifying circuit aging parameters by integrating the time-varying excitation flow; performing full-chip timing simulation on the circuit aging parameters to predict the performance erosion index; calculating the dynamic redundancy shrinkage vector and adjusting the guard band reduction magnitude to converge the evaluation to the target design range. This invention utilizes time-varying excitation flow and sensitivity partitioning topology to effectively capture the multi-physics coupling effect under dynamic loads, improving the prediction distortion problem caused by static assumptions. By optimizing the guard band design through dynamic redundancy shrinkage vector, a balance between chip area, power consumption, and reliability lifetime is achieved.