702 results about "Circuit performance" patented technology

A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.

A switching power converter and method of controlling an output voltage thereof using predictive sensing of magnetic flux provides a low-cost switching power converter via primary-side control using a primary-side winding. The power converter has improved immunity to parasitic phenomena and other variations within the power converter components. An integrator is used to generate a voltage analog that represents magnetic flux within a power magnetic element via an integration of a voltage on a primary-side winding of the power magnetic element. A detection circuit detects the end of a half-cycle of post-conduction resonance that occurs in the power magnetic element subsequent to the energy level in the power magnetic element reaching zero. The voltage of the integrator is stored at the end of the post-conduction resonance half-cycle and is used to determine a sampling point prior to or equal to the start of post-conduction resonance in a subsequent switching cycle of the power converter (which is the predicted zero-energy storage point of the power magnetic element). The primary-side winding voltage is then sampled at the sampling point, providing an indication of the output voltage of the power converter. By predicting the zero-magnetic-energy storage point, the output voltage of a power converter operating in discontinuous or boundary conduction mode can be accurately controlled without being affected by parasitic phenomena or variations in circuit performance over time, input voltage and temperature.

An integrated circuit (IC) design system and method provide an optimization of a layout of an integrated circuit wherein an assessment is taken into account of the circuit performance characteristics and the layout of the IC design. The system and method assess associated circuit performance characteristics, each as a cost function of a local pattern of shapes in an initial circuit layout, aggregate cost functions of the associated circuit performance characteristics to derive an integral performance number associated to the initial global circuit layout, perturb the integral performance number by varying the global circuit layout, and select perturbations that optimize the performance number, so as to optimize the global circuit layout. Assessment is taken into account of the circuit performance characteristics based on the layout and the interdependence of the circuit performance characteristics for the IC design. The physical process related effects such as well proximity effect and stress/strain engineering and/or performance parameters such as the P-N transistor size ratio are taken into account to achieve optimization.

An automated design for manufacturability platform which provides integrated physical verification and manufacturing enhancement operations. The platform uses an efficient data structure capable of handling and manipulating both layout circuit and geometry characteristics, which permits a wide range of operations such as timing analysis, design-rule checking and optical proximity corrections on a single platform. This feature eliminates the need to translate layout representations between various tools without the requirement of using a common database. Moreover, the platform's common user interface enables encapsulated information exchange between the design and the manufacturing teams, permiting early consideration of manufacturing distortion or enhancement impact on circuit performance.

A method of routing a random logic macro (RLM) that is used multiple times in a hierarchical VLSI design without having to route each individual instantiation independently. Once an RLM has been routed and timed it can be copied and reused in a physical design as is, and does not require any wiring changes. This method is an advantage over existing art because it conserves area, improves wireability, and reduces the time required for routing and timing each RLM instance. Furthermore, each RLM possesses the same timing and power characteristics, which improves overall circuit performance.

The present invention provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafers, wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.

A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.

The invention relates to an intelligent multi-core cable harness detection device. The device consists of a programmable power supply, an intelligent multi-channel switch, a current-limiting resistor network, a multi-core converter, a current sampling module, an analog multiplexer, a single-chip, a computer and detection software. The device can automatically analyze short-circuit performance, open-circuit performance and conduction performance of a multi-core cable harness. A harness system state is determined through a harness performance testing matrix graphical detection result and by comparing the result with a pre-stored standard, and different fault types are indicated by colors; and meanwhile, a fault alarm can be sent by an alarm device with sound and changing light. The device has the characteristics of simple and convenient operation, high testing efficiency, high system extensibility and the like, and can be directly used for development of harness-related products, quality control and performance detection.

An extraction, simulation, and analysis combined method is employed to account for the parasitic couplings from interconnect wires. Variations of parasitic resistance, capacitance, and inductance are used in circuit analysis calculators, including considering the variations of the parasitics on worst case circuit performance, skewing, and statistical Monte Carlo analysis. Each parasitic element is modeled as a call-up function with associated process distributions. Circuit analysis, such as a SPICE analysis is performed on the selected models.

We disclose a method for optimizing integrated circuit layout which comprises analyzing constraint relationship among objects in an initial layout; constructing local modifications to the constraint relationship; forming new constraint relationships by combining initial constraint relationships with their local modifications; and producing a new layout by implementing the new constraint relationships. Local modification to constraints provides a framework for bringing detailed local information into the design process in a highly automated manner, which can be applied to a wide range of situations. We disclose preferred embodiments on improving lithography printability, reducing defect susceptibility, and improving circuit performance such as reducing layout variability and leakage.

A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations.

Power output switching circuit for use in high current and high frequency applications. The output circuit provides a series of geometrically symmetric, parallel spaced semiconductor converters arranged such that the voltage for each semiconductor output device is substantially equal and minimal for each device. In this way, each device exhibits substantially the same impedance, such that circuit performance is largely a function of intrinsic device characteristics, and substantially independent of cross coupling and other external influences.

An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values of slack, and are combined. The combination of probability distribution functions represents a measure of circuit performance. The measure is computed for alternative implementations of the circuit, and used to identify an alternative more likely to meet timing constraints.

A semiconductor integrated circuit device includes control circuits FRQCNT, VDDCNT and VBBCNT that generate the optimum clock signal, supply voltage and substrate bias respectively and then supply them to a main circuit LSI. This operation makes it possible to suppress the variations of a CMOS circuit characteristic, thereby improving the circuit performance. Further, the low power consumption is realized without degrading the operating speed of the CMOS circuit or increasing the power consumption of the CMOS circuit.

The invention relates to a multipath routing establishing method based on chain circuit multi-eigenvalue in a wireless sensor network. The method includes: upon transmitting 'interest' data packets from a destination node to an originating node, endowing a definite selection probability to each route according to three eigenvalues (energy consumption, time-delay and band-width) in network chain, thereby establishing a gradient table; upon transmitting detecting data packets from the originating node to the destination nods, selecting a neighbor node with highest probability every time as the node of next-hop, if the neighbor node with highest probability reject to receive data packets, selecting a neighbor node with next high probability as the node of next-hop, until reaching the destination node; finally the destination node transmitting strengthened signals with different grades to the originating node, thereby establishing multipath from the originating node onto the destination node, so that the data can always been transmitted in multipath with better chain circuit performance. The invention extends survival cycle of network, improves transmission reliability and realizes load proportion.

A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.

An electronic device simulator includes a three-dimensional lumped device model, a three-dimensional visco-elastic process simulation model and a material design model that are interlinked with each other. The three-dimensional lumped device element model comprises a Poisson's equation model, an electron continuity equation model, a hole continuity equation model, a Maxwell's equations model, an eddy current equation model, and an Ohm's law equation model. The simulator accounts for the three dimensional characteristics of the circuit to determine circuit performance.

The invention discloses a method for building a covered wire inner full-state turbofan engine vehicle-mounted real-time model. The method comprises the steps of firstly building a vehicle-mounted real-time dynamic model, indicating an applied force-included and above-idle-speed state, of a turbofan engine, then, building a starting simplified model of the turbofan engine, finally, utilizing a Kalman filter for estimating gas circuit performance characteristic parameters of the turbofan engine, and building a vehicle-mounted self-adaptation real-time model indicating the applied force-included and above-idle-speed state. The method can meet the requirement of a covered wire full-state general model of the turbofan engine for precision and vehicle-mounted real-time performance, the strong adaptive capacity for model mismatch caused by the engine individual difference and performance degradation is obtained, model foundation is provided for experimental verification of a modern control theory and a fault-tolerant control method, and the method plays a positive and promotion role in shortening the preparation time, reducing test risk and cost.

A method for performing self-consistent minimization of IC design and process interactions is disclosed. This method is based on calculating the amount of design-process interaction based on the information derived from circuit sensitivity analysis and process characterization. Optical proximity correction is subsequently performed in such a way that a) ensures that desired circuit performance is achieved in a given manufacturing environment if at all possible and b) also limits the increase in mask complexity to a realistic minimum.