139 results about "Circuit performance" patented technology

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention provides an integrated circuit performance testing method based on multi-dimensional parameter fusion, and belongs to the technical field of integrated circuit performance testing. S2, collecting multi-dimensional parameters; s3, data preprocessing; s4, carrying out multi-dimensional parameter fusion; and S5, performance test analysis. Through multi-parameter coverage, multi-algorithm collaboration and full-process closed loop, the problems of isolation, fragmentation and simplification of traditional testing are solved, and systematic and refined technical support is provided for performance testing of the integrated circuit.

The invention relates to the technical field of circuit performance testing, in particular to an integrated circuit aging effect prediction and circuit life reliability evaluation method. The specific implementation process comprises the following steps: acquiring a physical design netlist and a basic process library, analyzing a test load into transient upset density, and generating a time-varying excitation flow in combination with layout geometric information; dividing an aging sensitive domain by using a double-track aging difference mechanism, and performing integration processing on the time-varying excitation flow to quantify a circuit aging parameter; performing full-chip time sequence simulation on the circuit aging parameter, and predicting a performance erosion index; and calculating a dynamic redundancy retraction vector, adjusting the reduction amplitude of the guard band, and converging the evaluation in a target design interval. According to the method, the time-varying excitation flow and the sensitivity partition topology are utilized, the multi-physical field coupling effect under the dynamic load is effectively captured, the problem of prediction distortion caused by static hypothesis is solved, and the balance of the chip area, the power consumption and the reliability service life is achieved through the dynamic redundancy retraction vector optimization design protection band.

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a radio frequency switch chip, and the circuit structure of the radio frequency switch chip comprises a transformer type differential inductor T-L1, a transformer type differential inductor T-L2, a capacitor C1, an NMOS transistor M1, an NMOS transistor M2, a gate resistor RG1, and a gate resistor RG2. The radio frequency switch chip provided by the invention adopts a differential structure, so that the parasitic inductance effect of a grounding key and a wire during packaging and testing can be eliminated, and the insertion loss and the isolation performance are improved; compared with a single-end port, the lower impedance of the differential port is more beneficial to improving the power capacity of the switch; the differential structure allows the transformer type differential inductor to use differential signal characteristics, the equivalent quality factor of the inductor is improved, and the circuit performance is improved; the differential structure can improve the linearity of the circuit, especially the second-order intermodulation effect; the differential structure can be compatible with a modern silicon-based CMOS radio frequency system, and an additional balun is not needed for signal conversion.

The invention belongs to the related technical field of integrated circuit design, and discloses an integrated circuit design process collaborative optimization method and system, and the optimization method comprises the steps: S1, randomly generating a plurality of groups of process parameters; s2, TCAD simulation is carried out, and an electrical characteristic curve of the device is obtained; s3, extracting electrical characteristics and inputting the electrical characteristics into the intelligent parameter extraction model to obtain compact model parameters; s4, inputting the compact model parameters into the SPICE model, and generating an integrated circuit layout by using an automatic layout generation system; s5, taking the optimized circuit performance index as an optimization target, and adopting a Bayesian optimization method to generate an optimal process parameter of a next iteration round; and S6, judging whether an iteration termination condition is met or not, if not, skipping to S2, and if yes, outputting the current process parameters. According to the method, the process / design barrier can be broken, it is ensured that the process development and the circuit design process can be collaboratively carried out, the whole optimization process is completely automatic, and the high-precision and high-efficiency collaborative optimization process is achieved.

The invention belongs to the technical field of integrated circuits, and relates to an automatic design optimization method suitable for a large-scale analog / radio frequency circuit, which comprises the following steps of: hierarchically dividing the large-scale analog / radio frequency circuit into a plurality of circuit modules; carrying out random sampling to obtain an initial data set, and establishing a Pareto frontier model of a lower-layer circuit module; the optimization of the performance index of the system circuit is converted into the optimization of the performance index of the lower circuit module; obtaining a'pseudo 'Pareto optimal point near the optimal performance index of each current lower-layer circuit module by using an improved evolutionary algorithm; updating the Pareto front of the lower layer module by using the extracted Pareto optimal point, and performing constraint mapping calculation until the Pareto front of the current lower layer module is partially overlapped with the actual Pareto front; and solving a design variable of the lower-layer circuit module by using the output optimal performance index of the lower-layer module. According to the method, good circuit performance indexes can be obtained with fewer SPICE simulation times, and the cost of automatic design of a large-scale analog / radio frequency circuit is reduced.

The invention discloses a low-cost soft error reinforcement method based on an approximate triple modular redundancy unit. The method comprises the following steps: establishing an approximate library: establishing an approximate gate unit for a basic gate unit of a to-be-reinforced circuit, and integrally establishing an approximate gate unit library; software modeling: acquiring basic information of each standard gate unit in the circuit, and evaluating the performance of the circuit according to a soft error propagation physical model so as to perform software modeling; and approximate reinforcement: selecting a gate unit in a to-be-reinforced circuit in a semi-directional manner based on improved dynamic adjustment NSGA-II to replace the gate unit with an approximate gate unit in an approximate library, simulating circuit performance indexes through an estimator, performing multi-target optimization solution, obtaining an optimal compromise of area, power consumption and soft error rate through iteration, and giving an approximate reinforcement scheme. The method has high efficiency, practicability and universality, can be used for guiding low-cost soft-error-tolerant approximate reinforcement of various high-reliability structures such as triple modular redundancy (TMR) and the like, and can adapt to multi-scene and multi-requirement circuit reinforcement design.

The invention discloses a multi-layer circuit board quality inspection method and system based on machine learning, and the method comprises the steps: carrying out the time-space registration of collected multi-source data through an adaptive weighted fusion algorithm, and generating a multi-mode quality inspection data set containing a line topological structure and material characteristics; outputting a fused circuit board defect sensitive feature vector set by using a pre-trained nested attention deep learning model based on the multi-modal quality inspection data set; inputting the defect sensitive feature vector set into a twin network architecture, positioning a potential defect area through a dynamic anchor frame generation mechanism, carrying out multi-label classification on defect types in combination with a Bayesian probability model, and synchronously introducing a defect severity evaluation module to quantify the influence degree of defects on circuit performance, and outputting a detection result containing the defect position type and severity. According to the embodiment of the invention, the collaborative judgment of the type, position and severity of the defect can be realized, and the detection precision and generalization capability of the defect of the multilayer circuit board are improved.

The invention discloses an automatic layout method of a filter chip layout and computer equipment. The method comprises the following steps: reading circuit netlist information of a filter; searching a shortest signal path between input and output of the circuit as a main path, and extracting all circuit elements on the main path; performing initial layout on elements on the main path, and storing coordinates of the elements in a coordinate dictionary; an improved force steering algorithm is adopted to carry out layout on the remaining elements, and coordinates of the elements are stored in a coordinate dictionary; judging whether geometric overlap exists among the elements, if yes, eliminating the geometric overlap through adjustment, and meanwhile, ensuring that the connection relationship of the elements corresponds to the netlist; adding an input / output port and adding a scribing channel at the edge of the chip; and performing design rule check and comparison check of the layout and the schematic diagram, if the check is passed, outputting the layout, otherwise, returning to perform overlap detection and adjustment. The design efficiency can be improved, human errors are reduced, and the circuit performance is optimized.

The invention relates to the technical field of integrated circuit reliability analogue simulation, in particular to an analogue simulation system and method applied to an integrated circuit. The method comprises the following steps: acquiring an integrated circuit layout and carrying out circuit topological structure datamation on the integrated circuit layout to obtain an oxide layer area grid chart; performing stress distribution mapping generation on the integrated circuit according to the oxide layer region grid chart to obtain a region stress state matrix; performing electric field-temperature collaborative analysis according to the regional stress state matrix to obtain a random fluctuation factor matrix; performing time sequence damage accumulation calculation according to the random fluctuation factor matrix to obtain a time sequence damage state set; and performing damage state feedback adjustment on the time sequence damage state set to obtain a time-varying damage evolution graph. According to the method, the fragile performance indexes and areas of the integrated circuit are identified, and the comprehensive circuit performance degradation characteristic spectrum is generated, so that a scientific basis is provided for reliability design and performance optimization of the integrated circuit.

This disclosure provides a state switching method, apparatus, and electronic device. The state switching method includes: generating and maintaining a state switching signal when a preset state switching condition is met; switching the state of a target object using the state switching signal; calculating the time interval between the current time and the end time of a synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal; and ending the state switching signal when the time interval meets a preset condition, thus completing the state switching of the target object; the preset condition includes the time interval being an even multiple of a first clock cycle. This embodiment ensures that the output signal of the target object after state switching is synchronized with the synchronization alignment signal, solving the problem of timing disorder and improving circuit performance.

The invention provides a domestic substitution method of a CATV (Community Antenna Television) light receiving chip TAT6254C, which relates to the technical field of CATV light receiving, and comprises the following steps of: S1, chip substitution: carefully taking down a TAT6254C chip on an original circuit board, and welding a domestic GNA4118 chip on the circuit board according to a correct pin direction and position, S2, peripheral circuit adjustment: analyzing the difference of frequency response and balance characteristics of the two chips, and adjusting the frequency response and balance characteristics of the two chips according to the difference of the frequency response and balance characteristics of the two chips. Redesigning an output matching circuit, adjusting a frequency response and equalization circuit, optimizing the output matching circuit, and adjusting a chip drive and matching circuit. According to the domestic substitution method for the CATV optical receiving chip TAT6254C, a domestic GNA4118 chip is used for substituting an imported TAT6254C chip, so that the purchase cost of the chip is reduced, the risk caused by unstable supply of the imported chip is reduced, the risk of production interruption caused by shortage of the chip is reduced, the characteristics of the GNA4118 chip can be optimized by adjusting an output matching circuit, and the production efficiency of the CATV optical receiving chip TAT6254C is improved. And the performance of the circuit can reach or exceed the original level of using a TAT6254C chip.

Methods, systems, and computer-readable media are used in graph-based machine learning of analog integrated circuits (ICs). In a first aspect, functional device pairs in transistor-level circuits are detected and classified using a hybrid approach combining a subgraph isomorphism algorithm, such as VF2, with a trained relational-graph convolutional network (RGCN). The VF2 algorithm identifies candidate pairs and initial categories, while the RGCN filters false positives using link prediction scores, preserving category labels for validated pairs. In a second aspect, a relational GraphSAGE model performs multi-class link prediction on a heterogeneous graph with netlist and functional relation edge types, labeling device pairs into analog primitive categories without technology-dependent features and merging overlapping pairs into larger functional groups. In a third aspect, circuit performance is predicted using a hierarchy-aware graph neural network comprising an edge-conditioned convolution (ECC) layer and multiple Circuit graph isomorphism network layers corresponding to hierarchy levels of device groupings.

The invention provides a multi-agent reinforcement learning optimization method of an analog circuit and a related device. The method comprises the following steps: setting an ideal performance parameter group of the analog circuit; clustering the components according to the transient current curves of the components to obtain a plurality of component groups; configuring an intelligent agent for each component group, and enabling the intelligent agent to output a circuit parameter value according to the ideal performance parameter group; applying the circuit parameter value to a simulation circuit for simulation to obtain a simulation circuit performance value; updating the intelligent agent according to the simulation circuit performance value and a preset target performance value to obtain a target intelligent agent; the elements are clustered by analyzing the actual current characteristics of the circuit under transient response, so that the elements with similar functions are divided to the same agent, thereby breaking the limitation of a physical module, realizing parameter decoupling and collaborative optimization, and improving the convergence efficiency.

The invention discloses a scheduling-driven high-level comprehensive array division method, which comprises the following steps of: creating an associated access instruction set for arrays in algorithm design, and analyzing an address calculation expression of each access instruction; on the basis of the control data flow diagram designed by the algorithm, instruction scheduling is executed according to an instruction topological sequence and circuit performance requirements, for an array access instruction, a schedulable interval of the array access instruction is calculated, control steps in the interval are traversed, and incremental address conflicts introduced by each scheduling mode are determined; aiming at each scheduling mode of the array access instruction, a minimum overhead array division scheme capable of solving all address conflicts is searched, and the overhead of the division scheme comprehensively considers the number of storage modules after division, address control logic complexity and time delay; the address conflicts comprise the incremental address conflicts and the stock address conflicts. The method has the advantages that compared with an existing array division scheme, calculation scheduling and array division are organically combined, the cost of array division is reduced, and the scheduling performance is improved.

The application provides an integrated circuit yield estimation method and a memory, and the method comprises the following steps: formulating a boundary of a success region and a failure region of an integrated circuit performance in a parameter space, and representing the boundary as a boundary surface formula equation; calculating a size of a space defined by the boundary surface formula equation and a boundary surface formed by each parameter axis; and calculating a ratio of the size of the space defined by the boundary surface formula equation and the boundary surface formed by each parameter axis to a size of a space formed by each parameter range, to obtain an estimated yield. The technical scheme of the application can improve the estimation efficiency of the integrated circuit yield.

The invention discloses a load isolation type power supply module aging device and a design method thereof, and belongs to the field of aging tests. The clamp plate and the load plate are separately designed, and the clamp plate is in butt joint with the applicable load plate through the golden fingers, so that the flexibility of the matching plate is ensured, the design time and the purchase cost are reduced, and the test efficiency is improved. According to the invention, the influence of load resistor heating on the power module circuit is effectively reduced, and the accuracy and safety of module circuit test are guaranteed; aiming at the performance of a module circuit, compatibility design is carried out on different output paths of the same package, so that the burn-in test can be carried out by using the same board during single-path output or double-path output, and the reuse rate of the clamp board is improved. The load board simultaneously comprises a state monitoring module, has the functions of monitoring output voltage, alarming abnormity and storing, and ensures high reliability of the test.

The invention discloses a vehicle-gauge-level analog circuit performance margin monitoring system and method, the system is based on a vehicle-gauge-level chip comprising a digital circuit and an analog transceiver circuit, and the digital circuit comprises a main controller CPU, a performance analysis engine module and a programmable pressure source module; the main controller CPU comprises a performance reference module and a pressure loopback self-checking module; the method comprises the following steps: in an initialization stage of a vehicle gauge level chip, executing an internal loopback test once under a reference condition, and quantifying a performance reference; in the inter-frame phase of data communication, the programmable pressure source applies instantaneous pressure to the analog transceiver circuit; when pressure is applied, loopback self-inspection is executed, and key performance indexes at the moment are quantified; and the digital circuit compares the performance index under the pressure with a previously stored performance reference, calculates a performance margin, and carries out early warning on an aging state or a potential performance degradation risk of the circuit according to the magnitude and the change trend of the margin.

The application discloses a three-dimensional integrated packaging structure based on a dielectric integrated suspended line, which comprises N layers of dielectric plates covered with metal on both sides; the N layers of dielectric plates are stacked from bottom to top; the dielectric plates of any one or any multiple adjacent layers from the 2nd layer to the N-1th layer are patterned and hollowed to form at least one air cavity; metalized through holes are formed on the 1st layer to the Nth layer to form an electric wall around the air cavity; the 1st layer and the Nth layer together with the formed electric wall constitute an electromagnetic shielding cavity; the 2nd layer to the N-1th layer are electrically connected through a three-dimensional vertical interconnection technology; and one or more functional devices are arranged in each air cavity. The application can realize the collaborative design of functional devices, system circuits and packaging, reduce the influence of packaging on the performance of circuits, reduce the mutual interference between functional devices, facilitate individual debugging, reduce transmission loss, be favorable for realizing high-speed data transmission and improve system reliability.

To provide a calibration method for calculating the electrical characteristics of semiconductor devices that can improve the accuracy of calculating the electrical characteristics of semiconductor devices, a calibration semiconductor device used for calibration, and a semiconductor device that can suppress the degradation of circuit performance. [Solution] The adjustment semiconductor device 2 includes an adjustment main body 20 having substantially the same structure as the target main body 10 and an adjustment wiring section 21 having higher heat dissipation than the target wiring section 11. The adjustment semiconductor device 2 includes a step of determining whether the difference between the measured value of the first electrical characteristics and the calculated value of the first electrical characteristics is within a predetermined tolerance range. If the determination result in the step is within the tolerance range, the adjustment step includes adjusting predetermined physical constants, including carrier mobility, used in a second simulation that calculates the electrical characteristics of the target semiconductor device 1 using the carrier mobility of the adjustment semiconductor device 2.

The utility model relates to verification fixture, specifically relates to a general integrated circuit performance verification fixture, including PCB board, and the product fixed base of setting in the middle part of PCB board upper surface, still be equipped with a plurality of groups with product fixed base pin number same's BNC joint, single -pole double -throw switch, banana plug and equipment welding tray on PCB board, in any group BNC joint, single -pole double -throw switch, banana plug and equipment welding tray, single -pole double -throw switch's common end is linked with the pin of product fixed base, and equipment welding tray is connected between single -pole double -throw switch's common end and the pin of product fixed base, single -pole double -throw switch's two signal ends are linked with BNC joint, banana plug respectively. Compared with prior art integrated circuit performance verification mode, the utility model can be applicable to the performance verification of common multiple integrated circuits, need not design corresponding integrated circuit performance verification fixture for specific kind of integrated circuit, and the verification cost is reduced.

A wave trap optimization method and system, and a related device. The method comprises: acquiring a circuit structure and circuit parameters of a wave trap to be optimized, and determining optimization indexes (S1); on the basis of the circuit structure and the corresponding circuit parameters, calculating a resonator performance parameter and a matching circuit performance parameter (S2); on the basis of a preset resonator adjustment method, adding, to the circuit structure, a resonator for constituting the wave trap, so as to obtain a new first optimized circuit structure (S4); on the basis of a preset matching circuit adjustment method, adding, to the first optimized circuit structure, a matching circuit for constituting the wave trap, so as to obtain a new second optimized circuit structure (S7); and on the basis of the second optimized circuit structure and the corresponding circuit parameters, using a first preset optimization method to perform optimization, so as to obtain an optimized circuit of the wave trap (S9).

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, the substrate comprising a first region; forming an initial first gate structure on the first region, the initial first gate structure comprising an initial first gate; forming at least one first gate opening in the initial first gate to form a first gate structure with the initial first gate structure and to form a first gate with the initial first gate; forming a second gate in the first gate opening, the material of the first gate and the material of the second gate being different, and the second gate material having different performance according to different integrated circuit performance requirements of the first gate structure, so as to adjust the performance of the first gate structure and to meet more integrated circuit design requirements.

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate which comprises a first region and a second region and comprises an x direction and a y direction which are perpendicular to each other; a plurality of first fins extending along the x direction are formed on the semiconductor substrate in the first region, and a plurality of second fins extending along the y direction are formed on the semiconductor substrate in the second region. The invention provides a semiconductor structure and a forming method thereof, which can improve the N / P mismatch characteristic of a CMOS (Complementary Metal Oxide Semiconductor) in a VFET (Very Field Effect Transistor), can enable an N / PMOS (P-channel Metal Oxide Semiconductor) to have relatively high mobility and can improve the circuit performance.

The invention relates to a microstrip network layout optimization method based on Fourier series, and belongs to the technical field of radio frequency circuit design. The method aims at solving the problems of topology dependence, boundary discontinuity and low efficiency caused by sharp increase of optimization parameters along with the area in a traditional rectangular spliced microstrip network. The core of the technical scheme is that a microstrip network boundary is modeled into a plane closed curve, the curve is represented through Fourier series decomposition, and a Fourier coefficient is optimized by taking circuit performance as a target drive, so that a microstrip layout with any shape and a continuous and smooth boundary is generated. According to the method, automatic design rule checking and port adding processes are integrated, and finally electromagnetic simulation iteration is carried out until a design target is met. The method can break through the limitation of the traditional topology, effectively improves the electromagnetic performance and design efficiency, and is widely applied to the microstrip network design of broadband matching, multi-band matching, harmonic control and the like.

The invention discloses a preparation method of an IGBT device. The IGBT device comprises a substrate, an interlayer dielectric layer, a metal barrier layer, a metal layer, a first passivation layer, a second passivation layer, an alloy processing substrate and a semiconductor device area. The stress in the semiconductor device is released through alloying treatment after photoetching, the problem that the stress of a boron-free phosphorosilicate glass IGBT device is too large in the related technology is solved, due to the fact that the stress is reduced, the channel opening of the IGBT device is more sufficient under the low opening voltage, the problem that the saturation voltage drop of a collector and an emitter is discrete is effectively solved, and the reliability of the IGBT device is improved. The stability and the consistency of the IGBT device are improved, and the performance and the reliability of the whole circuit can be improved; the passivation layer is changed from a single silicon-rich silicon nitride layer to the combined film layer of the silicon nitride layer and the silicon-rich silicon nitride layer, so that the problem of small black spots in the subsequent newly-added alloying treatment process is avoided, the structure of the combined film layer is more stable, and the durability and reliability of the device are improved.

The invention provides a diode combination packaging method, which comprises the steps of extracting heat conduction complex areas from a heat dissipation balance degree, applying a topological optimization algorithm to optimize packaging density for the areas, and obtaining optimized circuit performance indexes through iterative calculation; unstable factors are extracted from the corrected work stability evaluation value, potential heat conduction complex points are obtained through heat flow simulation according to the factors, and a packaging density adjustment scheme is determined; the adaptability of the isolation distance is judged according to the long-term index, if the adaptability is insufficient, a key path is selected from the heat dissipation data, a fine adjustment value of the packaging density is obtained, and a correction path with poor performance is determined; and high-integration-level compatible data is extracted from the correction path, stable output of circuit performance is obtained through comprehensive simulation for the compatible data, and the applicability of the whole scheme is judged.

The invention belongs to the technical field of integrated circuits, and provides a single-ended MEMS input-to-differential output circuit and an implementation method thereof. Through the CMFB circuit, effective signals of the CMEMS are averagely distributed to the VBIAS end and the VIN end, the maximum signal range which can be processed by the Pre-amplifier is doubled, meanwhile, a single-end-to-differential circuit is omitted, power consumption and noise are reduced, and circuit performance is improved. Compared with the prior art, according to the technical scheme, an impedance matching circuit or a capacitance compensation circuit is omitted, so that signal attenuation caused by parasitism is reduced, and performance is improved. Particularly, the stray capacitance of the VBIAS end can be ignored. The problem of performance deterioration under the condition that the stray capacitance of the VBIAS end is too large in the prior art is solved.

A state-of-the-art memory controller and methods for using the same are disclosed. The memory controller is intended for use with dynamic random-access memory (DRAM) circuitry. In one example, a memory controller includes a reordering preprocessor circuitry coupled to a reordering scheduler circuitry. The reordering scheduler circuitry is configured to control a reordering scheduler queue, and is coupled to DRAM circuitry. The reordering preprocessor circuitry is configured to control a preprocessor queue and reorder transactions in the preprocessor queue so as to increase the DRAM circuitry performance.

This invention relates to the field of three-dimensional spatial circuit manufacturing technology, specifically disclosing an auxiliary testing device and performance testing method for three-dimensional spatial circuits. The device includes auxiliary components designed and manufactured based on the substrate prefabrication structure in an integrated three-dimensional spatial circuit product, and a base assembly for fixing and supporting the auxiliary components. The auxiliary components include a tombstone assembly, and two blocks located on either side of the tombstone assembly and connected to it. The tombstone assembly includes multiple sets of tombstone structures connected in sequence; each set of tombstone structures is equipped with a tombstone body. This invention enables the testing of the circuit performance on the surface of the three-dimensional spatial circuit without cutting or damaging the tombstone bodies that may obstruct the circuit, obtaining the required circuit fabrication process parameters, reducing testing costs, and improving the accuracy of circuit fabrication.