251 results about "Circuit performance" patented technology

The invention discloses a process deviation-oriented analog circuit parameter optimization method, which comprises the following steps of: S1, carrying out multi-objective optimization on a given analog circuit under a nominal process condition, identifying and eliminating a design region with poor performance according to an optimization result, and carrying out clustering analysis to obtain an optimal design region; dividing the remaining high-quality areas into a plurality of initial trust areas; s2, modeling the finite Monte Carlo simulation data in the initial trust area by using a heterovariance Gaussian process model, capturing an average level and a change trend of circuit performance, and predicting behaviors of the circuit under process change; and S3, the required yield is kept while the performance is optimized, probability assurance is provided for the performance value by adopting the risk value, and a design point optimization set and a corresponding Pareto optimal solution set are finally obtained through multiple iterations in the optimization stage of considering the process change. According to the method, the high-quality Pareto optimal solution set meeting the yield constraint is found under the process change of unknown distribution, and the size of an analog circuit is optimized.

The invention relates to the technical field of circuit design, in particular to a digital circuit simulation design method and system. The method comprises the following steps: identifying a design demand document, performing deep semantic analysis and demand constraint mining, and constructing a demand specification constraint parameter set; performing demand complexity evaluation and multi-level division according to the demand specification constraint parameter set, and constructing a basic circuit architecture design blueprint; circuit routing path planning is carried out according to the basic circuit architecture design blueprint, and a standardized circuit topology network is constructed; performing electric signal propagation simulation on the standardized circuit topology network, and performing global circuit adaptability adjustment to obtain a circuit topology design scheme; and carrying out an extreme condition simulation test based on the circuit topology design scheme, and carrying out comprehensive performance evaluation to obtain a circuit performance evaluation report. By deeply understanding the user demand intention, the circuit layout matched with the user demand is designed, and the overall circuit performance is improved.

The invention discloses a layout method of a printed circuit board, a product, equipment and a readable storage medium, and relates to the technical field of PCB design, and the method comprises the steps: carrying out the optimization decoupling and optimization separation of a position layout and a rotation angle into independent stages of sequential execution, avoiding the mutual interference of two types of decisions, greatly reducing the search space, and improving the convergence efficiency. After newly-added elements are placed every time, all the placed elements on the current board are subjected to rotation optimization, the accumulated influence of default direction deviation of early-stage elements on subsequent layout is eliminated, the optimal solution is gradually approached through multi-round iteration, the total length of a finally-arranged wire net is reduced, the signal transmission performance of the PCB is remarkably improved, and the reliability of the PCB is improved. Therefore, the problem of irreversible influence of early decision on subsequent layout is solved, and the beneficial effects of improving layout quality and optimizing PCB circuit performance are achieved.

The invention provides an EDA (Electronic Design Automation) software collaborative optimization method based on a memory compiler entity IP (Internet Protocol), which relates to the technical field of memorizers and comprises the following steps: acquiring IP layout information, and establishing a time sequence netlist model containing path time sequence and power consumption distribution; by adjusting the intensity of a data driver and a hierarchical structure of a decoder, setting multiple stages of buffers to realize time sequence convergence; determining a hot spot area based on power consumption distribution, and inserting a low-power-consumption unit capable of dynamically adjusting voltage frequency to realize local power consumption dynamic balance; the layout is updated, wiring is optimized, the optimized memory compiler IP layout is generated, and the circuit performance and reliability are improved.

The invention provides a modular multiplier circuit applied to a post quantum cryptography algorithm and a calculation method thereof, and the circuit comprises a first calculation module which is used for calculating a result of (a * b1) modq, and obtaining a first calculation result f; wherein mod represents a complementation algorithm; the second calculation module is used for calculating a result of (a * b2) modq to obtain a second calculation result g; wherein a is 23-bit data, b is 23-bit data, b1 represents data from the 5th bit to the 22th bit of the data b, and b1 represents data from the 0th bit to the 4th bit of the data b; and the third calculation module is used for calculating a result of the (f + g) modq so as to obtain a final output result. According to the structure, only one DSP is used, and a register is inserted through a modular reduction method and a critical path, so that the circuit performance is further improved.

The invention provides an integrated circuit performance testing method based on multi-dimensional parameter fusion, and belongs to the technical field of integrated circuit performance testing. S2, collecting multi-dimensional parameters; s3, data preprocessing; s4, carrying out multi-dimensional parameter fusion; and S5, performance test analysis. Through multi-parameter coverage, multi-algorithm collaboration and full-process closed loop, the problems of isolation, fragmentation and simplification of traditional testing are solved, and systematic and refined technical support is provided for performance testing of the integrated circuit.

The embodiment of the invention provides a processing unit scheduling device and method, a chip and related equipment, the processing unit scheduling device comprises a first arbiter and M processing units connected with the first arbiter, and M is a positive integer greater than or equal to 2; wherein each processing unit is used for sending a first request signal to the first arbiter, the first request signal is used for requesting to switch the corresponding processing unit from a first power consumption state to a second power consumption state, and the power of the first power consumption state is lower than that of the second power consumption state; the first arbiter is used for receiving first request signals respectively sent by one or more of the M processing units, and arbitrating to obtain a first response sequence of the one or more first request signals; and controlling the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence. By implementing the embodiment of the invention, the phenomenon of functional errors of the circuit caused by voltage undershoot can be reduced, and the circuit performance is improved.

The embodiment of the invention provides a transmitting circuit, a receiving circuit, an integrated circuit chip and a test method. The transmitting circuit comprises a test data generation module, a to-be-tested transmitting module, a test receiving module and a test data detection module, wherein the test data generation module is configured to generate first test data; the to-be-tested sending module is configured to generate second test data based on the first test data; the test receiving module is configured to generate third test data based on the second test data; the test data detection module is configured to receive third test data and detect whether the third test data is consistent with the first test data, and the to-be-tested sending module is further configured to receive a first clock signal with an adjustable phase. The test receiving module and / or the test data detection module are / is further configured to receive a phase-adjustable second clock signal. According to the sending circuit, the circuit performance can be prevented from being affected, and performance testing, screening and grading of a physical layer circuit are achieved in the wafer testing stage.

The invention provides a layout generation method, a constraint file editor, a layout generator and a terminal.The layout generation method comprises the steps that firstly, device parameters of a target fixed circuit structure are converted into device parameters of a corresponding layout structure based on a configuration file; and determining the arrangement type, array number, spacing and other structural layouts of the device according to the layout rule. And generating a constraint file of bottom design through preset process parameters, and finally generating a layout result of the target fixed circuit structure based on the structural layout of the device and the constraint file. According to the scheme, full-automatic layout and wiring of the analog circuit layout can be realized, the design efficiency is remarkably improved, and the dependence on a specific process and a professional threshold of a layout engineer is reduced. Meanwhile, through parameterization constraint and symmetrical layout control on a fixed circuit structure, high symmetry of the layout is ensured, and the stability and reliability of circuit performance are effectively improved.

The invention provides a method for detecting the influence of temperature and mechanical deformation accumulation on the anti-short circuit performance of a converter transformer, belongs to the technical field of converter transformer anti-short circuit, and deeply studies the mechanical response characteristics of the converter transformer under different temperature and dynamic force load conditions through precise experiments and data analysis. Firstly, material characteristic parameters are obtained, temperature and mechanical load tests are carried out on a dynamic mechanical tension press, and temperature field distribution, mechanical response, residual deformation and insulation distance change of a converter transformer component are recorded in detail by using advanced equipment such as a three-dimensional laser scanner, a temperature sensor, a displacement sensor and a high-speed camera system. Through finite element analysis and data processing, a dynamic characteristic database under the accumulated action of temperature and mechanical deformation is established, and a correlation model is trained by applying a machine learning technology, so that the problem that a detection method capable of comprehensively evaluating temperature-mechanical deformation-electrical performance interaction is lacked in the prior art is solved.

The invention relates to an RC circuit health state assessment method, belongs to the technical field of circuit health management of equipment, and solves the technical problems of circuit health state assessment inaccuracy and high calculation cost caused by an algebraic ring in the prior art. The method comprises the following steps: constructing a multi-physics field coupling degradation model and a block diagram simulation model of the RC circuit device; the simulation module is used for acquiring a block diagram simulation model; converting the simulation module into a directed graph and obtaining an algebraic ring candidate set; determining a solving execution sequence of the simulation modules; establishing an algebraic ring solver according to a trust region broken line method; and obtaining a complete dynamic response result of the RC circuit device multi-physical field coupling degradation model in the whole simulation time by using an algebraic ring solver, and evaluating the health state of the RC circuit. According to the method, the algebraic ring in the degradation model can be accurately identified and efficiently processed, so that the physical authenticity of a degradation mechanism is ensured, and high-precision tracking of RC circuit performance and reliable evaluation of health state indexes are realized.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

The invention provides a preparation method of a semiconductor structure, and particularly relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the steps that a substrate is provided, the substrate comprises a substrate body, a pad oxide layer, a first pad nitride layer and a plurality of groove isolation structures, the pad oxide layer covers the portion, between every two adjacent groove isolation structures, of the substrate body, the first pad nitride layer covers the surface of the pad oxide layer, and the groove isolation structures are at least partially exposed out of the substrate body; removing the first pad nitride layer; performing ion implantation on the substrate; carrying out thinning treatment on the pad oxide layer; forming a second pad nitride layer on the surfaces of the trench isolation structure and the pad oxide layer; etching the second pad nitride layer, the pad oxide layer and the substrate by taking the patterned photoresist as a mask so as to form an opening in the substrate; and performing thermal oxidation treatment on the substrate in the opening to form an oxide layer. By adopting the preparation method of the semiconductor structure, the speed of a semiconductor device can be increased, and the circuit performance of the semiconductor device can be improved.

The invention discloses a CMOS analog multiplier circuit, the circuit comprises a current-to-voltage circuit and a multiplier sub-circuit connected with the current-to-voltage circuit, an OSC circuit in the multiplier sub-circuit receives an input voltage VB and a reference voltage VREF and generates a two-phase non-overlapping clock signal group, a voltage-to-current A circuit converts a voltage VA into a current iA, and the current iA is connected with the OSC circuit. The switched capacitor integrating circuit inputs a sampling voltage to the voltage-to-current B circuit and integrates a difference current is of a current iA and a current iB to realize multiplication, the voltage-to-current B circuit converts a sampling voltage signal into the current iB, and the current-to-voltage circuit converts the current iB into an output voltage Vo as a multiplier operation result. Through combination of modular design, a current mode method and a switched capacitor method and high-precision current conversion and integration processes, an efficient and accurate multiplication simulation function is realized, a THD enhancement function is introduced through multiplexing design, and circuit performance is further optimized.

The invention relates to the technical field of circuit performance testing, in particular to an integrated circuit aging effect prediction and circuit life reliability evaluation method. The specific implementation process comprises the following steps: acquiring a physical design netlist and a basic process library, analyzing a test load into transient upset density, and generating a time-varying excitation flow in combination with layout geometric information; dividing an aging sensitive domain by using a double-track aging difference mechanism, and performing integration processing on the time-varying excitation flow to quantify a circuit aging parameter; performing full-chip time sequence simulation on the circuit aging parameter, and predicting a performance erosion index; and calculating a dynamic redundancy retraction vector, adjusting the reduction amplitude of the guard band, and converging the evaluation in a target design interval. According to the method, the time-varying excitation flow and the sensitivity partition topology are utilized, the multi-physical field coupling effect under the dynamic load is effectively captured, the problem of prediction distortion caused by static hypothesis is solved, and the balance of the chip area, the power consumption and the reliability service life is achieved through the dynamic redundancy retraction vector optimization design protection band.

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a radio frequency switch chip, and the circuit structure of the radio frequency switch chip comprises a transformer type differential inductor T-L1, a transformer type differential inductor T-L2, a capacitor C1, an NMOS transistor M1, an NMOS transistor M2, a gate resistor RG1, and a gate resistor RG2. The radio frequency switch chip provided by the invention adopts a differential structure, so that the parasitic inductance effect of a grounding key and a wire during packaging and testing can be eliminated, and the insertion loss and the isolation performance are improved; compared with a single-end port, the lower impedance of the differential port is more beneficial to improving the power capacity of the switch; the differential structure allows the transformer type differential inductor to use differential signal characteristics, the equivalent quality factor of the inductor is improved, and the circuit performance is improved; the differential structure can improve the linearity of the circuit, especially the second-order intermodulation effect; the differential structure can be compatible with a modern silicon-based CMOS radio frequency system, and an additional balun is not needed for signal conversion.

The invention belongs to the related technical field of integrated circuit design, and discloses an integrated circuit design process collaborative optimization method and system, and the optimization method comprises the steps: S1, randomly generating a plurality of groups of process parameters; s2, TCAD simulation is carried out, and an electrical characteristic curve of the device is obtained; s3, extracting electrical characteristics and inputting the electrical characteristics into the intelligent parameter extraction model to obtain compact model parameters; s4, inputting the compact model parameters into the SPICE model, and generating an integrated circuit layout by using an automatic layout generation system; s5, taking the optimized circuit performance index as an optimization target, and adopting a Bayesian optimization method to generate an optimal process parameter of a next iteration round; and S6, judging whether an iteration termination condition is met or not, if not, skipping to S2, and if yes, outputting the current process parameters. According to the method, the process / design barrier can be broken, it is ensured that the process development and the circuit design process can be collaboratively carried out, the whole optimization process is completely automatic, and the high-precision and high-efficiency collaborative optimization process is achieved.

A method for automatic control of a simulation error in an analog circuit and a use thereof are provided. The method first determines a measurement object and acquires a simulation standard by simulating the measurement object. Then, the method performs simulation based on different parameters of a circuit netlist to acquire an electrical parameter and / or circuit performance evaluation indicator of the measurement object during a simulation process. The method forms a simulation sampling dataset based on a simulation option combination parameter and an error corresponding to the simulation standard. Finally, the method optimizes and analyzes the simulation sampling dataset based on an artificial intelligence algorithm to acquire a simulation option combination that meets a simulation error requirement and takes a least time. The solution achieves automatic selection of the simulation option combination, improving the accuracy of the simulation result.

The embodiment of the invention provides a method, equipment and device for chip design, a medium and a program product, and relates to the field of chip design tools. The method includes determining at least one confinement circuit structure among a plurality of devices designed for a chip of a first process. Dimensions of a set of devices in each of the at least one confinement circuit structure have a dimensional constraint between the dimensions of the set of devices in each of the at least one confinement circuit structure. The method further includes determining device parameter values of the plurality of devices under a second process different from the first process based on the size constraint; and determining that the chip design for the second process satisfies a circuit performance condition by the device parameter value. The method further includes migrating the chip design from the first process to the second process based on determining that the circuit performance condition is satisfied. In this way, by using the size constraint contained in the constraint circuit structure in the chip design of the first process, the device parameter optimization process under the second process can be accelerated, and thus the process migration efficiency is improved.

The invention discloses an integrated circuit worst performance processing method, and relates to the field of integrated circuits, and the method comprises the steps: employing a corrected normal distribution cumulative distribution function CDF to describe the nonlinearity between the failure rate and the circuit performance, and introducing a skewness parameter and a kurtosis parameter; and carrying out weight calculation on the sampling points, highlighting important samples near the failure boundary, and constructing a local linear model in a local region by adopting weighted least square regression. On the global scale, logarithmic transformation is carried out on a sampling matrix, feature distribution is converted from nonlinearity to approximate linearity, an orthogonal matching pursuit algorithm is adopted to construct a sparse global linear model, and the generalization ability and interpretation of the model are improved. Finally, according to the method, a circuit performance predicted value at 6 sigma calculated by a corrected Gaussian function is taken as a target, a global or local linear model is flexibly selected as a constraint condition according to the position of a worst performance point, an optimal solution is iteratively solved, and the estimation precision and the calculation efficiency are effectively balanced.

The invention provides an automatic layout method for electronic components of a circuit board, and the method comprises the steps: exporting functional modules in a schematic circuit diagram into an independent circuit netlist, carrying out the layout modeling of the components through employing a single-layer binary tree structure, and carrying out the layout modeling of the whole circuit based on a multi-layer binary tree structure. Therefore, a multi-layer nested binary tree structure is formed. An optimization algorithm is combined with a heuristic strategy, and circuit performance parameters such as wire length, layout area and signal integrity are used as optimization targets to carry out iterative optimization on the layout model. And automatically generating a detailed layout scheme of the circuit board according to the optimized layout model. Before layout, preprocessing of a schematic circuit diagram is carried out, after layout, verification of a layout scheme is carried out, and it is ensured that all design constraints are met. The circuit board design efficiency and quality can be remarkably improved, the workload of manual adjustment is reduced, the risk of design reworking is reduced, and the automatic design level is improved.

The invention discloses an analog circuit performance driving automatic wiring method based on multiple modes, and belongs to the technical field of integrated circuit design. According to the method, key information in circuit layout, physical interconnection and logic netlists is extracted by generating an input cost diagram containing horizontal, vertical and via hole wiring cost information and utilizing a multi-scale routing model fused by multi-modal features. Furthermore, the gradient of the input cost diagram to the circuit performance is calculated through back propagation of the neural network, and a wiring guidance diagram is generated through post-processing to guide subsequent detailed wiring based on an A * search framework and symmetric constraints. Finally, the method can improve the wiring precision, achieves the optimization of the performance of an analog circuit, and provides an efficient and intelligent wiring solution for the automatic design of an integrated circuit.

The invention belongs to the technical field of integrated circuits, and relates to an automatic design optimization method suitable for a large-scale analog / radio frequency circuit, which comprises the following steps of: hierarchically dividing the large-scale analog / radio frequency circuit into a plurality of circuit modules; carrying out random sampling to obtain an initial data set, and establishing a Pareto frontier model of a lower-layer circuit module; the optimization of the performance index of the system circuit is converted into the optimization of the performance index of the lower circuit module; obtaining a'pseudo 'Pareto optimal point near the optimal performance index of each current lower-layer circuit module by using an improved evolutionary algorithm; updating the Pareto front of the lower layer module by using the extracted Pareto optimal point, and performing constraint mapping calculation until the Pareto front of the current lower layer module is partially overlapped with the actual Pareto front; and solving a design variable of the lower-layer circuit module by using the output optimal performance index of the lower-layer module. According to the method, good circuit performance indexes can be obtained with fewer SPICE simulation times, and the cost of automatic design of a large-scale analog / radio frequency circuit is reduced.

The invention discloses a dielectric cavity filtering coupler for an indoor distribution system, particularly relates to the technical field of wireless communication, and solves the technical problems that in the prior art, a filter and a coupler need to be arranged separately as independent devices, the circuit size is large after cascade connection, and the space utilization rate is low. According to the technical scheme, the filter and the coupler are integrally designed and integrated, and the circuit structure is multiplexed. According to the invention, connecting lines and interfaces between discrete devices can be eliminated, cascade loss and insertion loss are reduced, the circuit performance is improved, the system architecture is more simplified through multifunctional integration, and the reliability is improved.

The invention discloses a low-cost soft error reinforcement method based on an approximate triple modular redundancy unit. The method comprises the following steps: establishing an approximate library: establishing an approximate gate unit for a basic gate unit of a to-be-reinforced circuit, and integrally establishing an approximate gate unit library; software modeling: acquiring basic information of each standard gate unit in the circuit, and evaluating the performance of the circuit according to a soft error propagation physical model so as to perform software modeling; and approximate reinforcement: selecting a gate unit in a to-be-reinforced circuit in a semi-directional manner based on improved dynamic adjustment NSGA-II to replace the gate unit with an approximate gate unit in an approximate library, simulating circuit performance indexes through an estimator, performing multi-target optimization solution, obtaining an optimal compromise of area, power consumption and soft error rate through iteration, and giving an approximate reinforcement scheme. The method has high efficiency, practicability and universality, can be used for guiding low-cost soft-error-tolerant approximate reinforcement of various high-reliability structures such as triple modular redundancy (TMR) and the like, and can adapt to multi-scene and multi-requirement circuit reinforcement design.

The invention discloses a multi-layer circuit board quality inspection method and system based on machine learning, and the method comprises the steps: carrying out the time-space registration of collected multi-source data through an adaptive weighted fusion algorithm, and generating a multi-mode quality inspection data set containing a line topological structure and material characteristics; outputting a fused circuit board defect sensitive feature vector set by using a pre-trained nested attention deep learning model based on the multi-modal quality inspection data set; inputting the defect sensitive feature vector set into a twin network architecture, positioning a potential defect area through a dynamic anchor frame generation mechanism, carrying out multi-label classification on defect types in combination with a Bayesian probability model, and synchronously introducing a defect severity evaluation module to quantify the influence degree of defects on circuit performance, and outputting a detection result containing the defect position type and severity. According to the embodiment of the invention, the collaborative judgment of the type, position and severity of the defect can be realized, and the detection precision and generalization capability of the defect of the multilayer circuit board are improved.

The invention discloses an automatic layout method of a filter chip layout and computer equipment. The method comprises the following steps: reading circuit netlist information of a filter; searching a shortest signal path between input and output of the circuit as a main path, and extracting all circuit elements on the main path; performing initial layout on elements on the main path, and storing coordinates of the elements in a coordinate dictionary; an improved force steering algorithm is adopted to carry out layout on the remaining elements, and coordinates of the elements are stored in a coordinate dictionary; judging whether geometric overlap exists among the elements, if yes, eliminating the geometric overlap through adjustment, and meanwhile, ensuring that the connection relationship of the elements corresponds to the netlist; adding an input / output port and adding a scribing channel at the edge of the chip; and performing design rule check and comparison check of the layout and the schematic diagram, if the check is passed, outputting the layout, otherwise, returning to perform overlap detection and adjustment. The design efficiency can be improved, human errors are reduced, and the circuit performance is optimized.

The invention relates to the technical field of integrated circuit reliability analogue simulation, in particular to an analogue simulation system and method applied to an integrated circuit. The method comprises the following steps: acquiring an integrated circuit layout and carrying out circuit topological structure datamation on the integrated circuit layout to obtain an oxide layer area grid chart; performing stress distribution mapping generation on the integrated circuit according to the oxide layer region grid chart to obtain a region stress state matrix; performing electric field-temperature collaborative analysis according to the regional stress state matrix to obtain a random fluctuation factor matrix; performing time sequence damage accumulation calculation according to the random fluctuation factor matrix to obtain a time sequence damage state set; and performing damage state feedback adjustment on the time sequence damage state set to obtain a time-varying damage evolution graph. According to the method, the fragile performance indexes and areas of the integrated circuit are identified, and the comprehensive circuit performance degradation characteristic spectrum is generated, so that a scientific basis is provided for reliability design and performance optimization of the integrated circuit.

The invention provides a process weak correlation frequency adjustable anti-aliasing filter circuit which is characterized by comprising a current generation module, a current mirror module, a control voltage generation module and an MOSFET-C anti-aliasing filter module. The anti-aliasing filter circuit with the adjustable frequency has the remarkable advantages that the anti-aliasing filter circuit with the adjustable frequency can generate cut-off frequency linearly related to the frequency of an input clock signal, and the anti-aliasing filtering function with the adjustable frequency is achieved. In addition, the circuit can effectively reduce the influence of technological parameters on the cut-off frequency, has good circuit performance, and meanwhile, compared with a cut-off frequency adjusting method of an existing on-chip filter circuit integrated control loop, the circuit is simple in structure, small in introduction power consumption and low in cost. And the anti-aliasing filtering requirement of the ADC acquisition front end within the input clock signal frequency range of 10 kHz to 100 kHz can be met.

This disclosure provides a state switching method, apparatus, and electronic device. The state switching method includes: generating and maintaining a state switching signal when a preset state switching condition is met; switching the state of a target object using the state switching signal; calculating the time interval between the current time and the end time of a synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal; and ending the state switching signal when the time interval meets a preset condition, thus completing the state switching of the target object; the preset condition includes the time interval being an even multiple of a first clock cycle. This embodiment ensures that the output signal of the target object after state switching is synchronized with the synchronization alignment signal, solving the problem of timing disorder and improving circuit performance.