Automatic design optimization method suitable for large-scale analog / radio frequency circuit

Abstract

The invention belongs to the technical field of integrated circuits, and relates to an automatic design optimization method suitable for a large-scale analog / radio frequency circuit, which comprises the following steps of: hierarchically dividing the large-scale analog / radio frequency circuit into a plurality of circuit modules; carrying out random sampling to obtain an initial data set, and establishing a Pareto frontier model of a lower-layer circuit module; the optimization of the performance index of the system circuit is converted into the optimization of the performance index of the lower circuit module; obtaining a'pseudo 'Pareto optimal point near the optimal performance index of each current lower-layer circuit module by using an improved evolutionary algorithm; updating the Pareto front of the lower layer module by using the extracted Pareto optimal point, and performing constraint mapping calculation until the Pareto front of the current lower layer module is partially overlapped with the actual Pareto front; and solving a design variable of the lower-layer circuit module by using the output optimal performance index of the lower-layer module. According to the method, good circuit performance indexes can be obtained with fewer SPICE simulation times, and the cost of automatic design of a large-scale analog / radio frequency circuit is reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to an automated design optimization method suitable for large-scale analog / RF circuits. Specifically, it relates to an improved hierarchical optimization method for automated design of large-scale analog / RF circuits. The main application scenario of this invention is the automated design of large-scale analog / RF circuits. Background Technology

[0002] In recent years, integrated circuits (ICs) have developed rapidly, and their presence can be found in almost every corner of modern society. From satellites and space stations for outer space exploration to mobile phones and earphones that people carry with them, integrated chips play an important role. According to the annual reports of the authoritative Global Semiconductor Alliance, the global semiconductor output value reached $556 billion in 2021, double the figure of the global semiconductor industry in 2007. It can be said that the semiconductor industry is developing very rapidly. However, with the rapid development of integrated circuits, the scale of chips is becoming increasingly larger, and the design difficulty of chips is also gradually increasing, especially for analog / RF circuits that process analog signals. The design of these circuits itself depends on the individual skill of the designer, and the ever-increasing circuit size makes it difficult for even experienced professional designers to complete the design within a limited time. The analog / RF circuits themselves are more difficult to program and configure due to the continuous signals they process. At the same time, the large number of parasitic effects, crosstalk, and external noise in these circuits make their automated design more difficult than that of digital circuits.

[0003] However, in recent years, researchers have continued to propose effective algorithms for the automated design of analog / RF circuits. Two representative approaches are flat optimization methods for small-scale analog / RF circuits and hierarchical optimization methods for large-scale analog / RF circuits. As circuit sizes increase, the application of flat optimization algorithms is diminishing, while hierarchical optimization methods are gaining increasing attention and leading to the development of new automated design algorithms. Hierarchical optimization algorithms first decompose the circuit into multiple circuit modules, transforming the optimization of the performance metrics of the top-level modules into the optimization of the performance metrics of each intermediate-level module. This essentially transforms the automated design of the system circuit into the automated design of individual modules. Since the transistor size of each circuit module is generally relatively small, the values ​​of its design variables can be directly obtained using flat optimization methods.

[0004] It is worth noting that hierarchical optimization algorithms first require establishing the Pareto front of the performance indicators for each circuit module, and extracting a complete Pareto front requires extracting a large number of Pareto optimal points. This actually requires a large number of SPICE simulations, which is computationally expensive. Therefore, reducing the number of SPICE simulations while ensuring the design quality of analog / RF circuits is of great significance for the automated design of large-scale analog / RF circuits.

[0005] Based on the current state of the technology, the inventors of this application intend to provide an automated design optimization method applicable to large-scale analog / RF circuits. Specifically, it is an improved hierarchical optimization method for automated design of large-scale analog / RF circuits. The main application scenario of this invention is the automated design of large-scale analog / RF circuits. Summary of the Invention

[0006] The purpose of this invention is to provide an automated design optimization method suitable for large-scale analog / RF circuits based on the current state of the technology. Specifically, it relates to an improved hierarchical optimization method for large-scale analog / RF circuits. This method makes the following improvements on the traditional hierarchical optimization method, thereby reducing the number of SPICE simulations in the automated design of large-scale analog / RF circuits, and thus reducing the design cost.

[0007] Specifically, the improved hierarchical optimization method of this invention includes an iterative optimization approach based on local Pareto front updates: First, the large-scale analog / RF circuit is hierarchically divided into multiple circuit modules; then, an initial dataset is randomly sampled and used to establish the Pareto front model of the lower-level circuit modules; then, the optimization of the system circuit performance indicators is transformed into the optimization of the performance indicators of the lower-level circuit modules, i.e., constraint mapping; then, an improved evolutionary algorithm is used to obtain "pseudo" Pareto optimal points near the current optimal performance indicators of each lower-level circuit module; the extracted Pareto optimal points are used to update the Pareto front of the lower-level modules, and the constraint mapping is recalculated until the current Pareto front of the lower-level modules partially coincides with the actual Pareto front; finally, the optimal performance indicators of the output lower-level modules are used to solve for the design variables of the lower-level circuit modules. This invention can obtain sufficiently good circuit performance indicators with fewer SPICE simulations.

[0008] More specifically,

[0009] In a first aspect of the present invention, a method for calculating constraint mapping between upper and lower layer circuits is provided, comprising:

[0010] Based on the analog / RF circuit topology, this large circuit is modularized. If the number of transistors in a certain circuit module is still very large after modularization, then that circuit module is further modularized.

[0011] Based on the aforementioned layered results of large-scale analog / RF circuits, a constraint mapping method for upper and lower layer circuits is used to transform the optimization problem of the performance of the upper layer circuit and the performance indicators of the upper and lower layer circuits into the optimization problem of the performance indicators of each lower layer circuit module. The computational model used for constraint mapping is as follows:

[0012]

[0013]

[0014] f j ∈Ω j (j = 1, 2, ..., N) block )

[0015] Where {f1,f2,…,f Nblock} represents the performance index vectors of the lower-level circuit modules, g0(·) and {g i (·); i = 1, 2, ..., N spec} represents the behavioral model of the upper-layer circuit performance metrics with respect to the lower-layer circuit performance metrics, G i The constraint of the i-th performance index of the upper-level circuit, Ω j Let N be the feasible range of the performance indicators of the j-th circuit module in the lower layer. spec N represents the number of performance indicators for the upper-level circuit. block This represents the number of lower-level circuit modules.

[0016] Based on the requirements of the above-mentioned constraint mapping problem, this application proposes an update strategy for the feasible region boundary to avoid the high computational cost of extracting the complete feasible region boundary of the performance index of each circuit module in advance in the traditional hierarchical optimization method.

[0017] Based on the establishment of the feasible region boundary, these parameters are substituted into the constraint mapping of the upper and lower layer circuits. This optimizes the main performance indicators of the upper layer circuit, constraining other performance indicators to a fixed range, while simultaneously constraining the performance indicators of the lower layer module within the feasible region. Solving this optimization problem allows us to obtain the optimal performance indicators of the lower layer circuit module. Using f... A ={f1 A f2 A ,…,f Nblock A} represents the optimal value of the performance index of the lower-level module.

[0018] In a second aspect of the present invention, a method for acquiring "pseudo" Pareto optimal points is provided. This method, based on the optimal values ​​of the performance indicators of lower-level modules obtained from the first aspect of the present invention, uses an improved evolutionary algorithm to extract Pareto optimal points around the optimal performance indicators of each circuit module. This includes:

[0019] Based on the initial sampling point set of the current lower-level circuit module and the optimal value of the performance index of the lower-level module, a Gaussian regression model and corresponding acquisition function are established for each performance index of each circuit module regarding the design variables of the circuit module.

[0020] Based on the Gaussian regression model and acquisition function mentioned above, an improved evolutionary algorithm is used to extract the Pareto optimal points around the performance indicators of the current circuit module.

[0021] When establishing the Gaussian regression model and its corresponding data acquisition function, the following should be included:

[0022] Gaussian regression models are applied sequentially to the lower-level circuit modules, with module j as an example, where j = 1, 2, ..., N. block Assume the performance index of this circuit module is f. j =[f j,1 ,f j,1 ,···,f j,Mj ], of which M j Let be the number of performance indicators for the j-th circuit module.

[0023] Based on dataset D={D j j = 1, 2, ..., N block}, obtain the set of sampling points D for the j-th circuit module. j Assume the number of points in this set is NM. j That is, D. j ={(x j,i ,f j,i ); i = 1, 2, ..., NM j Based on the points in these subsets, a performance index f for the j-th circuit module is established. j Regarding its design variable x j Multiple Gaussian regression models. The Gaussian regression models are GP... j =[GP j,1 GP j,2 , ···, GP j,Mj ].

[0024] Based on the Gaussian regression model between the circuit performance indicators and their corresponding design variables shown above, the model is used to establish the acquisition function, which is UCB. j (f j ) = [UCB j,1UCB j,2 UCB j,Mj ].

[0025] When using improved evolutionary algorithms, including:

[0026] Based on the dataset, the K nearest sampling points to the optimal performance metric of the current mid-layer module are extracted as the initial population, and an evolutionary algorithm is performed. The objective function of this evolutionary algorithm is the sampling function established above. The initial population is used as the parent population, and the following genetic algorithm is executed:

[0027] The parent population is used to generate K new populations through crossover and mutation. In each new population, the objective function value of an individual is determined to be within the range of R, the optimal performance index of the current circuit module. Individuals that do not meet this requirement are removed. When the number of individuals in the new population is less than K, the parent population undergoes crossover and mutation again, generating new individuals that are added to the new population and removing those that do not meet the requirement. This process continues until the number of individuals in the new population exceeds K. The new population is then merged with the parent population, and the K best individuals are selected (this genetic algorithm uses non-dominated sorting to determine the quality of individuals).

[0028] After multiple iterations, the modified evolutionary algorithm generates K optimal individuals and their parent populations. These individuals are then sorted in a non-dominated manner, and the top K individuals are considered "pseudo" Pareto optimal points. They are called "pseudo" Pareto optimal points because the objective function of these points is the sampled function value of the Gaussian regression model, rather than the performance index of the sampled points obtained through actual simulation.

[0029] After obtaining these "pseudo" Pareto optimal points, SPICE simulation can be used to simulate these "pseudo" Pareto optimal points and obtain their actual circuit module performance indicators. The simulated sampling points are then added to dataset D. j In this way, the extraction of a "pseudo" Pareto front for the j-th circuit module is completed.

[0030] By updating the Gaussian regression model and its corresponding sampling function using the new dataset, a more accurate "pseudo" Pareto optimal value can be extracted, and this process can be repeated multiple times. If the number of iterations exceeds a certain threshold, all sampling points used in the SPICE simulation during the iteration process are returned.

[0031] The extraction of the j-th circuit module is as shown above, and the extraction of the "pseudo" Pareto optimal points of other circuit modules is done in the same way.

[0032] In a third aspect of the present invention, a method for updating a local Pareto front is provided, comprising:

[0033] Based on the initial dataset, Pareto optimal points of performance indicators are extracted from the data subset corresponding to the lower-level circuit modules, and the obtained Pareto optimal points are modeled as Pareto frontier function models.

[0034] Based on the Pareto frontier function model obtained above, the optimal values ​​of the performance indicators of each of the current lower-level circuit modules are obtained by using the constraint mapping method.

[0035] Based on the optimal performance index values ​​of each lower-level circuit module obtained from the above, Pareto optimal points are extracted near the optimal performance index values ​​of each lower-level module.

[0036] Based on the Pareto optimal point obtained above, the Pareto front function model is updated to make it closer to the actual Pareto front in a local range.

[0037] Based on the updated Pareto front, the constraint mapping method is used again to obtain the optimal solution for the performance index of the current lower-level module. This process is iterated until the iteration exit condition is met.

[0038] When obtaining the Pareto optimal point based on the initial dataset, we have:

[0039] The initial dataset D is divided into multiple sub-datasets, each representing a set of sampling points for a lower-level circuit module;

[0040] For each circuit module, Pareto optimal points are selected individually. After selecting the Pareto optimal points, these Pareto optimal points are modeled using linear or nonlinear methods to form the current Pareto front.

[0041] Because the number of Pareto optima extracted initially is relatively small, the Pareto front modeled above differs significantly from the actual Pareto front. Therefore, it can be called a "pseudo" Pareto front.

[0042] When using constraint mapping to obtain the optimal performance metrics of each lower-level circuit module, we have:

[0043] Based on the "pseudo" Pareto front obtained above, the feasible region constraint in the upper and lower layer circuit constraint mapping can be replaced by the Pareto front constraint to obtain the optimal performance index of the current lower layer module.

[0044] Taking the j-th circuit module as an example, assume it has two performance indicators, namely fj = [f j,1 ,f j,2 The constraint mapping of the top-level circuit performance index to this circuit module can be expressed by the following formula:

[0045]

[0046] stgi (f j ) < G i (i = 1, 2, ..., N) spec )

[0047] f j,2 ≥p j,0 (f j,1 )

[0048] p in the appeal formula j,0 The feasible region boundary is defined by the performance index of the lower-level circuit module, and all points on the feasible region boundary satisfy f. j,2 =p j,0 (f j,1 When the requirements of the above formula are met, it means that the performance index optimized by the formula is within the feasible region. Calculating the above formula yields the optimal performance index of the current i-th module, which is fj. A .

[0049] When searching for "pseudo" Pareto maxima near the current Pareto maxima of each circuit module, we have:

[0050] Based on the current optimal performance index of each module obtained above, the first aspect of the implementation of this patent is used, namely the extraction of the “pseudo” Pareto optimal point of the lower circuit module.

[0051] When updating the Pareto frontier function model after obtaining the Pareto optimal point, we have:

[0052] Based on the Pareto optimal points obtained above, Pareto front simulations are performed using linear or nonlinear methods. Since the extracted Pareto optimal points are generally located within a certain range of the current circuit module's performance indicators, the actual update of the Pareto front will typically involve significant changes within a local range. The obtained new Pareto front will be used in the constraint mapping calculations for the upper and lower layer circuits in the next iteration.

[0053] The appeal loop continues until the updated Pareto front and the actual Pareto front are locally coincident, and then the loop ends. Since the actual Pareto front cannot be obtained directly, in practice, when the results of the two upper and lower level constraint mappings are similar, it can be regarded as the current Pareto front and the actual Pareto front being partially coincident.

[0054] In a fourth aspect of the present invention, a method for calculating lower-level circuit design variables in upper-lower-level circuit constraint mapping is provided, comprising:

[0055] Based on the third aspect of the implementation method of this invention, the optimal performance indicators of the lower-level circuit module can be obtained. The design parameters of the lower-level circuit module can be determined using either a multi-objective optimization simulation method or a model-based optimization method.

[0056] In the implementation method of this invention, a model-based optimization method is used. A Gaussian model between the performance indicators of the lower-level circuit module and the design variables is established through an initial dataset, and the lower-level variables are calculated by optimizing the model.

[0057] This invention provides an automated design optimization method suitable for large-scale analog / RF circuits. This method improves upon the traditional hierarchical optimization method, thereby reducing the number of SPICE simulations and lowering design costs in the automated design of large-scale analog / RF circuits. Attached Figure Description

[0058] Figure 1 This is a flowchart of the algorithm of the present invention.

[0059] Figure 2 This is a schematic diagram of the PLL circuit layering used as an exemplary method in the present invention.

[0060] Explanation of reference numerals in the attached diagrams: PFD sub-circuit module in 201-PLL circuit, CP sub-circuit module in 202-PLL circuit, and VCO sub-circuit module in 203-PLL circuit. Detailed Implementation

[0061] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0062] Example 1 Exemplary methods

[0063] like Figure 2 As shown, this exemplary method will employ a phase-locked loop (PLL) circuit to describe the automated design method of this invention. The main function of the PLL circuit is to generate an output clock signal that is phase-locked with the input clock; this circuit belongs to a relatively large-scale analog circuit. For example... Figure 2 As shown, this phase-locked loop (PLL) circuit can be divided into six lower-level circuit modules: a phase-frequency detector (PFD), a charge pump (CP), a low-pass filter (LF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV). The optimization of the sub-circuits mainly focuses on the PFD sub-circuit module in the 201-PLL circuit, the CP sub-circuit module in the 202-PLL circuit, and the VCO sub-circuit module in the 203-PLL circuit, as shown in the figure.

[0064] For the PFD module of 201, six design variables (design variables generally refer to some parameters of the undetermined components in the circuit module, such as the transistor size and the values ​​of resistors and capacitors) are extracted as variables to be optimized, namely: x 1 =[x1 1 ,…,x6 1 Extract two performance indicators from its circuit module, namely f 1 =[f1 1 f2 1 For the CP circuit module of 202, 15 design variables of its circuit module are extracted as variables that need to be optimized, namely x. 2 =[x1 2 ,…,x 15 2 At the same time, two performance indicators of its circuit module were extracted, namely f 2 =[f1 2 f2 2 For the final circuit module (the VCO circuit module of 203), three design variables of its circuit module are extracted as variables that need to be optimized, namely: x 3 =[x1 3 ,…,x3 3 Simultaneously, three performance indicators of its circuit module were extracted as f 3 =[f1 3 f2 3 f3 3 ].

[0065] based on Figure 2 The layered operation of the circuit modules shown first involves extracting the initial dataset. For the three sub-circuit modules, the values ​​of their design variables are randomly obtained, and all 24 design variables are used as a sampling point. SPICE simulation is then used to obtain the performance indicators of the three circuit modules at this sampling point, as well as the system's performance indicators. N random sampling points are extracted as the initial dataset {D}. j,0 ;j=1,2,3}, where D j,0 ={(x j n ,f j n );n=1,2,···,N}. j represents three lower-level circuit modules.

[0066] Based on the initial dataset D obtained above j,0 Extract D j,0 The Pareto optimal points corresponding to each module are modeled using linear or nonlinear methods to form the Pareto front of the performance index of each module. These Pareto fronts are expressed using f.j,0 =p j (f j,1 ,···,f j,Mj-1 ) indicates that M in it j Let be the number of performance metrics for the j-th circuit module. By substituting all Pareto fronts into the following formula, we can obtain the optimal performance metrics values ​​for each lower-level circuit module calculated using the current Pareto front model and constraint mapping.

[0067]

[0068] stg i (f j ) < G i (i = 1, 2)

[0069]

[0070] As shown in the formula above, the PLL circuit has three system performance indicators, two of which, g1 and g2, serve as constraints on the performance indicators. The optimization objective of the entire constraint mapping is g0. The other constraint in this optimization is the Pareto front of each module as modeled above. This constraint mapping obtains the current optimal performance indicator for each of the three lower-level circuit modules, denoted by {f}. j A ;j=1,2,3} represents.

[0071] Based on the optimal performance metrics obtained for each module, an improved evolutionary algorithm will be used to extract "pseudo" Pareto optima around them, which includes:

[0072] Based on the initial dataset D j,0 ={(x j n ,f j n (n = 1, 2, ..., N) Using these data, a mapping relationship is established between the performance indicators of the lower-level module circuit and its circuit design variables. This mapping is modeled using a Gaussian regression model. (GP) j =[GP j,0 GP j,1 , ···, GP j,Mj-1 ] represents the Gaussian regression model. M jLet [M0, M1, M2] = [2, 2, 3] represent the number of performance metrics for the j-th circuit module. In this example, [M0, M1, M2] = [2, 2, 3]. After establishing the Gaussian regression model corresponding to the performance metrics of each module, the Pareto optimal point corresponding to the current Gaussian regression model of each circuit module will be extracted using the maximum confidence boundary acquisition function. Since the number of Pareto optimal points is not unique, it is necessary to extract suitable Pareto optimal points. Furthermore, this problem is essentially a multi-objective optimization problem. The improved evolutionary algorithm used in this invention obtains suitable Pareto optimal points. This improved evolutionary algorithm is based on the second-generation non-dominated sorting evolutionary algorithm (NSGA-II), where non-dominated sorting is the method for determining the priority of Pareto optimal points. In this example, the extraction of Pareto optimal points is based on the Gaussian regression model of the performance metrics of each circuit module. These Pareto optimal points have not undergone actual SPICE simulation and are therefore called "pseudo" Pareto optimal points. Simultaneously, the "pseudo" Pareto optimal points extracted in this invention need to be around the optimal performance metrics of the current module, which are obtained based on the constraint mapping between the upper and lower layer circuit modules mentioned above.

[0073] The evolutionary algorithm flow for improving the above-mentioned single circuit module is shown below, taking the PFD module of 201 as an example:

[0074] Based on the initial dataset D 1,0 Select the performance index f1 that is closest to the current PFD. A The most recent N sampling points are used as the initial population for optimization of the NSGA-II evolutionary algorithm. The initial population is used as the parent population for evolutionary operations. First, new populations are generated through crossover and mutation operations. During the crossover and mutation process, based on the need for extracting local "pseudo" Pareto optima in this method, the newly generated offspring are substituted into a Gaussian regression model to solve whether their distance from f1 is significant. A Within a certain range, if the constraints are not met, offspring will be generated again. The number of newly generated offspring is also set to N. The generated offspring are merged with the parent population, and the N individuals with the highest priority are formed into a new parent population for the next round of evolution. This process is repeated until N "pseudo" Pareto optimal points that satisfy the constraints are obtained.

[0075] The priority comparison described above is a characteristic of NSGA-II. First, the individuals in the population are divided into Pareto levels. All Pareto optima in the current population are assigned to Pareto level 1. After excluding individuals of Pareto level 1, the remaining Pareto optima are assigned to Pareto level 2, and so on. This method requires a fixed number of high-priority individuals, therefore priority sorting is performed within each Pareto level. The NSGA-II algorithm typically uses crowding as a comparison method. Crowding is the sum of the length and width of the rectangle formed by the two Pareto optima of the same level to the left and right of the current Pareto optima. The larger this sum, the higher the priority of the Pareto optimum. The leftmost and rightmost Pareto optima of the same level have the highest crowding and therefore the highest priority.

[0076] Based on the above method for extracting "pseudo" Pareto optimal points, these "pseudo" Pareto optimal points are subjected to SPICE simulation, and the simulated data points are added to dataset D. 1,0 Meanwhile, the performance metrics of the PFD circuit module are updated using the Gaussian regression model based on these new data points.

[0077] The above process is an iterative process of Bayesian optimization based on Gaussian regression, where the Bayesian optimization data collection utilizes an improved evolutionary algorithm. After multiple iterations, a certain number of local Pareto optima are obtained in the current PFD module's Gaussian regression model. The points generated in this Bayesian optimization process, after being simulated using SPICE, contribute to the high accuracy of the Gaussian regression model within a local range.

[0078] Based on the "pseudo" Pareto optimal point obtained above, update the dataset D. 1,0 The Pareto optimal points in the current dataset are then selected again. Using these Pareto optimal points, a linear or nonlinear model is employed to model the Pareto front of the performance metrics of the current PFD module, thus achieving the goal of updating the Pareto front. Since the newly obtained Pareto optimal points are closer to the actual Pareto front in a local range, the feasible region of the updated PFD module's performance metrics is expanded.

[0079] Based on the new Pareto front of the circuit module performance indicators obtained above, the constraint mapping calculation of the upper and lower layer circuit performance indicators is performed again to obtain the optimal performance indicator {f} of the new module circuit. j B If j = 1, 2, 3}, and this iteration continues, the Pareto front of the module circuit performance index will gradually approach the actual Pareto front in a local range.

[0080] Based on the above iterative process, since the actual Pareto front cannot be obtained in advance, the termination condition of the above iteration is transformed into the following: the difference between the optimal performance indicators obtained in the two iterations is not large, which means that the current Pareto front model is close to the actual Pareto front in a local range, and the process terminates.

[0081] Based on the above algorithm flow, the optimal performance index of each circuit module is finally obtained, using {f j opt ;j=1,2,3} represents.

[0082] Based on the optimal performance metrics of each circuit module, a Gaussian regression model is established using the current datasets of each module to connect their respective performance metrics to the underlying design variables. Based on this model, the underlying design variables that best represent the performance metrics of each module are obtained. These design variables are then used as the final optimized design, and system-level simulation is used to obtain the top-level design performance metrics of this final design.

Claims

1. An automated design optimization method suitable for large-scale analog / RF circuits, characterized by: Based on the iterative optimization approach of local Pareto front updates, the system performance indicators of large-scale analog / RF circuits are optimized using the following method: Large-scale analog / RF circuits are layered and divided into multiple circuit modules; Based on the above large-scale circuit layering, the performance index optimization problem of the system circuit is transformed into the performance index optimization problem of each lower-level circuit module by using the constraint mapping method of the performance index of the upper and lower layer circuits. Based on the constraint mapping described above, the optimal performance indicators of each lower-level circuit module are obtained. Due to computational cost constraints, a constraint mapping is achieved by using the local Pareto front iteration method of circuit modules to find a "pseudo" Pareto optimal point near the optimal value of the current lower-level circuit module's performance index. Based on the "pseudo" Pareto optimal point obtained above, linear or nonlinear methods are used to update the Pareto front of the lower-level circuit module. Based on the above Pareto front update strategy, an iterative approach is used to continuously obtain the Pareto optimal point of the performance index of the lower-level circuit module, and the obtained Pareto optimal points are all within a certain range of the current optimal performance index of the lower-level circuit module; then, constraint mapping is continuously performed, and finally the updated Pareto front coincides with the actual Pareto front within a certain range. Based on the fact that the updated Pareto front coincides with the actual Pareto front within a certain range, the optimal performance index of the lower-level circuit module at this time is taken as the optimization objective. The values ​​of the design variables corresponding to each lower-level circuit module are calculated. The optimized design variables are those that make the simulation results of the lower-level circuit module close to the optimal performance index mentioned above.

2. The automated design optimization method according to claim 1, characterized in that, An iterative approach is used instead of the complete Pareto front used in traditional hierarchical optimization methods, which includes: Based on the initial dataset, the current Pareto optimal points are extracted and modeled as the current Pareto front. Since the number of points in the initial dataset is relatively small, the feasible region of the lower-level circuit module is relatively small, and the obtained optimal performance index of the lower-level module is poor. An improved evolutionary algorithm is used to search for "pseudo" Pareto optimal points within a certain range of the current optimal performance index of these lower-level circuit modules and add them to the dataset. Then, a new Pareto front of the lower-level circuit module is remodeled. This iterative process achieves the goal of obtaining the optimal design of the lower-level circuit module without extracting the complete Pareto front.

3. The automated design optimization method according to claim 2, characterized in that, Using constrained optimization computation to replace constraint mapping between upper and lower layer circuits includes: The constraint mapping between upper and lower layer circuit modules is transformed into a constrained optimization problem, as shown in the following formula: f j ∈Ω j (j=1,2,L,N block ) In this formula, a certain performance index of the system circuit is taken as the optimization target, and other performance indexes are taken as constraints. At the same time, in order for the performance index of the lower-level circuit module mapped by the constraints to be actually realized, the performance index of the mapped lower-level circuit module must be within the feasible domain of the performance index of its lower-level circuit module.

4. The automated design optimization method according to claim 2, characterized in that, An improved evolutionary algorithm is used to extract the "pseudo" Pareto optimal point of the performance index of the lower-level circuit module, which includes: Based on the optimal values ​​of the current lower-level circuit module's performance indicators obtained above, an improved evolutionary algorithm is used to find suitable Pareto optimal points around them. The improved evolutionary algorithm uses Bayesian optimization and the traditional NSGA-II algorithm to extend Bayesian optimization to a multi-objective level. In this method, Gaussian modeling is first performed on the performance indicators of each lower-level circuit module. After modeling, the acquisition function with the highest confidence interval is used to find "pseudo" Pareto optimal points. Since there are multiple performance indicators of the lower-level circuit modules, a multi-objective algorithm like NSGA-II is needed to achieve optimization. During the process of using the improved evolutionary algorithm, the generated "pseudo" Pareto fronts are used for SPICE simulation to obtain the performance indicators of their corresponding circuit modules, and these points are put into a set for output.

5. The automated design optimization method according to claim 4, characterized in that, Among them, the use of The obtained "pseudo" Pareto optimal point is used to update the Pareto front of the performance index of the lower-level circuit module, which includes: Based on the above, by using the improved evolutionary algorithm, new "pseudo" Pareto optimal points are output for each lower-level circuit module. These optimal points are added to the set initially used to extract the true Pareto optimal points. The definition of Pareto optimal points is used again to obtain all the true Pareto optimal points in the current set. These true Pareto optimal points are modeled in a linear or nonlinear manner to update the Pareto front. This front will be used in the constraint mapping calculation between the upper and lower-level circuit modules in the next iteration.

6. The method according to any one of claims 1 to 4, characterized in that, The method also includes: constraint mapping calculation and Pareto front update algorithm, which uses an iterative approach to continuously refresh the results of constraint mapping calculation until the optimal performance index of the lower-level circuit module is obtained, and the value of the design variable of the lower-level circuit module is calculated based on the performance index.

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