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1422results about "Frequency selective two-port networks" patented technology

System and method for linearizing a CMOS differential pair

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
Owner:AVAGO TECH INT SALES PTE LTD

Integrated frequency selectable resonant coupling network and method thereof

An integrated center frequency selectable resonant coupling network suited for use in an integrated circuit is disclosed. The network includes an integrated coupling transformer having a secondary winding for coupling to a load and a primary winding for coupling to a source; a first integrated capacitive circuit controllably coupled across one of the primary and secondary windings and when so coupled operable to resonate with the integrated coupling transformer at a frequency in a first frequency band; and a second integrated capacitive circuit coupled across a second one of the primary and the secondary windings that is operable to resonate with the integrated coupling transformer at a frequency in a second frequency band. The method is in an IC and includes providing and coupling an input signal within alternatively a first frequency band and a second frequency band to a primary winding of an integrated coupling transformer; controlling an integrated switched capacitor network, coupled to the transformer, to provide a coupling network that is alternatively and respectively resonant at a first and second frequency within the first and second frequency band thus selectively providing an output signal at a secondary winding of the transformer; and down converting the output signal.
Owner:APPLE INC

Integrated spiral inductor

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH INT SALES PTE LTD

Controlling Q-factor of filters

The present invention provides a method and an apparatus for controlling a Q-factor for a filter. The method comprises stabilizing an active feedback to provide a variable feedback in a filter, varying the active feedback based on an input signal to the filter, and producing a desired Q-factor for the filter at a first frequency band, in response to the variable feedback. The method further comprises reconfiguring a center frequency and a bandwidth of the filter based on a channel bandwidth of the input signal to the filter to adjust the Q-factor for the filter in response to a second frequency band different than the first frequency band. By reconfiguring a center frequency and a bandwidth of a filter, the Q-factor for the filter, such as a flexible or reconfigurable filter, may be controlled across a multiplicity of frequency band signals. Using software, for example, a common signal path may be provided for the multiplicity of frequency band signals within a frequency agile radio of a base station by tuning the radio based on a variable feedback through realization of a negative parallel resistance. Thus, tuneability of the Q-factor may provide frequency agile radios that include flexible or reconfigurable filters in a base station to serve different frequency bands without changing hardware. In this way, significant savings associated with frequency agility may be obtained.
Owner:WSOU INVESTMENTS LLC +1

System and method for ESD protection

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE

Filter trimming

The invention relates to trimming of analogue filters (201) in integrated circuits by means of an automatic adjusting circuit. A local oscillator (202) in the automatic adjusting circuit provides a periodic reference signal (R) to an adjustable phase shifter (203), which on basis thereof, produces a periodic phase shifted signal (R*). A phase detector (204) receives both the periodic reference signal (R) and the phase shifted period signal (R*) and produces a test signal (T) in response to a phase difference between the periodic reference signal (R) and the periodic phase shifted signal (R8). A lowpass filter (205) receives the test signal (T) and generates a level signal (TDC) relative a reference level, e.g. representing a zero voltage. A digital signal processor (207) produces a primary control signal (CS), having a serial format, on basis of the observation signal (M). A serial-to-parallel converter (208) converts the primary control signal (CS) into a control signal (CP) having a parallel signal format. The control signal (CP) influences a magnitude of at least one component value in the adjustable phase shift between the periodic reference signal (R) and the periodic phase shifted signal (R*) attains a calibrated value being as close as possible to a desired value. A latch (210) forwards at least one signal element of the control signal (CP) for setting of at least one component value in the analogue filter (201) in accordance with a setting of at least one component value in the adjustable phase shifter (203) which produces the calibrated value.
Owner:NAT SEMICON CORP
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