22results about "Computing operations for integration/differentiation" patented technology

The invention provides an ultrasonic fingerprint chip and an integral clock generation method and device of the ultrasonic fingerprint chip. Appropriate fingerprint pixel units can be selected from a plurality of fingerprint pixel units to serve as first-class pixel units and second-class pixel units, and the first-class pixel units and the second-class pixel units are respectively connected with a first-class detection circuit and a second-class detection circuit. Wherein a first integrator in the first type of detection circuit is sequentially connected with a first comparator, a time delay regulator, a clock dominant frequency duplicator and a frequency dividing circuit; the frequency dividing circuit is connected with the second type detection circuit; a second integrator in the second type detection circuit is connected with an amplification structure; the amplification structure is also connected with a second comparator; and the second comparator is connected with the time delay regulator in the first-class detection circuit. The circuit can automatically generate and obtain the integral clock signal which is matched with the ultrasonic fingerprint echo signal and is high in precision and good in effect, so that the received ultrasonic fingerprint echo signal is precisely processed, and a target signal with high quality is obtained.

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

A current-integrating summing circuit is provided, and may include a first capacitor and a second capacitor to integrate an input current over time, a first pair of transistors to receive a differential pair of input signals, a second pair of transistors to receive a common-mode voltage, a third pair of transistors and a fourth pair of transistors respectively configured in a cascode formation relative to the first pair of transistors and the second pair of transistors, and a pair of complementary clocks to activate the third pair of transistors to enable charging of the first and second capacitors according to the differential pair of input signals during an integration phase, wherein the pair of complementary clocks are to activate the fourth pair of transistors to enable discharging of the first and second capacitors during a reset phase.

A circuit and method for measuring an average current of a solenoid valve, relating to the technical field of automotive electronics. The circuit comprises a solenoid valve (110), a first power supply (120), a sampling resistor, a field effect transistor drive circuit (130), a current acquisition circuit (140), an integrator circuit (150), and an integration reset circuit (160); the field effect transistor drive circuit (130) is used for controlling an on-off state of a first field effect transistor on the basis of a pulse width modulation gating signal; the first power supply (120) is used for providing a drive current for the solenoid valve (110) when the first field effect transistor is in an on state, and the drive current flows through the sampling resistor; the current acquisition circuit (140) is used for sampling voltage signals on two sides of the sampling resistor, and outputting the voltage signals to the integrator circuit (150); the integrator circuit (150) is used for performing integration processing on the voltage signals, and determining an average current of the solenoid valve (110) on the basis of an integration result; and the integration reset circuit (160) is used for performing periodic reset processing on the integrator circuit (150) on the basis of the pulse width modulation gating signal.

This application provides an output amplifier circuit and an arbitrary waveform generator, belonging to the field of electronic circuit technology. The output amplifier circuit includes: a radio frequency amplifier circuit, including a first common-emitter amplifier sub-circuit and a second common-emitter amplifier sub-circuit, for amplifying high-frequency signals in the AC input signal from the input node; the second common-emitter amplifier sub-circuit includes a second transistor, the collector of which is connected to the output node through a current-sampling resistor; an output bias voltage circuit for superimposing an output bias voltage onto the output node; a static bias voltage circuit for providing a static bias voltage to the second transistor and outputting a reference voltage to the integrator circuit; a feedback amplifier circuit for outputting a feedback signal based on the static operating current of the second transistor; and an integrator circuit for outputting an integrated signal based on the reference voltage and the feedback signal. This output amplifier circuit can solve the problems of small output bias voltage range and performance degradation in ultra-high bandwidth AWGs.

Disclosed is an apparatus for computationally intensive applications, such as information technology applications requiring computational power. Disclosed is an apparatus arranged to provide an analog signal to at least one input of an analog compute-in-memory resistive matrix comprised in said apparatus, and to receive a digital signal from at least one direct-drive analog-to-digital converter in the output of said at least one analog compute-in-memory resistive matrix.

This specification provides an ultrasonic fingerprint chip, a method for generating an integrating clock for the ultrasonic fingerprint chip, and an apparatus. Suitable fingerprint pixel units can be selected from multiple fingerprint pixel units as a first type of pixel unit and a second type of pixel unit, and then connected to a first type of detection circuit and a second type of detection circuit, respectively. In the first type of detection circuit, a first integrator is sequentially connected to a first comparator, a time delay adjuster, a clock frequency replicator, and a frequency divider circuit; the frequency divider circuit is connected to the second type of detection circuit. In the second type of detection circuit, a second integrator is connected to an amplification structure; the amplification structure is also connected to a second comparator; the second comparator is connected to the time delay adjuster in the first type of detection circuit. This circuit can automatically generate an integrating clock signal with high accuracy and good performance that is adapted to the ultrasonic fingerprint echo signal, thereby accurately processing the received ultrasonic fingerprint echo signal and obtaining a high-quality target signal.

The invention relates to the technical field of electric data processing and intelligent algorithms, in particular to an image processing projection scaling optimization method and system based on the symplectic manifold acceleration technology. The method comprises the following steps: for a constraint minimization problem corresponding to an image deblurring or binary classification scene, solving the constraint minimization problem by adopting a zoom gradient projection algorithm to obtain an image deblurring result or a classification result; and a second-order symplectic integrator is introduced to perform position updating and momentum updating in the process of solving the constraint minimization problem by adopting the zoom gradient projection algorithm, so that the convergence efficiency of solving the constraint minimization problem by adopting the zoom gradient projection algorithm is improved.

The invention belongs to the technical field of chaotic circuits, and discloses a sine nonlinear characteristic-based third-order circuit system, which comprises a sine nonlinear function circuit and a third-order linear differential equation circuit, the input end of the sine nonlinear function circuit is connected with the x output end of the third-order linear differential equation circuit, and the output end of the sine nonlinear function circuit is connected with the x output end of the third-order linear differential equation circuit. The output end is connected with one input end of the x integrator of the third-order linear differential equation circuit; the sine nonlinear function circuit is composed of a first operational amplifier A1, resistors R1 to R16 and diodes D1 to D6, and the output and the input of the sine nonlinear function circuit are in a sine nonlinear function relationship; the third-order linear differential equation circuit forms three anti-phase addition integrators by three anti-phase operational amplifiers, three capacitors and seven resistors, and the sine nonlinear function circuit provides nonlinear signals to generate three Chua's chaotic signal outputs of the sine nonlinear third-order Chua's circuit; according to the invention, various chaotic line systems and chaotic secret communication systems can be formed.

The invention relates to a readout circuit and a readout chip of a detector. The readout circuit comprises at least one readout channel, and the readout channel comprises a charge sensitive pre-amplification circuit which is connected with a detector and is used for amplifying a charge signal output by the detector and outputting an initial voltage signal; the active shaping filter circuit is connected with the charge sensitive pre-amplification circuit and is used for receiving a control signal, carrying out filtering shaping processing on an initial voltage signal under the action of the control signal and outputting a shaping signal; the time constant of the active shaping filter circuit is regulated and controlled by the control signal; and the screening circuit is connected with the active shaping filter circuit and is used for receiving a preset voltage signal, comparing the shaping signal with the preset voltage signal and outputting a digital level signal according to a comparison result. The reading circuit has the advantage of being high in reading precision.

The utility model discloses an integrator and a chip. The integrator comprises an operational amplifier, a first switch group, a first sampling capacitor group, a second switch group, an integrating capacitor group, a third switch assembly and an adjusting capacitor group. The first switch group is used for controlling the first sampling capacitor group to perform charge acquisition on a first input signal in a sampling stage; the second switch group is used for controlling the integrating capacitor group to receive charges on the first sampling capacitor group in a conversion stage; the integrating capacitor bank is connected with the input end of the operational amplifier and the output end of the operational amplifier so as to cooperate with the operational amplifier to perform charge integration in a conversion stage; the adjusting capacitor bank is connected with the input end of the operational amplifier through the third switch assembly so as to cooperate with the integrating capacitor bank to adjust the loop bandwidth in the sampling stage. According to the integrator and the chip provided by the utility model, the loop bandwidth of the integrator in a sampling stage in a high-speed and high-precision application is reduced, so that the stability of the integrator in the high-speed and high-precision application is improved.

Control apparatus, control method, power supply, and computer-readable storage medium are disclosed. A power supply includes a primary winding, a secondary winding, a switch, and a controller. The secondary winding is magnetically coupled to the primary winding. The switch is coupled to the secondary winding and controls a state of current through the secondary winding. The controller controls the state of the switch based on an integrator voltage derived from monitoring a voltage from the secondary winding. For example, the controller activates the switch to an on state in response to detecting a condition in which a magnitude of the monitored voltage of the secondary winding crosses a threshold, such as a magnitude of an output voltage generated from the secondary winding.

To provide an electronic circuit that reduces power consumption.SOLUTION: The present invention relates to an electronic circuit including a spike generation circuit of which internal state depends on the history of an input current input to an input terminal and which outputs a single spike signal to an output terminal and resets the internal state to an initial value when the internal state reaches a threshold, and a wireless communication circuit that receives the single spike signal from the spike generation circuit and outputs electromagnetic waves to an antenna.SELECTED DRAWING: Figure 86

The invention belongs to the field of chaotic circuits, and particularly discloses a chaotic system based on a double-charge-control memristor model, which comprises a driving force module, an integral summation reverse module and a multiplication module, the integral summation reverse module comprises a first summation circuit, a first integral circuit, a second summation circuit, a second integral circuit, a first reverse circuit and a third integral circuit, the multiplication module comprises multipliers A1-A4 and a third integral circuit, and the multiplier A3 and the multiplier A4 form a charge-controlled memristor model and are used for enhancing the nonlinearity and noise immunity of the chaotic system. According to the invention, the charge-controlled memristor model is introduced into a Van der Pol-Duffing chaotic system structure, a chaotic system circuit with complex dynamic characteristics is successfully constructed, and the circuit can be suitable for a weak signal detection scene with a low signal-to-noise ratio and high precision.

The utility model provides an MEMS optical switch control device comprising a channel calibration table used for providing MEMS optical switch channel initial control voltage parameters; the cosine signal source is used for generating a cosine modulation voltage signal; the summator is used for superposing the initial control voltage, the cosine modulation voltage and the feedback adjustment voltage and then outputting the superposed voltage to the MEMS optical switch; the detection photodiode is used for receiving the optical signal output by the MEMS optical switch channel N and outputting a conversion power signal after photoelectric conversion; the multiplier is used for coherent amplification of the cosine modulation voltage signal and the conversion power signal and outputting a coherent signal; the first filter is connected with the multiplier, obtains the coherent signal, filters the frequency multiplication component of the coherent signal and outputs a direct current component; the integrator is used for obtaining the direct current component and integrating the obtained direct current adjustment amount as feedback adjustment voltage to be output to the summator; and the feedback adjustment voltage is output to the MEMS optical switch through the summator, so that compensation of a channel control voltage signal is realized.

The invention provides an output amplification circuit and an arbitrary waveform generator, and belongs to the technical field of electronic circuits. The output amplification circuit comprises a radio frequency amplification circuit which comprises a first common emitter amplification sub-circuit and a second common emitter amplification sub-circuit and is used for amplifying a high-frequency signal in an alternating current input signal from an input node; the second common-emitter amplification sub-circuit comprises a second transistor, and a collector of the second transistor is connected with the output node through a current sampling resistor; the output bias voltage circuit is used for superposing an output bias voltage to an output node; the static bias voltage circuit is used for providing static bias voltage for the second transistor and outputting reference voltage to the integrating circuit; the feedback amplification circuit is used for outputting a feedback signal according to the static working current of the second transistor; the integral circuit is used for outputting an integral signal according to the reference voltage and the feedback signal; the output amplification circuit can solve the problems that the output bias voltage range of an ultra-high bandwidth AWG is small and the performance is deteriorated.

The invention provides a closed-loop fully-differential modulation circuit, circuit architecture and electronic equipment, and the circuit architecture comprises a fully-differential integrator, a subtracter, a comparator, a power amplification module and a feedback module, and the subtracter carries out the subtraction of a first output signal and a second output signal outputted by the fully-differential integrator to obtain a differential signal. The residual PWM high-frequency signal between the first output signal and the second output signal is greatly suppressed, so that harmonic distortion caused by a harmonic component generated when the residual PWM high-frequency signal is compared with a carrier triangular wave is avoided. And the comparator compares the differential signal output by the subtractor with the carrier triangular wave signal to obtain a pulse width modulation signal. And the power amplification module obtains a first amplification signal and a second amplification signal according to the pulse width modulation signal and outputs the first amplification signal and the second amplification signal. And the feedback module feeds back the first amplification signal and the second amplification signal to the fully differential integrator.

This disclosure relates to a low-power integrator for a continuous-time ΔΣ analog-to-digital converter (ADC). The integrator includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, an operational transconductance amplifier, a first capacitor, a second capacitor, and a third capacitor. In this embodiment, the integrator controls the opening and closing of the first to eighth switches to alternately utilize either the first or second capacitor. The integrated charge accumulated by the input current over a certain time period is directly "poured" onto the third capacitor of the integrator. Integration is achieved through charge sharing between the first or second capacitor and the third capacitor. This eliminates the need for the operational transconductance amplifier to provide a large current to charge the integrating capacitor, reducing the requirement for high-performance active devices and lowering the integrator's power consumption, thereby contributing to a reduction in the power consumption of the continuous-time ΔΣ ADC.

The present disclosure relates to a dynamic integration time controller for time-of-flight ranging systems. According to embodiments, a system can dynamically control the integration time in a time-of-flight (ToF) device based on the current operating state. A signal scaler processes calibration data and real-time measurements to determine the desired signal and ambient rate. Parallel calculations determine the desired integration time, one based on achieving maximum ranging distance and the other based on the measurement accuracy requirements. The system selects the longer integration time and applies user-defined bounds to optimize power consumption while maintaining specified performance. By adapting the integration time to ambient light conditions and target reflectivity characteristics, the system is able to shorten the integration time in favorable conditions while automatically increasing the duration when needed for long distances or low reflectivity targets.

The invention discloses a magnetic suspension multi-span rotor balance correction method and system, and relates to the technical field of magnetic suspension rotor dynamic balance, and the method comprises the steps: constructing an SOGI-FLL-WIF same-frequency tracking model, and extracting the amplitude and phase of the first frequency multiplication of the rotating speed in real time; acquiring an initial vibration displacement vector at the two measurement cross sections under the conditions of a unified key phase zero point and a stable rotating speed; respectively applying a trial weight to the two measurement sections and remeasuring, calculating four influence coefficients according to a complex vector difference before and after the trial weight and the mass of the trial weight, and establishing a linear equation set to solve two correction counterweights; and weighting according to equal-angle hole sites to finish correction. The method has robustness to slow drifting of the rotating speed, frequency doubling and noise, and amplitude-phase input is stable; under the same vibration control target, the trial weight frequency and the debugging time can be reduced, and residual vibration and bearing stress fluctuation are reduced; the angle and the mass caliber are unified, recording tracing and multi-round iteration are facilitated, precision and repeatability are improved, and the method is suitable for transformation of an existing magnetic suspension test bed and an engineering device.

The invention provides a fully-differential closed-loop modulation circuit, circuit architecture and electronic equipment, and the circuit architecture comprises a fully-differential integrator, a subtracter, a comparator, a power amplification module and a feedback module, and the subtracter carries out the subtraction of a first integral signal and a second integral signal outputted by the fully-differential integrator, so as to obtain a differential signal. The residual PWM high-frequency signal between the first integral signal and the second integral signal is greatly suppressed, so that harmonic distortion caused by a harmonic component generated when the residual PWM high-frequency signal is compared with the carrier triangular wave signal is avoided. A driving unit and a half-bridge unit in the power amplification module output a first amplification signal according to a pulse width modulation signal output by a comparator, the driving unit and the half-bridge unit are both connected with positive and negative power supplies, and the positive and negative power supplies are opposite in polarity and equal in size, so that the first amplification signal is an alternating current, and a blocking capacitor does not need to be arranged; therefore, the quality of the output audio signal is improved while the system cost is reduced.