At frequency phase shifting circuit for use in a quadrature clock generator

Abstract

A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

Description

FIELD OF THE INVENTIONThe present invention relates generally to phase shifting circuits and more particularly to a phase shifting circuit that may be used in quadrature clock generator for .[.for.]. providing quadrature output signals.BACKGROUND OF THE INVENTIONA quadrature clock generator may be used in a delay locked loop (DLL) to provide two clock signals that are 90 degrees out of phase with one another. Typically, a first output clock signal (the "I" output clock signal) is in phase with the input reference clock signal, and a second output clock signal (the quadrature or "Q" output clock signal) is 90 degrees out of phase with the input reference clock signal. Both output clock signals of the quadrature clock generator have the reference frequency. The output clock signals are phase mixed to provide a desired phase difference or delay between the output clock signal of the DLL and the input reference clock.Cyclic variations from the desired phase difference between the output...

AI Technical Summary

Problems solved by technology

Cyclic variations from the desired phase difference between the output clock signals of the quadrature clock generator result in "jitter."

For DLL purposes, the jitter of the quadrature clock generator affects the timing margins of the DLL, increasing lock acquisition time for the DLL.

Wherein frequency dividing quadrature clock generators are capable of providing adequate jitter performance, a DL

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