15results about "Computing operations for integral formation" patented technology

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

The present invention discloses a method, device, equipment, and storage medium for correcting the flatness of a DA chip. This method utilizes a lookup table approach to correct the flatness of each DA chip frequency point, making it more convenient and accurate. Using an FPGA to process the flatness algorithm effectively increases computational speed and correction accuracy. This method achieves precise flatness correction at each DA chip frequency point, improving hardware performance. For hardware platforms, it offers high operability and low power consumption. It is worthy of widespread adoption.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

The embodiment of the application provides a data processing method and device of a filter, electronic equipment and medium, the method comprises the following steps: obtaining input data; according to a pre-configured filtering parameter, searching a pre-stored lookup table to find a target output bit width corresponding to the input data; according to the target output bit width, using a cascade integrator to perform integral processing on the input data to obtain integral data; according to the target output bit width, using a decimator to perform decimation sampling on the integral data to obtain sampling data; and according to the target output bit width, using a cascade differentiator to perform differential processing on the sampling data to obtain filtered data corresponding to the input data. In the embodiment of the application, a bit width adaptive control unit is added to realize bit width selection and effective data bit control under different decimation rates and orders, which can effectively avoid the generation of burrs in the filtering process.

The invention provides a complex integrator and a radio frequency device, the complex integrator comprises an in-phase signal processing branch and an orthogonal signal processing branch, the input end of the in-phase signal processing branch is connected with a complex real part signal, the in-phase signal processing branch is used for carrying out phase calibration on the complex real part signal according to a reference voltage, and the orthogonal signal processing branch is connected with the orthogonal signal processing branch. A voltage in-phase signal is output through the output end of the comparator; the input end of the orthogonal signal processing branch is connected with a complex imaginary part signal and connected with the output end of the in-phase signal processing branch, and the orthogonal signal processing branch is used for conducting complex integration on the voltage in-phase signal and the complex imaginary part signal according to the reference voltage. The complex integrator circuit is designed to adopt an approximately dual structure, and the output of the in-phase branch operational amplifier is used as the input of the orthogonal branch operational amplifier, so that the circuit structure of the complex integrator is simplified, and the power consumption of the circuit is reduced.

The invention relates to a device and a method for automatically testing an electrochemical sensor. The electrochemical sensor is designed like a fuel cell and comprises a measuring chamber, two electrodes, and an ionically conductive electrolyte between the two electrodes. A target gas to be detected triggers an electrochemical reaction in the measuring chamber. The reaction causes an electric current to flow. A parameter of the flowing electric current correlates with the desired target gas concentration. A current intensity curve [I(t)] is determined, which is the temporal variation of the current intensity (I) whose flow is triggered by the electrochemical reaction. Several parameters [T70, T70.35, T70.70, Tnorm] of the current intensity curve [I(t)] are determined. A measure of the current humidity of the electrolyte is determined.For this purpose, the determined parameters [T70, T70.35, T70.70, Tnorm] of the current intensity curve [I(t)] are used.

A full-scale convolution calculator based on a memristor crossbar array is characterized by comprising a convolution kernel matrix, an input array, and an output circuit that outputs the convolution result. A convolution method for a full-scale convolution calculator is described. The convolution kernel matrix acquires input data, which then transmits a pulse voltage signal below the memristor threshold voltage to the positive input of the convolution kernel. After passing through an arithmetic circuit, m data are obtained. Each data is connected to the input array and accumulated and summed within F convolution calculation units with the input data stored in the memristor crossbar array. The result is then output. This method significantly accelerates convolution calculations by increasing storage area, leveraging the high integration and size advantages of the memristor array. The convolver can perform convolution calculations on all convolution areas tiled on the convolution matrix in parallel, significantly increasing computational efficiency. The larger the input data, the more significant the effect.

Analog circuit for receiving a current signal for frequency decomposition using a plurality of transistors configured to receive a first current, a first drain coupled to a third drain at a third transistor, and a signal input applied to a first gate for determining current flowing through the first / second transistors; second transistor including a second source configured to receive the first current, second drain coupled to a fourth drain at fourth transistor, and the signal input applied to a second gate for determining current flowing through the second transistor, third transistor including a third source configured to receive a second current and signal input applied to a third gate for determining current flowing through the third transistor, and fourth transistor including a fourth source configured to receive the second current and signal input applied to a first gate for determining current flowing through the fourth transistor.

The present application relates to a kind of weight input control system of pulsating array, belong to pulse array control technical field.The weight input control system of pulsating array includes: control unit, input storage unit, weight storage unit, logic unit, pulsating array unit and output storage unit;The control unit is connected with the input storage unit, the logic unit and the pulsating array unit respectively;The logic unit is connected with the weight storage unit;The pulsating array unit is connected with the input storage unit, the weight storage unit and the output storage unit respectively;Based on this structure setting, the present application can reduce image data transmission time, and then improve computing efficiency.

To provide a semiconductor device with a hierarchical artificial neural network being constructed, a semiconductor device with low power consumption, and an electronic apparatus comprising such a semiconductor device.SOLUTION: A hierarchical artificial neural network 100 has a first layer comprising neurons N1(1) to Np(1) (where p is an integer of 1 or greater), a (k-1)th layer comprising neurons N1(k-1) to neuron Nm(k-1) (where m is an integer of 1 or greater), the k-th layer has neurons N1(k) to neuron Nn(k) (where n is an integer of 1 or greater). The R-th layer has neurons N1(R) to Nq(R) (where q is an integer of 1 or greater).SELECTED DRAWING: Figure 1

The invention discloses a systolic array and a control method thereof, an accelerator, electronic equipment and a systolic array, and the systolic array comprises a plurality of processing units which are regularly arranged and connected in a matrix form, and two boundary processing units which are located at the head part and the tail part of each column in the column direction of the systolic array, meanwhile, different weight data segments contained in corresponding column vectors in the weight matrix are loaded, and weight data in the loaded weight data segments are sequentially transmitted to corresponding processing units in the column according to the column direction; two boundary processing units located at the head and the tail of each row in the row direction of the systolic array respond to loaded to-be-calculated weight data and simultaneously load different input data segments contained in corresponding column vectors in an input matrix; and sequentially transmitting the loaded input data in the input data segment to each processing unit in the line according to the line direction, and carrying out calculation operation on the input data and the weight data which are loaded into the processing units so as to realize a calculation task.

To provide semiconductor and electronic devices that can perform calculations with low power consumption. [Solution] The arithmetic circuit is a semiconductor device having an array unit ALP and a circuit AFP, wherein the array unit ALP has circuits MP[1,j] to MP[m,j]. The circuit AFP also has a circuit ACTF[j], which has a capacitor CRE, a circuit AC, terminal T1, and terminal T2. Each of the circuits MP[1,j] to MP[m,j] is electrically connected to wiring XLS[1] to wiring XLS[m]. Wiring OL[j] is electrically connected to terminal T1, terminal T1 is electrically connected to the first terminal of capacitor CRE, wiring OLB[j] is electrically connected to terminal T2, terminal T2 is electrically connected to the second terminal of capacitor CRE. The voltage (charge) stored in capacitor CRE is input to circuit AC, and the amount of voltage (charge) stored in capacitor CRE is sensed.

To provide a semiconductor device with a hierarchical artificial neural network being constructed, a semiconductor device with low power consumption, and an electronic apparatus comprising such a semiconductor device.SOLUTION: A hierarchical artificial neural network 100 has a first layer comprising neurons N1(1) to Np(1) (where p is an integer of 1 or greater), a (k-1)th layer comprising neurons N1(k-1) to neuron Nm(k-1) (where m is an integer of 1 or greater), the k-th layer has neurons N1(k) to neuron Nn(k) (where n is an integer of 1 or greater). The R-th layer has neurons N1(R) to Nq(R) (where q is an integer of 1 or greater).SELECTED DRAWING: Figure 1