717 results about "Charge injection" patented technology

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

Methods and apparatus for improved current-to-voltage integrators reducing charge injection and kT/C errors from capacitor switching and intrinsic operational amplifier noise (i.e., offset, 1/f noise, thermal noise) during the reset cycle of the integrator, simultaneously reducing demands on the reference voltage source, using correlated double sampling to compensate for DC offset and low frequency op-amp noises, and “fake” integration and a capacitor divider to eliminate or significantly reduce kT/C noise and charge injection.

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

To provide an organic field effect transistor with stable characteristics and a long life span, an organic field effect transistor includes a gate electrode 8 formed on an organic semiconductor film 2 made of an organic semiconductor material with a gate insulating film 3 interposed therebetween; and a source electrode 6 and a drain electrode 7 provided so as to come in contacts with the organic semiconductor film with the gate electrode 8 interposed therebetween. At least one of the source electrode 6 and the drain electrode 7 is formed in contact with the organic semiconductor film 2 with charge injection layers 4 and 5 made of an inorganic material interposed therebetween.

In some embodiments, the present invention is directed to processes for the combination of injecting charge in a material electrochemically via non-faradaic (double-layer) charging, and retaining this charge and associated desirable properties changes when the electrolyte is removed. The present invention is also directed to compositions and applications using material property changes that are induced electrochemically by double-layer charging and retained during subsequent electrolyte removal. In some embodiments, the present invention provides reversible processes for electrochemically injecting charge into material that is not in direct contact with an electrolyte. Additionally, in some embodiments, the present invention is directed to devices and other material applications that use properties changes resulting from reversible electrochemical charge injection in the absence of an electrolyte.

An optoelectronic apparatus, a method for making the apparatus, and the use of the apparatus in an optoelectronic device are disclosed. The apparatus may include an active layer having a nanostructured network layer with a network of regularly spaced structures with spaces between neighboring structures. One or more network-filling materials are disposed in the spaces. At least one of the network-filling materials has complementary charge transfer properties with respect to the nanostructured network layer. An interfacial layer, configured to enhance an efficiency of the active layer, is disposed between the nanostructured network layer and the network-filling materials. The interfacial layer may be configured to provide (a) charge transfer between the two materials that exhibits different rates for forward versus backward transport; (b) differential light absorption to extend a range of wavelengths that the active layer can absorb; or (c) enhanced light absorption, which may be coupled with charge injection.

A tandem organic light emitting diode (OLED) device comprised of multiple stacked single OLEDs electrically connected in parallel via transparent interlayer is recited herein. Transparent interlayers are coated by charge injection layers in order to enhance the charge injection efficiency and decrease the operation voltage. Transparent nanomaterials, such as carbon nanotube sheets (or graphene, graphene ribbons and similar conductive transparent nano-carbon forms) are used as Interlayers or outer electrodes. Furthermore, functionalization of carbon nanotubes inter layers by n-doping (or p-doping) converts them into common cathode (or common anode), further decreasing operation voltage of tandem. The development of these alternative interconnecting layers comprised of nanomaterials simplifies the process and may be combined with traditional OLED devices. In addition, novel architectures are enabled that allow the parallel connection of the stacked OLEDs into monolithic multi-junction OLED tandems.

An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

The present invention discloses all-in-one organic electroluminescent inks for balanced charge injection. When of single layer organic lighting emitting diodes are made from these inks, the charge balance can be readily achieved. By using the invented all-in-one organic electroluminescent inks, both the device structure and the fabrication process are simplified, which will increase the production yield and reduce the production cost in manufacturing such devices. This invention also teaches methods to fabricate single layer all-in-one organic light emitting diodes.

An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.

A control circuit for a MEMS (Micro-Electro-Mechanical System) has a semiconductor switch which has a source, a drain and a gate, which is associated with a selected one of spatially arranged fixed and movable plates of a variable capacitor, and is arranged to selectively connect the selected one of the fixed and movable plates with a voltage source. A charge injection control circuit is associated with the semiconductor switch and attenuates current injection into the selected one of the fixed and movable plates of the capacitor.

Embodiments of the invention relate to vertical field effect transistor that is a light emitting transistor. The light emitting transistor incorporates a gate electrode for providing a gate field, a first electrode comprising a dilute nanotube network for injecting a charge, a second electrode for injecting a complementary charge, and an electroluminescent semiconductor layer disposed intermediate the nanotube network and the electron injecting layer. The charge injection is modulated by the gate field. The holes and electrons, combine to form photons, thereby causing the electroluminescent semiconductor layer to emit visible light. In other embodiments of the invention a vertical field effect transistor that employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.

To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2). The second conductive layer (WL) is connected to a word line and second conductivity type regions (S/D1, S/D2) are connected to bit lines (Bla, BLb).

The invention discloses a display panel and a display device. A threshold compensation circuit comprises a first threshold compensation transistor, a second threshold compensation transistor and a shielding capacitor. Wherein a first threshold compensation transistor and a second threshold compensation transistor are arranged; the length L of the channel region of the transistor can be increased equivalently, and the current I of the transistor is inversely proportional to the length L of the channel region, so that when the length L of the channel region is increased, the current I of the transistor can be reduced, and the quantity of charges flowing into the node N1 from the node N4 can be reduced. Moreover, by arranging the shielding capacitor, the charge of the node N4 can be stored inthe shielding capacitor by utilizing the charge storage effect of the shielding capacitor. Therefore, during signal switching on the scanning signal line, charges of the node N4 can be prevented frombeing injected into the node N1, so that the voltage of the grid electrode of the driving transistor can be kept stable, and the display uniformity of the display panel is improved.

Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Apparatus on cell architecture are provided for the nonvolatile memory cells. Additionally, apparatus on array architectures are provided for constructing the nonvolatile memory cells in memory array. Method on manufacturing such memory cells and array architectures are provided.

An energy recovery device including: at least one capacitor with variable capacitance, the capacitor including a fixed electrode, a dielectric layer, and a liquid electrode; and a mechanism to inject an electric charge into the capacitor and to remove the electric charge therefrom, including a charge injection electrode forming a portion of the second face positioned upstream from the fixed electrode in the direction of displacement of the liquid electrode, and a charge removal electrode forming a portion of the second face positioned downstream from the fixed electrode in the direction of displacement of the liquid electrode.