46 results about "Charge loss" patented technology

Systems and methods for providing a memory sub-system controller selectively refresh data by differentiating between read disturb charge loss from data retention charge loss. The controller performs a read disturb induced charge loss (RDCL) scan operation on a portion of a set of memory components. The controller determines that a first bit error count (BEC) associated with the RDCL scan operation on the portion of the set of memory components transgresses a threshold value and determines whether the first BEC corresponds to a second BEC that represents data retention (DR) charge loss. The controller selectively refreshes data stored in the portion of the set of memory components based on determining whether the first BEC corresponds to the second BEC that represents DR charge loss.

The invention provides a driving method and a driving circuit of a display panel and a display device.In the driving method of the display panel, in each display frame, positive polarity gray-scale voltage and negative polarity gray-scale voltage are alternately output to pixel units, aging of liquid crystal molecules can be reduced through a polarity alternate driving mode, and meanwhile, the driving efficiency of the display panel is improved. The target gray scale voltage with the same polarity as the next frame is inserted between the adjacent display frames, charge loss caused by leakage current of the thin film transistor is compensated, additional hardware does not need to be added, the design cost and power consumption are reduced, leakage current compensation can be achieved only through time sequence optimization, the problems of ghost shadow, flicker, contrast reduction and the like are effectively solved, and the display quality is improved. And the display image quality is improved.

This invention relates to the field of energy management technology for energy storage systems, and discloses a method and system for equalization control of UAV battery packs. The method includes: acquiring a voltage sequence and preprocessing it to obtain a smoothed voltage sequence, then sorting it by deviation level to obtain a priority processing unit set; calculating the equalization current based on the priority processing unit set and the smoothed voltage sequence to obtain an initial high-voltage current and an initial low-voltage current, and calculating the charging loss to obtain the total loss; optimizing the allocation based on the total loss to obtain an optimized high-voltage current and an optimized low-voltage current, and applying maximum current limiting to obtain a limited high-voltage current and a limited low-voltage current; predicting the range using a voltage range prediction model based on the limited high-voltage current and limited low-voltage current, and iteratively optimizing based on the predicted range value to obtain the final current pair; and generating current control commands based on the final current pair to control the battery pack. This method achieves voltage consistency during the charging process of the UAV battery pack.

The application provides a successive approximation type analog-digital converter, which comprises a first switch and a second switch, a first capacitor array type digital-analog converter, a second capacitor array type digital-analog converter, a successive approximation logic module which outputs a multi-bit digital signal, a comparator, a first input end of the comparator being connected with an output end of the first capacitor array type digital-analog converter through the first switch, and a second input end of the comparator being connected with an output end of the second capacitor array type digital-analog converter through the second switch, a first pre-charge circuit which works before the first switch is turned on and charges the first input end of the comparator based on an output voltage of the first capacitor array type digital-analog converter, and a second pre-charge circuit which works before the second switch is turned on and charges the second input end of the comparator based on an output voltage of the second capacitor array type digital-analog converter. In this way, the amount of charge loss can be reduced, and the precision of the successive approximation type analog-digital converter is improved.

The invention relates to the technical field of medical biological materials, and particularly discloses a composite electret flexible biological electrostatic electret patch and a preparation method thereof.The electrostatic electret patch comprises a backing layer, a medical pressure-sensitive adhesive layer and a functional layer which are sequentially arranged from outside to inside. According to the functional layer, at least one of polylactic acid, polyvinylidene fluoride and a polylactic acid-glycolic acid copolymer is selected as a polymer matrix to be compounded with graphene, a specific process combining ultrasonic dispersion and high-precision 3D printing is adopted, a deep-energy-level charge trap is introduced, the problems of high-conductivity filler agglomeration and surface charge leakage are solved, and the conductivity of the graphene is improved. The surface potential retention rate of the material can reach 60% or above after 900 days, the charge loss rate is not larger than 20% after 8-hour air exposure, and efficient physical electrostatic electret assisted sleep treatment under the drug-free and non-transdermal conditions is achieved.

The application discloses a kind of selected area epitaxy GaN-on-Si HEMT direct drive single-chip integration method, belong to semiconductor device technical field.The specific inclusion includes: selecting silicon substrate and dividing GaN device area and silicon MOSFET device area;Etching recess window in GaN device area, utilize selected area epitaxy technology and grow GaN HEMT epitaxial structure in recess window;Subsequently, silicon MOSFET device and GaN MIS-HEMT device are prepared in corresponding area respectively;Finally, the drain electrode of silicon MOSFET device and the source electrode of GaN MIS-HEMT device are connected by on-chip metal interconnection process.The application realizes normally open type GaN MIS-HEMT and normally off type silicon MOSFET monolithic cascade integration, shortens the device spacing to micron level, greatly reduces parasitic inductance and capacitance, effectively suppresses switch oscillation and overshoot, reduces switch loss, and the gate of GaN MIS-HEMT device is independently extracted to realize direct drive, avoiding reverse recovery charge loss;The method of the application does not need to be bonded, and the process compatibility is good, which significantly improves the high-frequency characteristics, reliability and integration of high-performance power electronic devices.

The invention provides a memory programming method, a memory control device and a memory, and belongs to the technical field of data storage. The method comprises the following steps: determining a state parameter of a target unit block in the memory; determining a programming adjustment parameter according to the state parameter of the target unit block; in response to the programming instruction, programming at least one page in the target unit block to obtain a current programmed page when programming is finished; and determining a page to be adjusted according to the current programming completion page, and programming the page to be adjusted according to the programming adjustment parameter. According to the method and the device, the voltage threshold value of the current programming completion page at the end of programming can be kept consistent with the voltage threshold values of other pages, so that the probability of errors caused by charge loss during data storage or cross-temperature operation is reduced, the accuracy of data storage of the memory is improved, the use of other memories is not influenced, and the use experience of the memory is improved. And the programming reliability of the memory is improved.

Various embodiments use a feedback-control loop to track slow charge loss (SCL) for a memory cell of a memory device, which can be used to adjust one or more read level voltages used to read data from the memory cell.

This application relates to open block management using storage charge loss margin checks. A system includes a memory device; and a processing means operatively coupled to the memory device to perform operations including: identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages; determining that the SCL amount satisfies a threshold criterion corresponding to an acceptable SCL amount that will occur on the open block; and, in response to determining that the SCL amount satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

A memory sub-system having a memory device with a plurality of cells and a processing device operatively coupled to the memory device, the processing device to perform the operations of: responsive to detecting a power off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells.

The present disclosure relates to a charging control method and device, electronic equipment and storage medium. The method comprises: obtaining charging data of an electronic device, wherein a charge pump module of the electronic device supports at least two working modes of charging; and controlling the charge pump module to switch to a target working mode according to the charging data, the target working mode being a working mode in which charging loss power under the charging data meets a preset condition. In this embodiment, the working mode of the charge pump module is switched to reduce the charging loss of the electronic device, in particular the loss function of the charge pump module, thereby improving the charging efficiency of the electronic device.

Methods, apparatuses, and systems for tracking charge loss are described. An apparatus may include a tracking mechanism configured to perform direct measurements for tracking charge loss in a first type of cell. An apparatus may be configured to specify a set of first type cells as a surrogate for modeling charge loss in a second type of cell having a different storage density than the first type of cell. The apparatus may perform measurements on the surrogate set of first type cells and use the tracking mechanism to translate the measurement results to respond to charge loss in the second type of cell.

The present application relates to the field of power electronics and battery management technology, and particularly relates to a self-adaptive fast charging method and system suitable for a direct current power supply. The present application breaks through the fixed parameter limitation of the traditional charging mode, automatically optimizes the output charging voltage and current instruction through an intelligent decision model, and can adapt to batteries of different temperature environments, aging degrees and types. The present application can accurately perceive the battery state, identify the battery aging characteristics and adjust the parameters accordingly, with the optimization goal of minimizing the charging loss, reducing the battery heating and relieving the internal aging, effectively prolonging the service life of the battery. At the same time, within the safety constraint of the battery, the optimal charging current is solved through the optimization algorithm, the safe charging power is maximized, the charging efficiency is greatly improved, and the charging time is significantly shortened. In addition, through real-time monitoring of the battery state, the present application can also early identify the battery abnormalities, provide data support for preventive maintenance, and improve the charging safety of the direct current screen system.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

The invention discloses a CsPbBr3 quantum dot modified inverted inorganic perovskite solar cell and a preparation method thereof. Belongs to the technical field of perovskite solar cells, and through CsPbBr3 quantum dot interface modification, the method can effectively inhibit non-radiative recombination, promote efficient extraction and transmission of electrons, reduce charge loss, passivate perovskite thin film surface defects, improve crystallization quality, inhibit crystal boundary defects and optimize the overall performance of the thin film. The modification layer induces a perovskite conduction band / valence band to move downwards at the same time, energy level matching with a PCBM electron transport layer is optimized, electron injection barriers and interface recombination are reduced, and the charge transport efficiency is improved. In addition, the modification layer enhances the built-in electric field and improves the open-circuit voltage. Through the synergistic effect of defect passivation, energy level optimization and built-in electric field enhancement, the photoelectric conversion efficiency (PCE) of the device is improved from 19.61% to 21.47%, and performance breakthrough is achieved.

This disclosure is directed to a memory system that compensates for slow charge loss (SCL) encountered during a power off period. The memory system computes, during a power-on sequence of the memory device, a first value associated with reading data from an individual portion of the memory device and obtains a second value associated with reading data from the individual portion, the second value having been computed during a power-off sequence of the memory device. The memory system compares the first value with the second value to estimate a measure of SCL encountered while the memory device was powered off and reads the data from a plurality of portions of the memory device based on respective threshold voltages that compensate for the estimated measure of SCL.

This disclosure relates to charge loss compensation during read operations in a memory device. Control logic in the memory device initiates a read operation on the memory array of the memory device and performs a calibration operation to detect a change in the series resistance in the memory array. The control logic determines whether the change in series resistance is attributable to charge loss in the memory array, and in response to determining that the change in series resistance is attributable to charge loss in the memory array, performs the read operation using a calibrated read voltage level to read data from the memory array.

This disclosure is directed to a memory system that compensates for slow charge loss (SCL) encountered during a power off period. The memory system computes, during a power-on sequence of the memory device, a first value associated with reading data from an individual portion of the memory device and obtains a second value associated with reading data from the individual portion, the second value having been computed during a power-off sequence of the memory device. The memory system compares the first value with the second value to estimate a measure of SCL encountered while the memory device was powered off and reads the data from a plurality of portions of the memory device based on respective threshold voltages that compensate for the estimated measure of SCL.

The invention discloses a battery charging adaptive integrated management circuit, which relates to the technical field of battery charging, and comprises a power supply module for providing charging electric energy for a first battery pack module and a second battery pack module, so that a first battery, a second battery and a third battery in the first battery pack module are connected in series for charging; a fourth battery, a fifth battery and a sixth battery in the second battery pack module are connected in series for charging, and a battery detection module detects the voltage difference states of the second battery, the fifth battery, the third battery and the sixth battery with the first battery and the fourth battery respectively, so as to control the charging paths of the second battery and the fifth battery; the charging paths of the third battery and the sixth battery are controlled, the charging objects of the first battery pack module and the second battery pack module are exchanged, and the battery charging difference is reduced. The battery charging adaptive integrated management circuit can reduce battery charging difference and charging loss and improve charging efficiency.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

The invention relates to a power switch device loss separation test method and device, computer equipment, a storage medium and a computer program product. The method comprises the steps of determining discharge loss corresponding to a power switch device according to first drain-source voltage data and first drain current data of the power switch device to be tested in a conduction steady state, and determining discharge loss corresponding to the power switch device according to second drain-source voltage data and second drain current data of the power switch device in a turn-off transient state, determining the overlapping loss corresponding to the power switch device, and determining the charging loss corresponding to the power switch device according to the third drain-source voltage data and the third drain current data of the power switch device in the turn-off steady state; determining hysteresis loss corresponding to the power switch device according to the charging loss, the discharging loss and the overlapping loss; and obtaining a loss test result corresponding to the power switch device based on the charging loss, the discharging loss, the overlapping loss and the hysteresis loss. By adopting the method, the loss test precision of the power switch device can be improved.

This application relates to charge loss scan operation management in memory devices. A memory system includes a memory device and a processing device operatively coupled to the memory device. The processing device performs operations including identifying an operating temperature of the memory device, determining that the operating temperature satisfies a temperature condition, modifying a scan frequency parameter for performing a scan operation on a representative block of a group of blocks in the memory device, and performing the scan operation at a frequency identified by the scan frequency parameter.

Processing logic of a memory sub-system to measure a set of slow charge loss (SCL) values, wherein each SCL value of the set of slow charge loss values corresponds to a memory die of a set of memory dies of a memory sub-system. An ordered SCL index based on the set of SCL values is generated. Using a die family threshold level, a set of ranges of the ordered SCL index is identified. Each range of the set of ranges is assigned to a corresponding die family of a set of die families.

The application provides a method and device for testing a battery management system micro-short circuit diagnosis, electronic equipment and a storage medium. The method comprises: controlling a specified battery cell in a battery pack to discharge continuously at a predetermined duty cycle; determining a reference state-of-charge loss rate according to an equalization current, a discharge time, the predetermined duty cycle and a capacity of the battery cell; running a micro-short circuit diagnosis scheme to obtain an output estimated state-of-charge loss rate; comparing the estimated state-of-charge loss rate with the reference state-of-charge loss rate, and determining the accuracy of the micro-short circuit diagnosis scheme according to the comparison result, which can standardize, test and verify the micro-short circuit diagnosis scheme of the battery management system in multiple scenarios.

A reference voltage generator for capacitive digital-to-analog converter (CDAC) is shown. The reference voltage generator has a low-pass circuit and a charge compensation circuit. The low-pass circuit has an input terminal receiving a reference voltage, and an output terminal coupled to a reference input terminal of a CDAC. The charge compensation circuit is coupled to the reference input terminal of the CDAC in a first phase to compensate for charge losses of the CDAC, and is coupled to the reference voltage in a second phase to be charged by the reference voltage. In the first phase, the charge compensation circuit provides a reinforced voltage to the reference input terminal of the CDAC, and the reinforced voltage is greater than the reference voltage. A stable voltage, therefore, is provided to the reference input terminal of the CDAC.

The application relates to a small extracellular vesicle detection method based on a solid-state nanopore and machine learning. The method comprises the following steps: detecting a to-be-detected sample by using a solid-state nanopore chip, making an electroosmotic flow dominate particle capture and a through hole by applying a voltage; collecting a nanopore ion current signal and performing filtering, baseline correction and detrending pretreatment; extracting equivalent charge loss, blocking amplitude, half-residence time, left edge slope and right edge slope of a single event through hole signal; inputting the features into a trained machine learning model to obtain a specific event correlation score, taking a correlation event ratio in a sample as a discrimination index, and realizing detection of target small extracellular vesicles. Compared with an existing detection method which needs labeling and enrichment, the application can realize rapid, label-free and single-particle-level detection analysis in a complex plasma matrix.

Apparatuses and methods for performing read operations using an offset based upon slow charge loss characteristics are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in the array of memory cells during a read operation on the word line, wherein the read voltage includes an offset associated with a slow charge loss characteristic of the word line.

A system includes a memory device and a processing device operatively coupled with the memory device to perform operations including determining to perform a first scan operation on a first block of a plurality of blocks of the memory device; responsive to determining to perform the first scan operation, adding an indication of the first scan operation to a queue of pending scan operations corresponding to scanning the plurality of blocks; determining whether a number of pending scan operations of the queue of pending scan operations satisfies a threshold condition; and responsive to determining that the number of pending scan operations does not satisfy the threshold condition, causing a first subset of scan operations of the queue of pending scan operations to be performed on respective blocks of the plurality of blocks.

Methods, systems, and devices for cross temperature read voltage calibration for a memory system are described. A memory system may generate read voltage offsets to apply to memory cells during a refresh or calibration operation based on a combination of both a read voltage shift associated with charge loss and cross-temperature conditions of the memory cells. The memory system may program memory cells at a first time and determine a first shift in read voltage for a first logic state as well as a first change in temperature between the first time and second time at which the memory cells are read out. The final read trims to apply during refresh may be calculated by inputting the read voltage shift and the change in temperature to a machine learning (ML) model, a combination of look-up tables (LUTs), or both, each of which may be trained to output read trim values.

DRAM cells need to be periodically refreshed to preserve the charge stored in them. The retention time is typically not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the retention time of cells with the highest charge loss and the cells with the lowest charge loss. Different refresh intervals are used for certain wordlines based on the required minimum retention time of the cells on those wordlines. The memory controller does not keep track of refresh addresses. After initialization of the DRAM devices, the memory controller issues a smaller number of refresh commands when compared to refreshing all wordlines at the same refresh interval.