76 results about "Charge loss" patented technology

The invention discloses an intelligent charging management system and management method based on a battery health state, which is used for managing a vehicle-mounted battery on a new energy electric vehicle and comprises a battery health monitoring module, an intelligent decision module, a charging execution module and a heat management module, the battery health monitoring module is used for correcting the SOH evaluation value of the battery and is matched with the intelligent decision-making module based on the correction, the optimal charging curve is dynamically output, pulse charging is integrated through the charging execution module so as to reduce polarization and recover charging waste heat, the battery equalization function can be started in time, and the service life of the battery is prolonged. According to the method, the attenuation speed of the service life of the battery is delayed, the thermal runaway risk caused by fast charging is reduced, the charging loss is reduced so as to improve the energy utilization rate, and the effect of optimizing the charging efficiency, the safety and the service life of the battery is achieved through real-time monitoring and dynamic regulation and control.

Systems and methods for providing a memory sub-system controller selectively refresh data by differentiating between read disturb charge loss from data retention charge loss. The controller performs a read disturb induced charge loss (RDCL) scan operation on a portion of a set of memory components. The controller determines that a first bit error count (BEC) associated with the RDCL scan operation on the portion of the set of memory components transgresses a threshold value and determines whether the first BEC corresponds to a second BEC that represents data retention (DR) charge loss. The controller selectively refreshes data stored in the portion of the set of memory components based on determining whether the first BEC corresponds to the second BEC that represents DR charge loss.

The invention provides a driving method and a driving circuit of a display panel and a display device.In the driving method of the display panel, in each display frame, positive polarity gray-scale voltage and negative polarity gray-scale voltage are alternately output to pixel units, aging of liquid crystal molecules can be reduced through a polarity alternate driving mode, and meanwhile, the driving efficiency of the display panel is improved. The target gray scale voltage with the same polarity as the next frame is inserted between the adjacent display frames, charge loss caused by leakage current of the thin film transistor is compensated, additional hardware does not need to be added, the design cost and power consumption are reduced, leakage current compensation can be achieved only through time sequence optimization, the problems of ghost shadow, flicker, contrast reduction and the like are effectively solved, and the display quality is improved. And the display image quality is improved.

A threshold voltage prediction apparatus according to the present invention comprises: a memory storing a program for providing operation simulation for a nonvolatile memory apparatus; and a processor that executes the program stored in the memory, wherein the program: receives device characteristics including an arrangement structure of a plurality of devices and initial operation parameters to generate a virtual nonvolatile memory; sets a variable parameter for determining the degree of charge loss for each of a plurality of compact models based on a charge loss model and applies the variable parameter to each device; performs Monte-Carlo simulation for the virtual nonvolatile memory on the basis of the plurality of compact models applied to respective devices and a physical mechanism causing charge loss; and outputs a change in threshold voltage of each device, which is predicted on the basis of results of the simulation.

This invention relates to the field of energy management technology for energy storage systems, and discloses a method and system for equalization control of UAV battery packs. The method includes: acquiring a voltage sequence and preprocessing it to obtain a smoothed voltage sequence, then sorting it by deviation level to obtain a priority processing unit set; calculating the equalization current based on the priority processing unit set and the smoothed voltage sequence to obtain an initial high-voltage current and an initial low-voltage current, and calculating the charging loss to obtain the total loss; optimizing the allocation based on the total loss to obtain an optimized high-voltage current and an optimized low-voltage current, and applying maximum current limiting to obtain a limited high-voltage current and a limited low-voltage current; predicting the range using a voltage range prediction model based on the limited high-voltage current and limited low-voltage current, and iteratively optimizing based on the predicted range value to obtain the final current pair; and generating current control commands based on the final current pair to control the battery pack. This method achieves voltage consistency during the charging process of the UAV battery pack.

The utility model discloses an ultra-low power consumption quick starting circuit of a power adapter, which comprises a high-voltage power supply end HV and an accelerated charging starting circuit connected with the high-voltage power supply end HV, and the accelerated charging starting circuit is connected with an after-starting turn-off charging circuit. The acceleration charging starting circuit is composed of a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor CE1, a capacitor C1, a capacitor CE3 and an MOS tube Q1, the resistor R1 and the resistor R2 are connected in series and then connected with the capacitor CE1 in parallel, one end of the resistor R3 is connected with the capacitor CE1 and the resistor R2, and the other end of the resistor R3 is connected with the grid electrode of the capacitor C1 and the grid electrode of the MOS tube Q1. The resistor R4 and the resistor R5 are connected in series, and one end, far away from the resistor R5, of the resistor R4 is respectively connected with the capacitor CE1, the resistor R1 and the high-voltage power supply end HV. According to the utility model, the accelerated charging starting circuit and the after-starting turn-off charging circuit are combined, so that the charging loss is reduced, and the adapter meets the requirements that the starting time is less than 0.5 s, the European standard six-level energy efficiency is met, and the no-load power consumption is less than 0.1 W and 230Vac.

The application provides a successive approximation type analog-digital converter, which comprises a first switch and a second switch, a first capacitor array type digital-analog converter, a second capacitor array type digital-analog converter, a successive approximation logic module which outputs a multi-bit digital signal, a comparator, a first input end of the comparator being connected with an output end of the first capacitor array type digital-analog converter through the first switch, and a second input end of the comparator being connected with an output end of the second capacitor array type digital-analog converter through the second switch, a first pre-charge circuit which works before the first switch is turned on and charges the first input end of the comparator based on an output voltage of the first capacitor array type digital-analog converter, and a second pre-charge circuit which works before the second switch is turned on and charges the second input end of the comparator based on an output voltage of the second capacitor array type digital-analog converter. In this way, the amount of charge loss can be reduced, and the precision of the successive approximation type analog-digital converter is improved.

The invention relates to the technical field of medical biological materials, and particularly discloses a composite electret flexible biological electrostatic electret patch and a preparation method thereof.The electrostatic electret patch comprises a backing layer, a medical pressure-sensitive adhesive layer and a functional layer which are sequentially arranged from outside to inside. According to the functional layer, at least one of polylactic acid, polyvinylidene fluoride and a polylactic acid-glycolic acid copolymer is selected as a polymer matrix to be compounded with graphene, a specific process combining ultrasonic dispersion and high-precision 3D printing is adopted, a deep-energy-level charge trap is introduced, the problems of high-conductivity filler agglomeration and surface charge leakage are solved, and the conductivity of the graphene is improved. The surface potential retention rate of the material can reach 60% or above after 900 days, the charge loss rate is not larger than 20% after 8-hour air exposure, and efficient physical electrostatic electret assisted sleep treatment under the drug-free and non-transdermal conditions is achieved.

The application discloses a kind of selected area epitaxy GaN-on-Si HEMT direct drive single-chip integration method, belong to semiconductor device technical field.The specific inclusion includes: selecting silicon substrate and dividing GaN device area and silicon MOSFET device area;Etching recess window in GaN device area, utilize selected area epitaxy technology and grow GaN HEMT epitaxial structure in recess window;Subsequently, silicon MOSFET device and GaN MIS-HEMT device are prepared in corresponding area respectively;Finally, the drain electrode of silicon MOSFET device and the source electrode of GaN MIS-HEMT device are connected by on-chip metal interconnection process.The application realizes normally open type GaN MIS-HEMT and normally off type silicon MOSFET monolithic cascade integration, shortens the device spacing to micron level, greatly reduces parasitic inductance and capacitance, effectively suppresses switch oscillation and overshoot, reduces switch loss, and the gate of GaN MIS-HEMT device is independently extracted to realize direct drive, avoiding reverse recovery charge loss;The method of the application does not need to be bonded, and the process compatibility is good, which significantly improves the high-frequency characteristics, reliability and integration of high-performance power electronic devices.

The invention provides a memory programming method, a memory control device and a memory, and belongs to the technical field of data storage. The method comprises the following steps: determining a state parameter of a target unit block in the memory; determining a programming adjustment parameter according to the state parameter of the target unit block; in response to the programming instruction, programming at least one page in the target unit block to obtain a current programmed page when programming is finished; and determining a page to be adjusted according to the current programming completion page, and programming the page to be adjusted according to the programming adjustment parameter. According to the method and the device, the voltage threshold value of the current programming completion page at the end of programming can be kept consistent with the voltage threshold values of other pages, so that the probability of errors caused by charge loss during data storage or cross-temperature operation is reduced, the accuracy of data storage of the memory is improved, the use of other memories is not influenced, and the use experience of the memory is improved. And the programming reliability of the memory is improved.

To provide a battery system having a plurality of batteries and a relay that switches a connection relation of the batteries, and a technique for efficiently charging the plurality of batteries in consideration of losses of the relay.SOLUTION: A battery system includes a voltage converter, a series relay, and a parallel relay. The series relay and the parallel relay switch a connection relation of the plurality of batteries relative to the voltage converter. The controller compares series charge loss, which is a sum of losses of the voltage converter and the series relay when the series relay is closed to charge the plurality of batteries, with parallel charge loss, which is a sum of losses of the voltage converter and the parallel relay when the parallel relay is closed to charge the plurality of batteries. The controller charges the plurality of batteries in a mode of a smaller one of the series charge loss and the parallel charge loss.SELECTED DRAWING: Figure 2

This application relates to double verification for reducing fast charge loss in memory cells. A memory device includes a memory array of memory cells. A page buffer is used to apply a first voltage or a second voltage higher than the first voltage to a bit line during a program verify operation. Control logic, operatively coupled with the page buffer, is used to perform operations including causing a plurality of memory cells to program with a first program pulse, measuring threshold voltages of the memory cells, forming a threshold voltage distribution from the measured threshold voltages, classifying a first subset of the memory cells as having a faster fast charge loss than a second subset of the memory cells based on the threshold voltage distribution, and causing the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells in response to the classifying.

The utility model relates to the technical field of water electrolysis hydrogen production, and provides an AEM water electrolysis hydrogen production bipolar runner plate which comprises a bipolar runner plate body. One surface of the bipolar runner plate body is an anode surface, and the other surface of the bipolar runner plate body is a cathode surface; an AEM film placing opening is formed in the bipolar runner plate body; four corners of the bipolar runner plate body are respectively provided with a first opening, a second opening, a third opening and a fourth opening; the anode surface is provided with an anode gas diffusion layer placing groove in the circumferential direction of the AEM film placing opening; the lower part of the anode surface is provided with a first snakelike flow channel and a first branched flow channel communicated with the first snakelike flow channel; the first snakelike flow channel is communicated with the first opening, and the first branched flow channel is communicated with the anode gas diffusion layer placing groove. According to the utility model, the contact area of electrolyte between the bipolar plate and the diffusion layer is increased, the circulation sectional area is reduced, the flow channel length is prolonged, the charge loss generated by bypass current is reduced, and the coulombic efficiency is improved.

Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

Control logic in a memory device causes a programming pulse of a programming operation to be applied to a selected wordline associated with a plurality of memory cells of a memory device to be programmed to a target voltage level representing a programming level, where a charge loss associated with the plurality of memory cells occurs following application of the programming pulse. The selected wordline is discharged to establish an erase voltage level on the plurality of memory cells and accelerate the charge loss associated with the plurality of memory cells. The control logic performs a program verify operation corresponding to the programming level associated with the plurality of memory cells.

Various embodiments use a feedback-control loop to track slow charge loss (SCL) for a memory cell of a memory device, which can be used to adjust one or more read level voltages used to read data from the memory cell.

This application relates to open block management using storage charge loss margin checks. A system includes a memory device; and a processing means operatively coupled to the memory device to perform operations including: identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages; determining that the SCL amount satisfies a threshold criterion corresponding to an acceptable SCL amount that will occur on the open block; and, in response to determining that the SCL amount satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

A memory sub-system having a memory device with a plurality of cells and a processing device operatively coupled to the memory device, the processing device to perform the operations of: responsive to detecting a power off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells.

The present disclosure relates to a charging control method and device, electronic equipment and storage medium. The method comprises: obtaining charging data of an electronic device, wherein a charge pump module of the electronic device supports at least two working modes of charging; and controlling the charge pump module to switch to a target working mode according to the charging data, the target working mode being a working mode in which charging loss power under the charging data meets a preset condition. In this embodiment, the working mode of the charge pump module is switched to reduce the charging loss of the electronic device, in particular the loss function of the charge pump module, thereby improving the charging efficiency of the electronic device.

Methods, apparatuses, and systems for tracking charge loss are described. An apparatus may include a tracking mechanism configured to perform direct measurements for tracking charge loss in a first type of cell. An apparatus may be configured to specify a set of first type cells as a surrogate for modeling charge loss in a second type of cell having a different storage density than the first type of cell. The apparatus may perform measurements on the surrogate set of first type cells and use the tracking mechanism to translate the measurement results to respond to charge loss in the second type of cell.

Methods, systems, and devices for charge loss weak die identification are described. The described techniques provide for a memory system to avoid sampling, during block family (BF) scans, blocks of memory cells associated with memory dies that are classified as read disturb charge loss (RDCL) weak dies. The memory system may identify a memory die as being an RDCL weak die based on a threshold quantity of blocks associated with the memory die experiencing relatively high charge loss. If the quantity satisfies a threshold value, the memory system may classify the memory die as an RDCL weak die and the memory system may refrain from selecting blocks from a BF that are associated with a memory die classified as an RDCL weak die.

Methods, systems, and devices for charge loss weak die identification are described. The described techniques provide for a memory system to avoid sampling, during block family (BF) scans, blocks of memory cells associated with memory dies that are classified as read disturb charge loss (RDCL) weak dies. The memory system may identify a memory die as being an RDCL weak die based on a threshold quantity of blocks associated with the memory die experiencing relatively high charge loss. If the quantity satisfies a threshold value, the memory system may classify the memory die as an RDCL weak die and the memory system may refrain from selecting blocks from a BF that are associated with a memory die classified as an RDCL weak die.

The invention relates to the technical field of smelting, and discloses a material nozzle opening degree adjusting device and a method thereof.The device comprises a stock bin, a material nozzle is formed in the lower end of the stock bin, flashboards are arranged on the left side and the right side of the material nozzle, supporting plates are arranged on the two sides, corresponding to the flashboards, of the stock bin, and an adjusting assembly is installed on each supporting plate; the adjusting assembly is used for adjusting the inclination angle of the flashboard, the belt can be prevented from deviating through the device, the discharging angle and the opening degree can be adjusted in the production process aiming at the deviating belt, and the influence on production is reduced; by means of the method, the discharging angle and the opening degree can be adjusted in time when discharging is not correct, belt damage caused by belt deviation is avoided, the production control situation caused by material nozzle replacement is reduced, meanwhile, furnace burden loss caused by belt deviation is avoided, the service life of the belt is prolonged, and the furnace burden loss is reduced.

Methods, apparatuses and systems related to managing stored data in view of charge losses are described. An apparatus may include a management mechanism that scans memory cells and adjusts read voltage levels for the memory cells to account for charge losses during operation of the apparatus. The apparatus may further leverage the management mechanism to detect or estimate one or more targeted conditions by tracking an adjustment progress while implementing the management mechanism. When the adjustment progress reaches a predetermined condition, the apparatus can estimate the occurrence of the one or more targeted conditions and implement a data refresh mechanism to restore the charges to their intended levels instead of completing the management mechanism.

The present application relates to the field of power electronics and battery management technology, and particularly relates to a self-adaptive fast charging method and system suitable for a direct current power supply. The present application breaks through the fixed parameter limitation of the traditional charging mode, automatically optimizes the output charging voltage and current instruction through an intelligent decision model, and can adapt to batteries of different temperature environments, aging degrees and types. The present application can accurately perceive the battery state, identify the battery aging characteristics and adjust the parameters accordingly, with the optimization goal of minimizing the charging loss, reducing the battery heating and relieving the internal aging, effectively prolonging the service life of the battery. At the same time, within the safety constraint of the battery, the optimal charging current is solved through the optimization algorithm, the safe charging power is maximized, the charging efficiency is greatly improved, and the charging time is significantly shortened. In addition, through real-time monitoring of the battery state, the present application can also early identify the battery abnormalities, provide data support for preventive maintenance, and improve the charging safety of the direct current screen system.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

The invention discloses a CsPbBr3 quantum dot modified inverted inorganic perovskite solar cell and a preparation method thereof. Belongs to the technical field of perovskite solar cells, and through CsPbBr3 quantum dot interface modification, the method can effectively inhibit non-radiative recombination, promote efficient extraction and transmission of electrons, reduce charge loss, passivate perovskite thin film surface defects, improve crystallization quality, inhibit crystal boundary defects and optimize the overall performance of the thin film. The modification layer induces a perovskite conduction band / valence band to move downwards at the same time, energy level matching with a PCBM electron transport layer is optimized, electron injection barriers and interface recombination are reduced, and the charge transport efficiency is improved. In addition, the modification layer enhances the built-in electric field and improves the open-circuit voltage. Through the synergistic effect of defect passivation, energy level optimization and built-in electric field enhancement, the photoelectric conversion efficiency (PCE) of the device is improved from 19.61% to 21.47%, and performance breakthrough is achieved.

Method for reducing the total charge loss of battery cells (16, 18) by balancing charge states SoC, comprising the following process steps: a) checking boundary conditions, specifically whether a previous balancing step occurred at least a defined time interval t_wait, - the temperature of a balancing unit (64) is below an adjustable temperature limit, - the charge states SoC_i of all battery cells (16, 18) are > SoC_MIN, b) determining a balancing requirement by determining whether a maximum difference of all charge states SoC_i of all battery cells (16, 18) is > DELTA_SoC, c) if process steps a) and b) are affirmed, the battery cells (16, 18) are balanced by the balancing units (64), during which balancing resistors R_bal are connected to the respective battery cells (16, 18) for a time t_i.mitt_i=Q_i⋅R_balU_OCV(SoC_i)Q_i≙ charge to be dissipated from the battery cell iU_OCV ≙ battery cell voltage with open circuitSoC_i ≙ state of charge of the battery cell iR_bal ≙ resistance value of the balancing resistord) the selection of the time interval t_wait between two balancing steps such that this corresponds to the execution of a maximum number of cycles of the balancing units (64), characterized in that the maximum number of cycles of the balancing unit (64) and the coverage of any symmetrization requirement by the duration t_i of a balancing step are adapted to each other.,

This disclosure is directed to a memory system that compensates for slow charge loss (SCL) encountered during a power off period. The memory system computes, during a power-on sequence of the memory device, a first value associated with reading data from an individual portion of the memory device and obtains a second value associated with reading data from the individual portion, the second value having been computed during a power-off sequence of the memory device. The memory system compares the first value with the second value to estimate a measure of SCL encountered while the memory device was powered off and reads the data from a plurality of portions of the memory device based on respective threshold voltages that compensate for the estimated measure of SCL.