292 results about "Data retention" patented technology

The embodiment of the invention discloses an in-memory computing circuit based on a magnetic cache, and the circuit comprises at least one magnetic cache unit, at least one in-memory computing unit, and a timer. The magnetic cache unit in the at least one magnetic cache unit is used for caching data output by the corresponding in-memory computing unit as to-be-processed data within the corresponding data retention time; the timer is used for respectively setting data retention time for the at least one magnetic cache unit; and the in-memory computing unit in the at least one in-memory computing unit is used for extracting the data to be processed from the corresponding magnetic cache unit for calculation and outputting the computed data to other magnetic cache units. According to the embodiment of the invention, the invention achieves the flexible adjustment of the data retention time of the magnetic cache unit in various in-memory calculation scenes, and achieves the provision of a high-capacity cache for the data needed by in-memory computing under the lower power consumption.

The invention discloses a security storage chip energy consumption optimization method based on multi-objective optimization, and relates to the technical field of energy consumption optimization, and the method comprises the steps: inputting the threshold voltage distribution characteristics of a security storage chip of a candidate parameter set into an aging model, fitting the rule of the threshold voltage distribution characteristics along with the time under an accelerated aging condition, and obtaining an aging model; aging model parameters are obtained; calculating the data retention failure rate of the security storage chip in the target life cycle by using the aging model parameters, and obtaining an extended feasible region of the instant erasure security constraint and the long-term retention security constraint in combination with a data retention judgment standard; and establishing a multi-objective optimization function with reduction of operation energy consumption and maintenance energy consumption as optimization objectives in the extended feasible region, and obtaining a candidate solution set through a multi-objective optimization algorithm. According to the method, data retention prediction in the life cycle is realized, and energy consumption optimization and long-term reliability constraint are combined.

The embodiment of the invention discloses an application upgrading method and device, equipment, a terminal, a storage medium and a program.The method is applied to an operation system of a WebAssembly virtual machine and comprises the steps that a first upgrading instruction initiated by a to-be-upgraded application is received; the first upgrading instruction comprises application data retention indication information of the to-be-upgraded application; obtaining an old-version application corresponding to the to-be-upgraded application and an application data object of the old-version application according to application data retention indication information included in the first upgrading instruction, and storing application data in the application data object of the old-version application; receiving a second upgrading instruction initiated by the to-be-upgraded application; and recovering the application data in the application data object of the old-version application to the application data object of the new-version application corresponding to the old-version application according to the second upgrading instruction. According to the technical scheme provided by the embodiment of the invention, the application upgrading flexibility in the operation system of the WebAssembly virtual machine can be improved.

The invention relates to a memristor and a preparation method thereof. The preparation method comprises the following steps: providing an insulating substrate with a bottom electrode formed on the surface; depositing an aluminum oxide thin film on the bottom electrode by adopting electron beam evaporation under a room temperature condition to form a resistive function layer, and not performing high-temperature annealing treatment after deposition is completed, so that a primary oxygen vacancy defect is reserved in the thin film; and then depositing a top electrode on the resistive function layer through thermal evaporation or electron beam evaporation to obtain the memristor. The resistive function layer is an aluminum oxide film which is not densified through annealing, and internal defects of the resistive function layer provide a channel for metal ion migration, so that the reversible resistive characteristic is achieved. The memristor device is simple in structure and suitable for normal-temperature process preparation, the stable resistance switching behavior can be achieved, excessive densification of a film layer and thermal damage of an ITO electrode interface caused by high-temperature annealing are avoided, and the memristor has high cycle durability and nonvolatile data retention capacity and has the stable bipolar resistance change characteristic.

Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.

Systems and methods for providing a memory sub-system controller selectively refresh data by differentiating between read disturb charge loss from data retention charge loss. The controller performs a read disturb induced charge loss (RDCL) scan operation on a portion of a set of memory components. The controller determines that a first bit error count (BEC) associated with the RDCL scan operation on the portion of the set of memory components transgresses a threshold value and determines whether the first BEC corresponds to a second BEC that represents data retention (DR) charge loss. The controller selectively refreshes data stored in the portion of the set of memory components based on determining whether the first BEC corresponds to the second BEC that represents DR charge loss.

The invention relates to the technical field of power transmission lines, and discloses a power transmission line state multi-dimensional sensing method and system based on multi-source data fusion, and the method comprises the steps: dividing the fault evolution into a germination period, a development period and a critical period through a fault layering judgment mechanism, enabling each stage to be matched with a differential caching strategy, and achieving the collaborative optimization of fault data retention and resource utilization. Through a full-link value quantification model, three dimensions of fault state, time decay and data type, confidence gain, link adaptation and redundancy loss correction are fused, a unified priority standard is provided for caching, routing and transmission, and the transmission efficiency of a communication window is improved. A dual-mode reconstruction strategy is adopted, fault physical mechanism deduction and space-time correlation interpolation are combined, missing data are reliably complemented through fusion judgment and conflict analysis, it is ensured that a reconstruction result conforms to a physical rule, and a complete time sequence support is provided for fault traceability.

The invention belongs to the technical field of engineering machinery load safety monitoring, particularly discloses a lifting winch load monitoring system based on dynamic weighing, and aims to solve the problems of large weighing error, response lag and disjunction of early warning and control in the conventional lifting winch load monitoring under a dynamic working condition. According to the system, multi-dimensional parameter acquisition, multi-source interference elimination, load state full-dimensional evaluation, safety risk active intervention and full-process data retention are realized through cooperative work of six modules including a data acquisition module, a data preprocessing module, a dynamic load correction module, a load state evaluation module, a multi-stage early warning and control module and a data storage and tracing module. The system can effectively adapt to the dynamic working conditions of different types of lifting winches, improves the load monitoring precision and response timeliness, upgrades passive alarm to pre-judgment, intervention and tracing full-chain safety management and control, guarantees the operation safety of the lifting winches, and is suitable for various lifting winches in the fields of ports, mines, buildings and the like.

A computer-implemented method for deleting an individual's personal data is provided. A request to delete the individual's personal data may be received from a communication device associated with the individual. The individual's identity may be verified. Responsive to verifying the individual's identity, the request may be compared with a data retention policy, wherein the data retention policy may comprise a data retention end date. If a date of the request is earlier than the data retention end date, a denial notification may be generated and transmitted to the communication device to notify the individual that the request is denied based on the data retention end date. Responsive to a determination that the date of the request is later than the data retention end date, the request to delete the individual's personal data from one or more associated databases may be processed.

The invention relates to the technical field of computer NAND chip storage, in particular to an NAND Flash data storage system and method, and the system comprises a cloud inventory management platform; the wireless storage device is provided with a plurality of storage positions for storing hard disks, and a wireless charging module is arranged in each storage position; the energy receiving modules are arranged in the storage hard disks; according to the technical scheme provided by the invention, a cloud-controlled penetration type wireless trickle charging technology is adopted, and on the premise of keeping sealed packaging of the equipment and unattended warehouse, automatic and periodic data refreshing of large-batch and multi-form NAND Flash storage equipment is realized, so that the problem of data retention failure caused by long-term inventory is fundamentally solved, and the service life of the NAND Flash storage equipment is prolonged. Meanwhile, the management cost, the operation risk and the complexity are greatly reduced, and the reliability and the management efficiency of inventory products are remarkably improved.

Technology for re-calibrating a temperature coefficient (Tco) for reading NAND memory cells. The Tco may be re-calibrated based on an amount of data retention impact to NAND memory cells since the NAND memory cells were programmed. The data retention impact may be measured by determining a shift to a candidate Vt distribution. The candidate Vt distribution may be selected as one that exhibits a significant data retention impact. The Tco may include, but is not limited to a bit line voltage Tco or a Vread Tco. The bit line voltage Tco may be used to establish the bit line voltage during read. The Vread Tco may be used to establish a voltage to unselected word lines during read.

The invention relates to the field of data access, and particularly provides an MPT-based block chain database system, a data access method, a terminal and a medium, the system comprises a native MPT storage engine used for realizing an MPT node structure in a disk and a memory, and the node structure comprises branch nodes, extension nodes and leaf nodes; the asynchronous I / O module is used for realizing non-blocking disk operation based on Linux iouring; the file system bypass module is used for supporting direct access to the block device; the versioning concurrency control module is used for realizing lock-free reading through an immutable Trie structure and atomic pointer updating; and the dynamic compression module is used for dynamically adjusting a historical data retention strategy according to the disk space utilization rate. The MPT structure storage engine is realized, basic data support is provided for a high-performance block chain system, serialization overhead is eliminated, and storage efficiency is improved.

The invention relates to a batch chart automatic generation method and system based on data fusion and cleaning, electronic equipment and a computer readable storage medium, and the method comprises the following steps: S1, obtaining a measurement data set of a product from at least one data source based on an access parameter preset in a spreadsheet application program; s2, in response to a first interaction operation of a user in the spreadsheet application program, selecting one of a plurality of predefined data retention strategies, and running a first script program to generate a regular data set; the data retention strategy is based on a multiple measurement sequence of the same product and is configured to retain a data subset conforming to a specific quality state and a sequence position; s3, in response to a second interaction operation of the user in the statistical analysis software, selecting one of a plurality of predefined chart generation modes, and generating statistical charts with unified naming specifications in batches; and S4, in response to a third interaction operation of the user in the spreadsheet application program, selecting a report output format.

Time tracking for memory apparatuses is described herein. Time information (e.g., timestamps) received for each power event can be utilized to generate statistical information indicating the duration a computing device has spent in a particular power state. This statistical information can be retrieved by manufacturers for purposes such as data retention analysis.

The present invention provides a memory drive device, an information processing device, and a control method that reduce data corruption due to retention characteristics and improve reliability. [Solution] The SSD (Solid State Drive) in the information processing device 100 comprises a data storage unit including a data storage area and a test storage area, and a control unit. The data storage area is composed of rewritable non-volatile memory and stores data used for information processing. The test storage area is composed of non-volatile memory and stores predetermined test data. The control unit determines that a predetermined data retention period has been reached if the date and time information obtained from the information processing device is accurate and the power outage period based on the date and time information exceeds a threshold period. If the date and time information is inaccurate, the control unit determines that a predetermined data retention period has been reached based on an index value related to storage failures in the test storage area and performs a rewrite of the already stored data to the data storage area.

The present disclosure relates to a 2T memory cell, and more particularly to a technology including a first transistor that performs data write and erase operations and a second transistor that performs a data read operation. The first transistor is formed vertically above the second transistor, and the first drain of the first transistor serves as the second gate of the second transistor. The channel of the first transistor has a longer effective channel length than the channel of the second transistor. High-density integration is possible by forming the first transistor through a self-aligned process, and data retention characteristics are improved by forming the channel of the first transistor with a semiconductor material having a wide bandgap such as polysilicon or IGZO. The 2T memory cell according to the present disclosure can simultaneously achieve high-speed operation and high integration density.

Techniques are provided for adaptive usage of storage resources using data source models and data source representations generated using the data source models. One method comprises obtaining sampled data generated by sampling source data from a data source; fitting a data model to the sampled data to obtain a representation of the sampled data; obtaining a classification of the sampled data into one of multiple predefined retention models; and adapting a usage of one or more storage resources that store the retained data based on the representation and the classification. The adaptive storage resource usage may comprise, for example: (i) varying a data retention model based on an age of the sampled data; (ii) evicting cache data based on the representation; (iii) moving the retained data to a different storage tier; and (iv) determining an amount of time to store the retained data.

The invention discloses a PLC (Programmable Logic Controller) power failure data retention system based on a Linux memory mapping technology. The PLC power failure data retention system comprises a hardware subsystem and a software subsystem, the hardware subsystem comprises a CPU module for running a real-time Linux operating system; the power failure detection module is used for monitoring the voltage of an external power supply and triggering hardware interruption; the super capacitor power supply module is used for providing backup power after power failure; and the EMMC storage module is used for storing PLC key data. The software subsystem comprises a memory mapping driving module for mapping a physical space of the EMMC storage module to a system space to form a shared memory mapping area; the synchronization guarantee module is used for realizing lock-free synchronous access control by operating a state register; and the power failure control module responds to hardware interruption to start a data synchronization process. According to the system, lock-free synchronous access control between a user mode and a kernel mode is achieved through atomic bit flipping and exclusive-OR logic, it is ensured that a complete data block is synchronized to an EMMC storage module, the reliability problem of power-down data retention of a PLC system is solved, and the data synchronization efficiency and the system stability are improved.

To efficiently suppress an increase in access time accompanying read assist in a semiconductor device including an SRAM.SOLUTION: The read assist circuit is configured to be switchable between valid and invalid, and when the read assist circuit is valid, a word line voltage applied to the word line is reduced in order to secure a static noise margin of the memory cell. The SNM detection circuit SNMD includes a replica memory cell RMC configured to have a data holding capability lower than that of the memory cell. The SNM detector SNMD detects the static noise margin of the memory cell in a pseudo manner by using the replica memory cell RMC, and switches the validity / invalidity of the read assist circuit according to the detection result.SELECTED DRAWING: Figure 4

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

The invention discloses a display panel and a brightness compensation method thereof, and the method comprises the steps: obtaining a global image; identifying an effective display area of each display panel according to the global image; adjusting a focal length corresponding to each display panel according to the parameter information of each display panel to obtain a standard focal length, and sequentially obtaining an actually measured local image of each display panel through an image obtaining module; and generating compensation data of each display panel according to the actually measured local image of each display panel. After the effective display area of each display panel is identified, the compensation data can be subsequently determined according to the obtained characteristics of each pixel in the effective display area, each pixel is compensated, the retention rate of edge data of the effective display area is improved, and the compensation precision of the display panel is further improved.

A memory device includes a memory cell array including a plurality of word lines, a sense amplifier circuit, and a control logic circuit. The sense amplifier circuit is configured to amplify read data obtained from active memory cells of an active word line among the plurality of word lines, and provide write data from the memory controller to the active memory cells. The control logic circuit is configured to store inverted first data in memory cells of a first word line of the plurality of word lines by inverting the first data of the memory cells of the first word line stored in the sense amplifier circuit based on activation of the first word line.

The invention relates to the technical field of DNA information storage, and discloses a method for prolonging data storage time and application, the method comprises the following steps: data is converted into a DNA sequence with a preset length, DNA is synthesized and stored, primary amino groups in basic groups of the DNA are independently modified by protective groups, the protective groups are selected from-COR, and the primary amino groups in the basic groups of the DNA are independently modified by the protective groups. R is selected from alkyl of C1-C6, substituted or unsubstituted naphthenic base of C3-C8 or substituted or unsubstituted phenyl. According to the method for prolonging the data storage time, the degradation rate of DNA can be remarkably inhibited, the stability of the DNA can be improved so as to realize long-time stable storage of the data, and the method is particularly suitable for forming a DNA storage scene with limited conditions, namely, the method is suitable for DNA synthesis in large companies with advanced technologies and equipment and also suitable for large companies with advanced technologies and equipment. The method is also suitable for DNA synthesis of small companies, and has application prospects and potential.

The invention provides a configurable automatic data archiving method and system based on a storage process, and belongs to the technical field of database data life cycle management.The method comprises the following processes that firstly, an archiving task is initialized, and a configuration table archiving rule is loaded; automatically judging and creating an archiving history table; secondly, dynamically calculating an archiving reference date; archiving conditions are generated, and data archiving and source table cleaning are executed in batches; abnormities are processed through log and transaction control, and data archiving and source table cleaning are completed; and finally, task circulation and exception handling are performed, and configurable and automatic historical data management is realized. The method solves the problems that an existing data archiving scheme is high in hard coding dependency, lacks unified configuration, is high in batch processing risk, is weak in fault tolerance and traceability, and is disordered in historical table management, is suitable for batch backup and archiving of historical data and source table cleaning in a core business system, guarantees the performance of a core table, and meets the requirements of data retention compliance.

This disclosure relates to the semiconductor field and proposes a memory and electronic device. The memory includes an array driving circuit, a memory cell array, a feedback cell array, and an output unit. The memory cell array includes memory cells, and the feedback cell array includes feedback units. The array driving circuit controls the memory cells to enter a data readout phase. The memory cells are used to read stored data to the corresponding feedback unit and output unit when entering the data readout phase. The feedback unit is used to rewrite the read data back into the memory cell. The output unit is used to output the data read from the memory cell. The memory of this disclosure adds a feedback unit to the 2TOC DRAM memory cell, and enhances the anti-interference capability and data retention capability of the floating memory node by using the feedback unit to rewrite the read data back into the memory cell during the data readout phase, thereby improving readout stability and non-volatile memory characteristics.

A disclosed D flip-flop includes first and second stages. The first stage includes a first intermediate node. The second stage includes second and third intermediate nodes and a pair of transistors connected in series to the second intermediate node. The first and third intermediate nodes are connected to the gates of different ones of the transistors in the pair in order to provide feedforward and feedback paths for maintaining the voltage level of a signal on the second intermediate node when a clock signal is static and the second intermediate node is floating. Optionally, the second stage can also include a feedback loop (including an inverter and a multiphase clock-controlled tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of a signal on the third intermediate node when the clock signal is static and the third intermediate node is floating.

The present invention provides a highly reliable storage device having a long data retention time. This storage device has a peripheral circuit and a plurality of memory cells. Each of the memory cells has a first transistor and a capacitive element. The peripheral circuit has a second transistor and a third transistor. A first terminal of the first transistor is electrically connected to a first terminal of the capacitive element, and a second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor. Respective semiconductor layers of the first transistor, the second transistor, and the third transistor have mutually different compositions.

A maintenance system of a data storage device identifies which portions of the data storage device are more susceptible to data retention failures and other issues when compared with other portions of the data storage device. Various portions of the data storage device are identified as susceptible portions based on one or more characteristics. When the susceptible portions are identified, the maintenance system determines a frequency at which subsequent maintenance operations will be performed on the susceptible portions. The frequency may be based on the one or more characteristics, an amount of errors in data associated with the susceptible portion or a type of the susceptible portion.

A computer system provides transaction-level data retention policy inheritance. The system may perform operations including storing a first dataset comprising a plurality of transactions, each of the plurality of transactions comprising one or more data items; receiving a first transaction to the first dataset, the first transaction comprising one or more data items; determining a first retention policy for the first transaction; and storing the first retention policy with the first transaction. The system may further perform operations including calculating a deletion date for the first transaction based on the first retention policy; and storing the deletion date with the first transaction in the first dataset.

The embodiment of the present application provides a kind of phase change material and its manufacturing method, phase change memory and its manufacturing method, wherein the phase change material includes: first doped element, second doped element and phase change bulk material;Wherein, the first doped element and the second doped element can form chemical bond with the element in the phase change bulk material;The bond energy of the chemical bond formed is greater than the bond energy of the chemical bond between elements in the phase change bulk material;The first doped element and the second doped element belong to the elements of different groups in periodic table.The embodiment of the present application can improve the amorphous thermal stability and data retention of phase change material, so as to improve the electrical performance of phase change memory.