11 results about "Static noise margin" patented technology

To efficiently suppress an increase in access time accompanying read assist in a semiconductor device including an SRAM.SOLUTION: The read assist circuit is configured to be switchable between valid and invalid, and when the read assist circuit is valid, a word line voltage applied to the word line is reduced in order to secure a static noise margin of the memory cell. The SNM detection circuit SNMD includes a replica memory cell RMC configured to have a data holding capability lower than that of the memory cell. The SNM detector SNMD detects the static noise margin of the memory cell in a pseudo manner by using the replica memory cell RMC, and switches the validity / invalidity of the read assist circuit according to the detection result.SELECTED DRAWING: Figure 4

The invention provides a method for predicting the minimum working voltage of a static memory, and belongs to the technical field of semiconductors, and the method comprises the steps: obtaining the static noise margins of the static memory under at least two preset working voltages through simulation in a preset temperature range and a preset working state, at least two static noise margins are obtained under each preset working voltage; obtaining the ratio of the median of the static noise margin to the standard deviation under each preset working voltage; performing linear fitting on all the ratios to obtain a fitting line; and predicting the minimum working voltage of the static memory in the preset temperature range and the preset working state according to the fitting line. The ratio in the application can represent the yield of the static memory, and the minimum working voltage of the static memory in the predetermined working state can be accurately predicted according to the fitting line by performing linear fitting on all the ratios.

This application provides a method for adjusting the minimum operating voltage of a static memory (SMC), belonging to the field of semiconductor technology. The method includes: simulating and obtaining the read static noise margin and write static noise margin of the SMC at at least two predetermined operating voltages within at least two predetermined temperature ranges; obtaining a first ratio of the median to the standard deviation of the read static noise margin for each predetermined operating voltage within each predetermined temperature range, and a second ratio of the median to the standard deviation of the write static noise margin for each predetermined operating voltage within each predetermined temperature range; performing linear fitting on all the first ratios and all the second ratios within each predetermined temperature range to obtain a first fitting line and a second fitting line, to determine the changing trend of the minimum read operating voltage and the minimum write operating voltage with temperature; and adjusting the threshold voltage of at least one transistor when the changing trend does not meet the requirements, thereby improving the performance of the SMC.

The invention discloses a semiconductor device, a forming method thereof and a chip, and the method comprises the steps: forming an active groove in at least part of a fin part, and enabling a corner position point in the active groove to have a first transverse distance with an outermost position point on an adjacent side wall in the active groove; at least removing and modifying the corner part in the active groove to form a modified layer; removing the modification layer to form an adjusted active trench, a corner position point in the adjusted active trench having a second lateral distance from an outermost position point adjacent to the sidewall in the adjusted active trench, the second lateral distance being smaller than the first lateral distance; and forming a source-drain region at the adjusted active trench. According to the invention, the problems of static noise margin and device function failure caused by formation of the source and drain regions with poor morphology are solved.

This application relates to a write auxiliary circuit, a memory, and an electronic device. The write auxiliary circuit includes: a logic switching circuit configured such that its input terminal is connected to a power supply voltage, and its control terminal receives a level control signal to provide different voltages; an inverting amplifier configured such that its non-inverting input terminal is grounded, its inverting input terminal is connected to the output terminal of the logic switching circuit, and its output terminal is connected to the bit line and the inverted bit line to reduce the bit line potential; and a resistor selector configured such that its input terminal is connected to the inverting input terminal of the inverting amplifier, its control terminal receives a resistor control signal, and its output terminal is connected to the output terminal of the inverting amplifier to provide different feedback resistor values. By achieving a negative voltage output through the operational amplifier circuit, the gamma ratio and write quiescent noise margin are increased, effectively improving the write capability of the SRAM.

A read assist circuit is configured so as to be capable of switching validation / invalidation, and lowers a word line voltage applied to a word line in order to secure a static noise margin of a memory cell when being valid. An SNM detection circuit has a replica memory cell configured so as to make data retention ability lower than that of memory cell. The SNM detection circuit detects the static noise margin of the memory cell in a pseudo manner by using the replica memory and cell, switches the validation / invalidation of the read assist circuit depending on a detection result.

This invention provides a semiconductor device structure and manufacturing method. The structure includes a semiconductor substrate having N-type and P-type device regions and corresponding gate structures; a dielectric barrier layer is located on the semiconductor substrate and P-type gate structure in the P-type device region; a stress layer is located on the semiconductor substrate and N-type gate structure in the N-type device region, and is also located on the dielectric barrier layer in the P-type device region. This invention introduces a dielectric barrier layer in a full-coverage stress memory process, subjecting the N-type device to high tensile stress to improve performance, while simultaneously reducing the tensile stress on the P-type device to avoid performance degradation. This approach can significantly reduce the lower limit of SRAM operating voltage, improve static noise margin and write margin, and the process is simple and highly compatible.

The present application relates to direct measurement test structures for measuring static random access memory static noise margin, and discloses a test structure for measuring static noise margin (SNM) of one or more static random access memory (SRAM) cells, which can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In embodiments, an interconnect between an output of a first inverter and an input of a second inverter of an SRAM cell can be electrically disconnected using a shunt. During operation of the SRAM cell, an internal storage node within the SRAM cell can be electrically coupled to, for example, an external pin and a test device through the first TG and the second TG. An electrical parameter, such as a voltage, can be measured at the internal storage node through the external pin and used to calculate the SNM of the SRAM cell.

The invention relates to a multi-threshold 16T anti-radiation SRAM (Static Random Access Memory) storage unit circuit and a memory, a storage module in the circuit is of a bistable structure formed by two cross-coupled phase inverters formed by PMOS (P-channel Metal Oxide Semiconductor) transistors, and two storage nodes are formed; the redundant storage module adopts NMOS (N-channel metal oxide semiconductor) transistors to form a bistable structure, and two redundant nodes are formed to serve as redundant backups of the storage module; when the read-write operation control module reads or writes data, a word line is activated, and the data is read from the storage node and the redundant node or written into the storage node and the redundant node through the switched-on transistor; and the bit line driving module is used for driving the bit lines during reading and writing operations. According to the circuit, by introducing redundant nodes and a feedback mechanism, efficient resistance and recovery of single event upset and multi-node upset of a single node are achieved, the anti-radiation capacity is improved, the static noise margin, the read-write speed and the power consumption performance are optimized, and the circuit is suitable for reliable data storage requirements in a high-radiation environment.

The invention provides a method for adjusting the minimum working voltage of a static memory, and belongs to the technical field of semiconductors, and the method comprises the following steps: respectively simulating and obtaining a reading static noise margin and a writing static noise margin of the static memory under at least two preset working voltages in at least two preset temperature ranges; obtaining a first ratio of the median of the read static noise margin of each predetermined working voltage in each predetermined temperature range to the standard deviation, and a second ratio of the median of the write static noise margin of each predetermined working voltage in each predetermined temperature range to the standard deviation; and performing linear fitting on all the first ratios and all the second ratios in each preset temperature range to obtain a first fitting line and a second fitting line so as to judge the variation trend of reading the minimum working voltage and writing the minimum working voltage along with the temperature, and when the variation trend does not meet the requirement, adjusting the threshold voltage of at least one transistor so as to obtain the temperature of the transistor. The performance of the static memory is improved.