32 results about "Bit Test" patented technology

The invention relates to the technical field of electronic testing, and discloses a USB module multi-station synchronous testing and data association method and system, and the method comprises the steps: constructing a global schedulable resource map of a testing station, so as to create a resource load balancing table and a global testing database of the testing station; configuring a synchronous test controller of the test station by using the test task flow generated by the test station and the global schedulable resource atlas; reading the unique identity label of the USB module so as to establish an association mapping network of the USB module in the global test database; and executing multi-station synchronous testing and data association processing of the USB module based on the global schedulable resource atlas, the resource load balancing table, the synchronous testing controller, the collaborative optimization strategy set and the association mapping network. According to the invention, accurate synchronous control of multi-station test and automatic correlation analysis of test data can be realized.

The invention relates to the technical field of data storage, and discloses a memory particle test method, which comprises the following steps that: 32-bit memory particles relate to a first channel (16-bit) and a second channel (16-bit), the first channel (16-bit) and the second channel (16-bit) of the 32-bit memory particles correspond to physical blocks in the 32-bit memory particles, the 16-bit memory particles only relate to the first channel, and the second channel (16-bit) corresponds to physical blocks in the 32-bit memory particles. The first channel corresponds to a physical block in the 16-bit memory particle; all memory spaces of the 16-bit memory particles are scanned through a program of the 32-bit test system, if errors occur in the program, it is judged that the corresponding program relates to the second channel, codes related to the second channel in the test system are found, and the codes corresponding to the second channel are shielded. By means of channel shielding, code modification, address mapping and the like, compatibility of the 32-bit test system to two kinds of particles is achieved.

The present disclosure provides a system and method for designing a power management cluster using a no-code approach, enabling test reset delivery through the same path as a functional reset in test mode. The system includes at least one processor executing instructions stored in memory, the instructions comprising: generating a power instance from power component information; generating a reset controller instance upstream of the power instance to transmit a reset output to a target; setting first connection information between the target and the reset controller instance; generating a reset test controller instance including a test mode TDR block and a test control TDR block; setting second connection information between the reset and reset test controller instances; and generating hardware code based on the components and connection information.

The application discloses a three-dimensional stacked chip testing method based on multi-interface cooperation and parallel broadcasting, and relates to the technical field of integrated circuit testing.The method sets a USB controller on a master control chip layer to preload 116 bit testing instruction streams to a PRO_RAM on the chip;the states of each layer are configured by issuing instructions through JTAG;then, a coordinator FSM runs in a three-stage pipeline mode of instruction fetching, broadcasting and executing, instruction parameters are synchronously distributed to BIST controllers of target layers by using a source fan-out broadcasting bus;by introducing physically isolated shadow registers and active registers in the BIST controllers, the next group of instructions are prefetched and loaded in the background while the current task scanning and shifting are performed, and zero-bubble task switching is achieved;the application effectively reduces the transmission amount of repeated instructions, eliminates the time domain coupling of configuration and execution in the traditional architecture, and significantly improves the testing efficiency of the heterogeneous stacked chip.

The invention discloses testing equipment compatible with chip and wafer testing, and relates to the technical field of semiconductor testing, the testing equipment comprises a material table, a testing table and a transfer device, the top of the material table is provided with a conveying mechanism and a material box mechanism, the conveying mechanism extends in the longitudinal direction, and the testing table is provided with a material box; the two sides of the top of the conveying mechanism in the longitudinal direction are a feeding and discharging side and a material taking and placing side respectively, the material box mechanism is arranged close to the feeding and discharging side, the material box mechanism is used for containing a material bin, and the material bin is used for containing a diaphragm capsule bearing a chip; the test bench comprises a rack, a test mechanism and a loading mechanism, the test mechanism and the loading mechanism are arranged on the rack, a first loading and unloading station, a test station and a second loading and unloading station are sequentially arranged on the rack in the longitudinal direction, and the test mechanism is arranged above the loading mechanism and corresponds to the position of the test station; the transfer device is arranged at the top of the material table and is close to the material taking and placing side, and the transfer device extends in the transverse direction and crosses the test table. The testing of chips and wafers can be compatible, and the flexibility and the universality are better.

A method for performing an analog-to-digital conversion using an analog-to-digital converter (ADC) with a successive approximation register (SAR), the method comprising: performing bit tests using a digital-to-analog converter (DAC) circuit of the SAR-ADC to convert a first sample of an analog input signal into an N-bit output; before performing bit trials on a second sample of the analog input signal, precharging M bits of the N-bit output from the first sample onto the DAC circuit, where M is less than N; prior to conversion, comparing the second sample to a range having an upper limit and a lower limit, the upper limit and the lower limit being based on a representation of the precharged M bits; if the comparison indicates that the second sample is within the range, performing bit trials on the second sample to determine the remaining (NM) bits; if the comparison indicates that the second sample is not within the range, performing bit trials on the second sample to determine all N bits; and Controlling a value of M using at least one result of a previous bit attempt.

The present invention relates to a system and method for designing a power management cluster in a code-free manner, the system comprising at least one processor for executing at least one instruction for generating a power instance based on power component information; instructions to generate a reset controller instance disposed at a front end of the power instance and delivering a reset output to a target including the power instance; instructions to set first connection point information between the target and the reset controller instance; an instruction to generate a reset test controller instance including a test mode test data register block corresponding to the reset controller instance and a test control test data register block; an instruction for setting information of a second connection point between the reset controller instance and the reset test controller instance; instructions to generate hardware code based on the power instance, the reset controller instance, the first connection point information, the reset test controller instance, the second connection point information, and hardware code logic.

The application provides an STDF file analysis method and device and a storage medium. The STDF data stream is segmented, and each data segment obtained through segmentation is divided into compacted data based on PIR and PRR data types, so that the continuous data stream is divided into small block data of multiple logical levels. The required running memory for analyzing the small block data is small, the compacted data and the multiple small block data are analyzed in parallel based on computer multi-core operation, the analysis efficiency is improved, the analysis result is stored in a hardware storage device after the compacted data of one data packet is analyzed, the running memory is released, and the situations of lag and death are avoided. In addition, the analysis result including a test station, a test item and a test result is saved by using a multi-thread nested dictionary, which is equivalent to establishing a mapping relationship of each chip, a test item and a test result, and the test result of each test item of a single chip can be accurately searched.

The utility model discloses a sensor impact force testing device, which comprises an equipment base provided with a multi-station replaceable efficient testing structure. The multi-station replacement type efficient testing structure comprises a mounting groove, a pair of driving motors, a pair of adjusting screw rods, two pairs of moving blocks, a pair of sliding rails, two pairs of sliding blocks, a mounting table, three rapid clamping assemblies, a mounting frame and a tester. The utility model relates to the technical field of sensor impact force testing devices, and has the beneficial effects of solving the problems that the conventional sensor impact force testing device generally adopts a single-station testing mode, the testing efficiency is low, the requirements of the modern semiconductor industry on high-efficiency and high-precision testing are difficult to meet, the clamping structure is tedious to operate, the cost is high, and the like. The problems that frequent manual clamping is needed, the function of rapidly replacing stations is lacked, the test period is prolonged, and the production efficiency is affected are solved.

The present invention provides a BIT testing method for an electro-hydraulic servo valve in an aircraft remote electronic unit, relating to the field of aircraft control technology. The method comprises: within a communication cycle, a command channel and a monitoring channel in the remote electronic unit receive actuation commands from a flight control computer via the same digital bus; the command channel and the monitoring channel respectively parse the actuation commands, and based on the parsed actuation commands, execute BIT testing tasks for the high and low sides of the servo valve, respectively, using an error integrator or a two-stage comparison strategy; and the command channel transmits the BIT test results of the two channels and uploads the actual status information of the servo valve via a digital bus. The method ensures high integrity of the BIT test, effectively monitors failure modes such as electro-hydraulic servo valve coil faults, remote electronic unit drive circuit faults, and line faults, ensuring that common-mode faults do not occur during BIT testing of the remote electronic unit in the flight control system, thereby improving fault detection coverage.

A reset test system and a system-on-chip, which enable a test reset to be transmitted through the same path as a functional reset in a reset test mode. The reset test system includes a scan test controller configured to generate a scan test enable signal, a scan reset control signal, and a scan reset deactivation signal; a target reset test controller configured to generate a target reset test mode signal and target reset test data; a leading target reset controller configured to synchronize a leading reset input to a functional clock in a functional mode and to output the target reset test data as a leading reset output in a scan test mode; and a following target reset controller configured to receive the leading reset output as a following reset input, synchronize it to the functional clock in the functional mode, and output the target reset test data.

The invention provides an STDF file analysis method and device and a storage medium. The method comprises the following steps of: segmenting an STDF data stream, carrying out lamination data division on each data segment obtained by segmentation based on PIR and PRR data types, dividing a continuous data stream into small blocks of data of a plurality of logic levels, analyzing the small blocks of data with a small running memory, and carrying out parallel analysis on the lamination data and the plurality of small blocks of data based on computer multi-core operation, the analysis efficiency is improved; moreover, when the press fit data of one data packet is analyzed, the analysis result is transferred to the hardware storage device, so that the running memory can be released, and the conditions of lagging and dead halt are avoided; besides, analysis results including the test stations, the test items and the test results thereof are stored by adopting a multi-thread nested dictionary, equivalently, a mapping relation between each chip and the test items and the test results thereof is established, and the test results of each test item of a single chip can be accurately retrieved.

The application discloses a S7 protocol communication test method and device, equipment and a storage medium. The application obtains corresponding read-write request information based on a PLC data port; processes and classifies the read-write request information to obtain a processing classification result; performs a corresponding point test operation according to the processing classification result to obtain a communication test result. The application identifies and distinguishes the source of the read-write request through the PLC data port, and then processes and classifies the read-write request. Finally, the corresponding communication test result is obtained according to the processing classification result, the result visualization is realized, and the communication test efficiency and reliability are improved.

This application discloses an automated production scheduling method and apparatus for harmonic reducers, relating to the field of industrial control technology. The automated production scheduling method for harmonic reducers includes: acquiring a basic dataset for multi-station testing of the harmonic reducer; optimizing the test item set corresponding to the test samples to determine the target test sequence of the test samples and the target test time corresponding to the target test sequence; constructing an initial test scheduling scheme for multi-station testing based on the target test sequence and target test time; and solving the initial test scheduling scheme to obtain the target test scheduling scheme for the harmonic reducer. Because the test sequence of the test item set corresponding to the test samples is optimized, unnecessary station state switching waiting time is reduced; and by further solving the initial test scheduling scheme, the global optimality of the obtained solution is ensured, improving production efficiency and equipment utilization.

The present application belongs to the technical field of semiconductor, and particularly relates to a control method for quickly enabling and shielding multi-station test channels in wafer testing, which comprises generating a multi-station physical resource mapping matrix according to a hardware board card in a test initialization stage; when a station state is changed, a computer system broadcasts a station enabling control vector to each hardware board card; each board card performs an element-by-element logical AND operation on the vector by using a local mapping matrix, and performs a logical OR compression on a result row to generate a physical channel enabling vector to drive channel enabling or shielding. By adopting the above technical scheme, a station-level broadcast instruction and a local matrix operation of a hardware board card are cooperated to avoid the computer system from performing full-amount physical channel traversal and cross-board card state coordination at each station change; channel enabling state determination under resource sharing is completed in parallel by a special logic circuit built in each hardware board card, and real-time performance and certainty of multi-station dynamic adjustment are ensured.

The application belongs to the technical field of semiconductor chip testing, and particularly relates to a test matrix instant stop method based on target result triggering, which is suitable for a test matrix scene, and realizes instant termination of a test process by relying on a preset hardware signal line designed by connecting a pull-up resistor to Vcc and comprises the following steps: S1, a pre-test configuration stage, S2, a test matrix preparation execution stage, S3, a test matrix execution stage, and S4, an instant stop stage. A flexible configuration mechanism of test target event registration and stop event binding is constructed, and a special hardware signal line of connecting a pull-up resistor to Vcc is matched to realize global synchronous triggering and stopping across a board card, the traditional fixed sequence test mode is abandoned, and the core problems of executing redundant test items after a test target is achieved in the prior art, causing invalid consumption of test time and equipment resources, and lacking of unified synchronous stopping capability in multi-board card cooperative testing and high parallel / multi-station test period being greatly lengthened are solved.

A system for a memory module mounting test according to an embodiment of the present disclosure includes: a test tray on which a memory module array in which a plurality of memory modules are positioned in a predetermined pattern is loaded; a tester in which the test tray is able to be seated and a socket corresponding to the predetermined pattern is formed to perform a test on the memory module array; a transfer for transferring the test tray from an initial position to a seating position where the test tray is seated in the tester; and a mounter for mounting the memory module array transferred to the seating position in the socket.

A memory device comprising a plurality of sense amplifier circuits to sense data bits in response to parallel test signals from a plurality of memory banks, a plurality of comparators to compare the data bits from each of the plurality of sense amplifier circuits to a test bit, and a logic circuit to receive output signals of the plurality of comparators and output a test result, wherein each of the plurality of comparators receives the test bit, an evolving parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bits and the test bit in response to the evolving parallel bit test (PBT) signal, at least one logic state test set signal, and the test pass signal, and passes through the respective memory bank in response to the test pass signal regardless of the test operation.

The invention relates to the technical field of integrated circuit ATE testing, and provides a calibration method and system of ATE equipment, computer equipment and a readable storage medium, the ATE equipment is provided with at least two test stations, the test stations are configured to test parameters of a chip, and the method comprises the following steps: obtaining a reference input signal and a reference output signal of a reference chip, the reference input signal and the reference output signal meet a preset signal mapping relation; the control signal source applies a reference input signal to the reference chip; controlling the measuring unit to measure an actual output signal of the reference chip; and generating a control signal according to the deviation between the actual output signal and the reference input signal so as to adjust the input signal applied to the reference chip by the signal source, so that the actual output signal approaches or is equal to the reference output signal. In the scheme, the calibration process of multiple test stations eliminates the measurement deviation caused by hardware difference between different test stations, and ensures the consistency of the parameter test results of the chip in the subsequent mass production test.

The invention belongs to the technical field of chip testing, and particularly relates to an Aurora bus communication method based on a chip testing machine, which comprises the following steps: S1, building and initializing a system architecture: deploying a hardware architecture of PC + FPGA master control + multi-FPGA functional modules, and establishing a high-speed serial communication link among the modules through an Aurora bus; after the test machine is powered on, the PC terminal collects in-place states of all the FPGA function modules through a special instruction, distributes a unique attribute identifier for each FPGA function module in combination with a board card model and slot position information, and completes hardware readiness and identity calibration before communication; aurora bus parallel communication and FPGA distributed architecture are adopted, the multi-station test duration is not linearly increased along with the number of stations any more, and compared with a traditional PCIe bus scheme, the test efficiency is improved, and the efficient test requirement of large-scale chip production can be met; the communication performance is obviously optimized, and the communication time delay of the system is reduced by more than 50% by combining the characteristic of simplification of an Aurora bus protocol with the hardware acceleration capability of the FPGA.

To provide a semiconductor memory device that can operate suitably. [Solution] The semiconductor memory device comprises a memory cell array, a first pad electrode to which write data is input and read data is output, a comparator to which one input terminal is connected to the first pad electrode and a reference voltage is supplied to the other input terminal, a latch circuit to which the output signal of the comparator is latched according to a latch enable signal, and a second pad electrode to which a latch enable signal is supplied when write data is input. This semiconductor memory device is configured to perform a write data training operation. Furthermore, during the write data training operation, this semiconductor memory device receives test data of multiple bits via the first pad electrode and generates data indicating whether or not a bit error occurred when the test data was input. Furthermore, this semiconductor memory device is configured to output data indicating whether or not a bit error occurred.

The invention discloses a signal quality bit acquisition method and system, and the method comprises the steps: obtaining an input signal which comprises an analog signal and a switching signal; determining each status bit in the signal quality bits according to a preset rule and the input signal; the status bits of the signal quality bits comprise a test status bit, an invalid status bit, a valid status bit, a test or invalid status bit, a fault status bit and a degradation status bit; generating the signal quality bits according to the status bits; and generating an output instruction according to the signal quality bit. Through efficient analysis and effective combination of signal state bits under different working conditions, the availability state and fault condition of signals can be accurately described, more accurate and comprehensive signal quality bits are generated, the reliability of the signals can be effectively judged based on the states of the signal quality bits, and therefore corresponding operation instructions are output, the reliability of the system is remarkably improved, and the reliability of the system is improved. And meanwhile, a standardized technical normal form is provided for the acquisition of the signal quality bits.

This application provides a reset testing method, apparatus, and device, relating to the field of computer technology, aiming to solve the problems of high cost and low efficiency in RAID card reset testing for reset scenarios in related technologies. The method includes: obtaining a target reset type number, and determining the target reset information corresponding to the target reset type number based on the correspondence between the reset type number and reset information; if the reset type in the target reset information is a hard disk reset, sending the target reset information to the disk array to trigger the disk array to execute a hard disk reset process; if the reset type in the target reset information is a host reset, determining whether it needs to be executed in an I / O scenario, and sending the target reset information to the disk array to trigger the disk array to execute a host reset process or execute a host reset process in I / O processing.

The invention discloses an S7 protocol communication test method and device, equipment and a storage medium. The method comprises the following steps: acquiring corresponding read-write request information based on a PLC data port; processing and classifying according to the read-write request information to obtain a processing and classifying result; and executing a corresponding point location test operation according to the processing classification result to obtain a communication test result. According to the method, the source of the read-write request is identified and distinguished through the PLC data port, then the read-write request is processed and classified, and finally the corresponding communication test result is obtained according to the processing and classification result, so that result visualization is realized, and the communication test efficiency and reliability are improved.

The invention relates to a reset test system and a system on chip comprising the same. The system can transmit a test reset signal through a path same as a function reset path in a reset test mode. The system comprises a scan test controller for generating scan test related signals, a target reset test controller for generating reset test signals, and a preamble and subsequent target reset controller for realizing reset synchronization and transmission, so that the test coverage rate can be improved.

The invention discloses a multi-gear test mode control circuit based on negative voltage triggering and a method thereof. According to the scheme, a negative voltage pulse generated by battery anti-reverse-connection detection is multiplexed as a unique external trigger, and an inlet signal is subjected to on-chip shaping and cascade frequency division counting and then is in a set test mode; after entering, the on-chip test beat clkdec is output through time sequence conditioning, a state sequence is driven to form a multi-bit state code, the multi-bit state code serves as an equivalent test vector, a gating matrix is controlled through decoding, and different tested signals are routed to an observation pin in a mutually exclusive mode to be read out; the whole process is driven by the number of external pulses, and reset exit and repeated execution are supported; compared with the prior art, on the premise that a test pin and a communication time sequence do not need to be newly added, lightweight on-chip self-test (BIST) which is simple in structure and robust in time sequence is achieved, gears and beats can be configured in a parameterized mode, and the on-chip self-test device is suitable for mass production test and on-site rapid verification of power management ICs and similar analog mixed signal devices.

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a system comprising a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the test board includes a functional / interface application specific integrated circuit (ASIC) component, and the test board includes a component configured to generate a simulated indication that a resource from a source external to the functional / interface ASIC is stable, and a tester configured to direct testing of the plurality of DUTs, wherein the tester is communicatively coupled to the functional / interface ASIC. In one embodiment the ASIC is a field programmable gate array (FPGA).

The invention discloses an eMMC abnormal reset control method and device, a medium and equipment, and relates to the technical field of storage chips, and the method comprises the steps that a PC host issues a global configuration command to a test board main control module for global configuration; a reset type execution type command is sent; when the eMMC chip to be tested holds the DAT0 bus, the test board main control module detects the level state of the DAT0 bus after executing an MMC protocol command or sending data; executing power reset, software reset and hardware reset according to the type of the reset type execution type command; and according to the configured power supply pull-down time and the reset port pull-down time, the level is reduced after the level reaches the corresponding time. Through cooperation of the PC host and the test board master control, the reset operation is automatically controlled by means of software commands, the test efficiency is greatly improved, a large number of reset test tasks can be completed in a short time, and the large-scale test requirement is met. And three reset modes of power supply, hardware and software are supported, and the reset test requirements of the eMMC chip are comprehensively met.

The invention provides a verification method and a verification device for a standard cell library. Standard units to be tested are classified into combinational logic units and sequential logic units, then classification is carried out according to the number of output ports, simulation is carried out on different types of standard units to be tested, problems can be found in time, and adjustment and debugging can be carried out in time; the input ports of the same type of the combinatorial logic unit and the sequential logic unit are integrated, so that the input ports with the same function correspond to the same bit test vector, redundant test vectors are removed, and the verification time is shortened; the simulation output in the simulation process is collected while simulation is executed, and the top layer output end and the simulation analysis end are connected at the same time, so that it is ensured that output signals of the same standard unit to be tested are simultaneously tested by a machine table and collected by a simulation test, verification accuracy is improved, excessive dependence on the test machine table is avoided, and verification efficiency is improved.

The invention discloses a method for realizing SDRAM (synchronous dynamic random access memory) function performance online detection based on a JTAG (joint test action group) tool. The method comprises the following steps: designing an SDRAM function performance test program; wherein the size of a target file of the function performance test program does not exceed the size of a cache with an SRAM mode in the CPU; setting initial address information of a code segment, a static data segment, a data segment and a stack segment in the function performance test program; a CPU emulator is used for controlling a PC pointer value logic address through a JTAG interface so as to complete the skipping function of the PC pointer, and a cache with an SRAM mode in a CPU is switched to the SRAM mode; and loading the function performance test program to a cache with an SRAM mode in the CPU to realize the execution of the test program. According to the method, the problems that the boundary scanning test is low in test efficiency and the internal BIT test is insufficient in test coverage rate are solved, so that the quality and reliability of delivered products are improved.