129 results about "Decision circuit" patented technology

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

A receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuit configured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.

A circuit arrangement includes a preprocessing circuit configured to obtain context information related to a user location, a learning circuit configured to determine a predicted user movement based on context information related to a user location to obtain a predicted route and to determine predicted radio conditions along the predicted route, and a decision circuit configured to, based on the predicted radio conditions, identify one or more first areas expected to have a first type of radio conditions and one or more second areas expected to have a second type of radio conditions different from the first type of radio conditions and to control radio activity while traveling on the predicted route according to the one or more first areas and the one or more second areas.

High speed of an analog-digital converter of a semiconductor device is achieved. A voltage quantizer circuit includes: a first comparator including a first input transistor inputting differential input voltages, and defining a value of a first bit of a digital signal; and a second comparator including a second input transistor being different from the first input transistor, and defining a value of a second bit of the digital signal. A correction code decision circuit decides a correction code for correcting a common-mode voltage of the differential input voltages, based on a conversion end signal output from the voltage quantizer circuit. A common-mode voltage regulator circuit regulates the common-mode voltage by adding or subtracting a corrected voltage based on the correction code to or from the differential input voltages.

A driver circuit that displays received display data on a display panel is provided. The driver circuit includes: a first register circuit, holding display control data used for controlling display of the display data on a display panel and outputting the display control data at a predetermined timing; multiple second register circuits, holding decision data with predetermined logic; a decision circuit, outputting a decision result indicating no abnormality has occurred in response to a logic of decision data held in second register circuits being a predetermined logic, respectively, and display control data held in the first register circuit being active; and a mask control circuit, controlling so that display control data held in the first register circuit is output to a circuit that performs display control of the display panel in response to a decision result output from the decision circuit indicating that no abnormality has occurred.

The on-off keying (OOK) receiver has a discontinuous automatic gain control (AGC) that sets the gain at the start of each frame and locks the gain setting for the remainder of that frame, preventing the OOK data from causing instability in the AGC loop. The AGC controller initializes the gain settings of the low-noise amplifier (LNA), low-pass filter (LPF), and programmable gain amplifier (PGA) to maximum values. The LNA, LPF, and PGA are in series and provide an input signal to the rectifier, which produces a voltage output to the 1 / 0 data decision circuit. The level detector compares the voltage output with two thresholds. When either threshold is exceeded, the AGC controller steps down the gain setting until the voltage output is between the two thresholds, at which point the gain setting is locked for the remainder of the current frame. When a long string of 0 data is detected between frames, the frame detector resets the AGC controller between frames. The LNA gain is reduced last.

The present disclosure provides a wireless communication device and method for controlling activation of a radio frequency (RF) transmit signal generation circuit. The wireless communication equipment comprises a communication processor and a transceiver; the transceiver is controlled by the communication processor and performs wireless communication. Wherein the transceiver comprises: a phase locked loop (PLL) circuit for generating a first oscillation signal based on a clock frequency signal; an RF transmission signal generation circuit for generating an RF transmission signal based on the first oscillation signal received from the PLL circuit and a baseband transmission signal received from the communication processor; and a first decision circuit for receiving a first phase comparison signal from a first phase comparator of the PLL circuit and controlling activation of at least one component of the RF transmit signal generation circuit based on the first phase comparison signal, where the first phase comparison signal indicates whether a phase of the first oscillation signal is fixed.

A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

A control circuit controls a multiphase power converter which includes plural power stage circuits, so as to convert an input power to an output power. The control circuit includes: a current sensing circuit, for sensing an output current for generating a current sensing signal; a transient detection circuit, for generating a transient indication signal by an output voltage; and a phase decision circuit, for generating a phase decision signal by a processed sensing signal and the transient indication signal, for determining an activated phase number. The phase decision circuit includes: a low-pass filter, for generating a low-pass-filtered signal by low-pass: filtering the current sensing signal; and a multiplexer, for adaptively selecting the current sensing signal or the low-pass-filtered signal to be the processed sensing signal according to the transient indication signal.

Apparatuses and techniques for local-bank-level scheduling enhancement of usage-based-disturbance mitigation based on global-bank-level control are described. To enable efficient utilization of timing resources, a memory device includes a refresh control circuit implemented at a global-bank level of the memory die and a mitigation decision circuit implemented at a local-bank level of the memory die. The refresh control circuit determines currently available timing resources for mitigating usage-based disturbance and generates a control signal to pass this information to the mitigation decision circuit. The mitigation decision circuit schedules the mitigation actions to efficiently utilize the currently available timing resources and ensure that different conditions associated with usage-based-disturbance are mitigated in order of priority. In this manner, available timing resources are efficiently utilized to decrease a risk of the memory device being subjected to usage-based disturbance. Furthermore, these techniques can be performed without significantly increasing cost or die size.

An external chip driving system includes a decision circuit, multiple first adjustable enhancement circuits, multiple second adjustable enhancement circuits, a pull-up circuit, and a pull-down circuit. The decision circuit outputs first and second decision signals based on a frequency signal and an input signal. In response to the first and second decision signals and one of the first selection signals, each of the first adjustable enhancement circuits generates a first control signal. In response to the first and second decision signals and one of the second selection signals, each of the second adjustable enhancement circuits generates a second control signal. Because the signal amplitude attenuates and becomes distorted during high-speed data transmission, in this disclosure, the first driver in the pull-up circuit is activated in response to the corresponding first control signal, and the second driver in the pull-down circuit is activated in response to the corresponding second control signal, thereby increasing the slew rate of the output signal and reducing the distortion of the output data.

The utility model discloses a circuit for improving the safety of a bridge circuit for magnetic bearing suspension current. The circuit comprises an intercommunication detection module and a driving control module, the intercommunication detection module comprises a first logic circuit, a second logic circuit and a hybrid decision circuit; the first logic circuit comprises a first OR gate and two first NOT gates, in two paths of enable signals of the double-path magnetic suspension bearing, the negative current of the first enable signal and the positive current of the second enable signal are respectively input into the input ends of the two first NOT gates, and the output ends of the two first NOT gates are correspondingly connected with the two input ends of the first OR gate; the second logic circuit comprises a second OR gate and two second NOT gates, the positive current of the first enable signal and the negative current of the second enable signal are respectively input into the input ends of the two second NOT gates, and the output ends of the two second NOT gates are correspondingly connected with the two input ends of the second OR gate; according to the utility model, intercommunication of two MOS transistors on the same bridge arm can be avoided, the structure is simple and reliable, the cost is low, and the circuit is suitable for large-scale mass production.

An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.

The application discloses a dual-mode event trigger circuit based on light detection and optical synapse, comprising a detection module and a detection module; the detection module is used for triggering based on light events or voltage events, converting received optical signals or electrical signals into current signals, and transmitting the current signals to the detection module; the detection module is used for collecting current signals and performing corresponding event detection; wherein the detection module is configured with an optoelectronic device integrating light detection and optical synapse functions, when the optoelectronic device is subjected to light and no external voltage is applied, the optoelectronic device behaves as a light detection mode, at the same time, the detection module works in a light event detection mode; when the optoelectronic device is simultaneously subjected to an external voltage and light, the optoelectronic device behaves as an optical synapse mode, at the same time, the detection module works in a voltage event detection mode. The circuit realizes dual-mode event triggering by using simple devices, has compact circuit structure, high device integration, does not need a complex multi-stage decision circuit, and effectively reduces energy consumption.

The invention provides an orientation device for an IRS communication system. The orientation device comprises an antenna and a signal detection decision circuit, the antenna is arranged on user equipment UE, a spherical or ellipsoidal outer surface is adopted, the surface is composed of a series of identical surface elements, and each surface element is independently connected with a signal detection decision circuit. By using the device and the corresponding control method provided by the invention, the direction of arrival can be quickly detected, and a data link is established between the IRS and the user UE according to the azimuth angle of radiation between the user UE and the IRS. According to the device structure, the UE can have higher directivity when receiving the signal from the IRS, and misjudgment of the signal radiation direction is avoided.

To provide a PFM control circuit that can reduce possibility that overcurrent occurs.SOLUTION: A PFM control circuit 15 includes a drive output 37b that outputs drive signals SDRV for driving switching elements 23, a first comparison circuit 31 that compares first monitor signals related to output voltage on the secondary side of a switching regulator 17 with a first reference value to generate first comparison signals, a second comparison circuit 43 that compares second monitor signals related to current flowing through the switching elements 23 with a second reference value to generate second comparison signals, a determination circuit 47 that is configured to determine whether or not to expand one of the HIGH width and the LOW width of clock signals CLK based on the first comparison signals and the second comparison signals and generate expansion signals SXTN that indicate the result of the determination, a pulse generation circuit 45 that includes an expansion circuit 49 that generates a pulse signal SPLS from the clock signals CLK in response to the expansion signals SXTN, and a drive circuit 53 that provides the drive signals SDRV to the drive output 37b.SELECTED DRAWING: Figure 1

The invention discloses a motor driver for adjusting power based on a shared voltage. A motor driver includes a shared voltage difference calculation circuit, a duty ratio decision circuit, a signal generator circuit, a control circuit, a drive circuit, and an output stage circuit. The shared voltage difference value calculation circuit calculates a difference value between the shared voltage received by the output stage circuit and a critical value. The duty ratio determination circuit determines a duty ratio adjustment value according to the difference value. The signal generator circuit adjusts the plurality of waveform signals according to the duty cycle adjustment value. The control circuit outputs a control signal according to a plurality of waveform signals. The driving circuit outputs a driving signal according to the control signal. The output stage circuit operates according to the shared voltage and the driving signal to drive the motor.

A sequence detection device includes a feed-forward filter, a feedback filter, a combining circuit, a decision circuit, and a sequence detection circuit. The feed-forward filter processes a received signal to generate a first equalized signal. The feedback filter processes a symbol decision signal to generate a second equalized signal. The combining circuit combines the first and second equalized signals to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the first equalized signal, and includes a region estimation circuit and a trellis selection circuit. The region estimation circuit is independent of the decision circuit, and categorizes each sample of the sample signal into one region. The trellis selection circuit selects one trellis scheme for branch metric calculation according to region estimation results output from the region estimation circuit.

The present invention relates to a floating omnidirectional maneuverable platform, method and application for surface clusters, belonging to the field of cluster intelligence technology; it includes a floating shell, a perception and decision module, a drive execution module and a power supply module. Through the cooperation of each module and in combination with a power distribution method, an omnidirectional maneuverable platform that can be used to verify the self-organizing motion algorithm of clusters in open water environments is obtained. The present invention integrates perception, decision-making and execution into one, and through the combined use of a 360° angle controllable servo and a camera module, it has the ability to actively perceive environmental information at 360°; the perception and decision circuit board has a built-in cluster self-organizing motion control algorithm, and the drive execution circuit board has a built-in thrust distribution algorithm. Combined with three propeller thrusters distributed at 120° intervals, it has the ability to move omnidirectionally on the water surface. It has the advantages of stable operation, strong flexibility and easy development, good engineering application value, and helps to improve the portability of cluster algorithms to machine clusters.

A cardiac treatment device, including:stimulation circuitry configured to generate a non-excitatory electrical signal which, when applied to ventricular tissue during a ventricular refractory period thereof improves a condition of heart failure in human patients;atrial arrhythmia detection circuitry; anddecision circuitry which controls the stimulation circuitry to delivery said signal, also when said atrial arrhythmia detection circuitry detects an atrial arrhythmia.

An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.

A pattern inspection device according to one embodiment of the present invention is characterized by being provided with: an optical image acquisition means for acquiring an optical image of a sample to be inspected on which a pattern is formed; a parameter range setting circuit that sets a range of reference image generation parameters on the basis of the degree of coincidence with past inspection condition parameters; a filter function generation circuit that generates a plurality of filter function candidates using values within the set range of the reference image generation parameters; a determination circuit that determines a filter function for creating a reference image from among the generated candidates of the plurality of filter functions; a reference image creation circuit that creates a reference image using the determined filter function; and a comparison circuit that compares the optical image with the reference image.

The present invention discloses an anti-misfire protection module for preventing the safety and control device of a carrier rocket from misfire, comprising: an A / D sampling circuit for collecting and measuring the voltage of the detonation preparation output terminal and the detonation output terminal of the safety and control device. A protection logic circuit electrically connected to the A / D sampling circuit and the safety and control logic module of the safety and control device, respectively, for receiving signals from the A / D sampling circuit and the safety and control logic module and performing protection operations, and outputting a detonation circuit breaker control signal when it is determined that there is a hidden danger of misfire. A protection decision circuit for receiving the detonation circuit breaker control signal and driving the protection switch array to disconnect. A protection switch array electrically connected to the detonation output terminal and the detonator of the safety and control device, respectively, is controlled by the protection decision circuit to cut off the detonation output terminal and the detonator to prevent the safety and control device from misfire. It has excellent integration and can effectively improve the safety and reliability of the safety and control device by controlling the on and off of the detonation path.

A switching regulator includes: a phase number signal generator circuit which includes: a current sensing signal differentiator circuit for performing differentiation on a current sensing signal to generate a current differentiation signal; a current sense signal filter circuit for filtering the current sense signal to generate a filtered current signal according to the current differentiation signal; and a phase number decision circuit for deciding a phase number signal according to the filtered current signal; and an AQR signal generator circuit which includes: a voltage sensing signal differentiator circuit for performing differentiation on a voltage sensing signal to generate a voltage differentiation signal; and plural comparator circuits for comparing the voltage differentiation signal with plural AQR threshold signals to generate plural AQR comparison signals, so as to generate an AQR signal to control an operation signal generator circuit to perform an adaptive quick response procedure.

A power switch includes a power device connecting a supply input to an output, and a power switch controller comprising a gate control circuit that turns the power device on and off in response to a command signal and a decision circuit that produces an OFF signal indicating when the power device is fully off. The power device may be integrated or separate from the power switch controller. The gate control circuit may accept one or more enable signals that must be active to turn on the power device, so that OFF signals and enable inputs of multiple power switches can be interconnected to facilitate break-before-make operation using minimal additional circuitry. Coordinated systems of power switches connecting one or more power supplies to one or more loads and methods of coordinating systems of power switches having OFF indication are also provided.

A Powered Single Pair Ethernet (SPE) switch (1s) comprises first and second trunk cable interfaces (P1, N1, P2, N2), at least one pair of inductors (5, 29, 7, 27) connected in series with one another between the trunk cable interfaces, an internal power supply (18) for powering the SPE switch, a switching circuit (SC) connected to the internal power supply and the trunk cable interfaces, a respective voltage and / or current measurement circuit (8, 14, 11, 22, 23, 26) for each trunk cable interface, and a decision circuit (9, 10, 16, 24, 25) configured to signal whether one of the trunk cable interfaces has been shorted based on the voltage and / or current measurement circuits. The switching circuit (SC) supplies power to the internal power supply (18) and has a first state allowing bidirectional flow of current between the first and second trunk cable interfaces, and a second state interrupting flow of current between the first and second trunk cable interfaces when the decision circuit signals a short circuit.

Faults in a periodically oscillating MEMS mass are detected by processing a position signal, having an amplitude and oscillation frequency, generated as a function of mass position. First and second reference signals formed by samples of quadrature sinusoids at the oscillation frequency are generated. First and second multipliers generate a first product signal and a second product signal, respectively, via multiplication of the position signal by the first and second reference signals. The first and second product signals are low pass filtered to generate first and second filtered signals, respectively. An estimator circuit determines estimates of the amplitude as a function of the first and second filtered signals. A decision circuit detects the presence of faults on the basis of a comparison of the estimates with a range of values.

The invention discloses a power converter with a spread spectrum control mechanism. In the power converter, a buffer circuit determines a plurality of buffer ratios respectively used in a plurality of frequency bands according to a plurality of energy upper limit values respectively in the plurality of frequency bands in a switching frequency range. In a power converter, a buffer circuit buffers a voltage signal from an inductor according to a plurality of buffer ratios, respectively, when switching frequencies of an upper bridge switch and a lower bridge switch are within a plurality of frequency bands, respectively. In the power converter, a turn-on time decision circuit decides the turn-on time of an upper bridge switch and a lower bridge switch according to a buffered output voltage signal.

A universal serial bus device includes a resistor, a decision circuit, and a control circuit. The resistor is configured to receive a power supply voltage selectively. The decision circuit is configured to determine whether to remove the resistor based on at least one state of the universal serial bus device. If the decision circuit determines to remove the resistor based on the at least one state of the universal serial bus device, the decision circuit generates a removing signal. The control circuit is configured to remove the resistor based on the removing signal.

A command address control circuit includes a command decoding circuit, an error decision circuit, and a shifting circuit. The command decoding circuit detects a type of command address signal set in synchronization with a reference clock signal. The error decision circuit detects whether an error is present in the command address signal set, and generates a block signal based on the type of command address signal set and the results of the detection of an error. The shifting circuit outputs the command address signal set as an internal command address signal set based on the reference clock signal and the block signal.