660 results about "Decision circuit" patented technology

A decision circuit (10) monitors a main current flowing in an IGBT (1), and when operation of the IGBT (1) enters an overcurrent state and the control voltage applied to the control terminal (G) of the IGBT (1) is equal to or larger than the threshold voltage, it determines that the IGBT (1) is in the overcurrent state and places the IGBT (1) in an OFF state, and also outputs the result of the determination as an output signal to an external microcomputer from an error output terminal (9). Receiving this output signal, the microcomputer immediately fixes driving signals for the IGBT (1) and another IGBTs at an OFF signal level to disconnect these IGBTs, thus preventing the main current of the IGBT (1) from increasing to a still larger overcurrent to protect the IGBT (1). Generation of a turn-off surge voltage is suppressed in the overcurrent state by detecting the overcurrent state of the power transistor by earlier timing.

Adaptive equalization methods and adaptive equalizers used with precoded systems dominated by intersymbol interference (ISI) monitor the output of a DFE and compare it to a reference for updating a precoder in response to the comparison. To accomplish this, an adaptive equalizer includes a feed forward equalizer receiving a signal from a communication channel, the feed forward equalizer equalizing variations in pre-cursor intersymbol interference resulting from changes in characteristics of the channel and providing an output signal to an error correction decoder, a decision circuit, coupled to the feed forward equalizer, for generating error vectors in response to the output signal of the feed forward equalizer and a decision feedback equalizer, coupled to the decision circuit, the decision feedback equalizer monitoring the pre-cursor intersymbol interference of the channel, determining when the transmitter coefficients to the precoder warrant updating, and generating a signal indicating that an update to the transmitter coefficients to the precoder is warranted. The adaptive equalizer farther includes a comparison circuit, the comparison circuit receiving an output from the decision feedback equalizer and comparing the output from the decision feedback equalizer to a reference, the comparison circuit generating the signal indicating that an update to the transmitter coefficients to the precoder is warranted in response to the comparison.

A continuous-time domain Decision Feedback Equalizer (DFE) for use in a serial communication channel comprises in one embodiment a summer, a decision circuit, a capture flip-flop (FF) and an N-th order active filter. The DFE and its active filter operate in continuous time to give improved performance over a discrete-time DFE. In one embodiment involving a first-order active filter, the capture FF is outside the continuous-time negative feedback loop of the DFE and involves a differential signal amplifier. In another embodiment, the capture flip-flop is inside the DFE loop, and in a third embodiment the decision circuit comprises a comparator.

A data coupler includes first and second acoustic isolation transformers that develop first and second isolated output signals in response to first and second modulated input signals. A first and a second transmitter is coupled to the first and second acoustic isolation transformers to receive a first and a second data input signal and generate the first and second modulated input signal in response to the first and second data input signals. A first and a second receiver is coupled to the first and second acoustic isolation transformers to receive the first and a second isolated output signals and generate first and second demodulated signals responsive to the first and second isolated output signals. An output decision circuit is coupled to the first and second receivers to receive the first and second data output signals and generates a data output signal responsive to the first and second demodulated signals.

A transmitter is provided for transmitting data to a communication channel and a receiver receives the data from the communication channel. The transmitter comprises an encoder to encode data and a linear block encoder to encode data encoded by the encoder. The receiver comprises a soft channel decoder to decode the data, and a soft linear block code decoder to decode data decoded by the soft channel decoder. In the first iteration, the soft channel decoder decodes data received by the receiver. In succeeding iterations, the soft channel decoder decodes the data received by the receiver and utilizes information from the soft linear block decoder from an immediate preceding iteration. A decision circuit selects an output of the soft linear block decoder if an evaluated criterion is less than a threshold, or an output of the soft channel decoder if the evaluated criterion is greater than the threshold. A decoder decodes an output of the threshold check circuit.

An adaptive LCD power supply circuit for adjusting at least one supply parameter in response to at least one load parameter of an associated load includes a feedback path configured to sense at least one load parameter and provide a control signal representative of at least one load parameter, and a regulating circuit configured to accept the control signal and regulate at least one supply parameter based on the control signal. The feedback path may include a first path to provide a first signal representative of a load condition of a first module, and a second path to provide a second signal representative of a load condition of a second load module, and a minimum decision circuit to output a third signal equal to the lesser of the first and second signals. An electronic device including an adaptive LCD power supply circuit is also provided.

When a buffer underrun decision circuit decides that a buffer underrun is about to occur, data recording on the disk is interrupted by a recording control circuit. On the other hand, when the buffer underrun decision circuit determines that a buffer underrun situation has been avoided, data recording is resumed by the recording control circuit. At this time, data recording is resumed from a position of the disk which is continuous to data recorded by the time the data recording was interrupted, thereby recording new data continuous to the last recorded data.

The battery system has a battery 1 having a plurality of series-connected battery cells 2, a voltage detection circuit 3 that detects each battery cell voltage, discharge circuits 4 to discharge each battery cell, and a decision circuit 5 that judges the condition of the connection between a battery cell 2 and the voltage detection circuit 3 from the detected battery cell voltage measured by the voltage detection circuit. The voltage detection circuit 3 measures discharge voltage of a battery cell 2 with the discharge circuit 4 in the discharging state, and measures non-discharge voltage with the battery cell 2 in a non-discharging state. The decision circuit 5 compares the difference between the detected battery cell non-discharge voltage and discharge voltage with the normal voltage, or compares battery cell discharge voltage with the normal voltage to judge abnormal connection between the battery cell and the voltage detection circuit.

The distance to a target vehicle is calculated comparatively accurately. To achieve this, a target vehicle traveling ahead of one's own vehicle is imaged by a camera and it is determined to what vehicle group, such as a light-duty vehicle group, standard passenger car group or heavy-duty vehicle group, the image of the target vehicle belongs. A first distance from one's own vehicle to the target vehicle is calculated by a circuit using the representative vehicle width of the vehicle group decided. A vanishing point is detected from the captured image by a vanishing point detection circuit and a second distance from one's own vehicle to the target vehicle is calculated utilizing the vanishing point. The distance to the target vehicle is decided from the first and second distances by a distance decision circuit, wherein the shorter the distance to the vanishing point, the more the value of a weighting coefficient of the second distance is reduced.

The present invention is directed to an electrical wiring device that includes an automatic self-test assembly coupled to the plurality of line terminals or the plurality of load terminals, the detection circuit, the fault detection circuit and the circuit interrupter assembly. The automatic self-test assembly is configured to cause the detection circuit to generate a simulated sensor fault signal during a predetermined half-cycle of an AC line cycle in accordance with a predetermined periodic testing schedule, monitor the fault detection signal corresponding to the simulated sensor fault signal, and generate a test result signal based on monitoring the fault detection signal. The automatic self-test assembly also includes a noise immunized decision circuit configured to evaluate a plurality of test results to thereby provide a noise immunized end-of-life signal. One of the conductive paths that connects the plurality of line terminals and the plurality of load terminals being interrupted in response to the noise immunized end-of-life signal.

A driving circuit includes a first light-emitting device, a first constant-current supplier, a voltage regulator circuit, an analysis and decision circuit, and a first switch. The first constant-current supplier provides a constant current to the first light-emitting device. The voltage regulator circuit provides a driving voltage to the first light-emitting device and adjusts driving voltage according to a feedback signal. The analysis and decision circuit is coupled to the voltage regulator circuit and the first light-emitting device. The analysis and decision circuit generates a first switch control signal. The first switch is coupled to the first light-emitting device, the analysis and decision circuit, and the voltage regulator circuit. The first switch is turned on and off according to the first switch control signal.

A system for detecting the presence of a near filed communication object includes a radiator configured to radiate a magnetic field from a near field communication reader device; a detector configured to detect a loading effect on the magnetic field caused by the near filed communication object; and a decision circuit configured to determine that the near field communication object is present based on the detected loading effect. Only once the presence of a nearby NFC object is detected will higher power-consuming communications take place. Accordingly a power-sensitive background polling feature can be implement within the NFC architecture.

A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data.

An involatile memory which carries out, in a flash memory itself, verify check of the flash memory for respective bit lines, and produces an overall verify check result from a completion decision circuit to a tester. This makes it possible to solve a problem of a conventional flash memory in that the time taken by the verify check depends on the bus width of an external data bus, because it carries out the verify check by reading data from the flash memory through the external bus. Thus, the time taken by the verify check can be reduced.

A process is proposed for recovering disturbed digital signals, wherein the electrical signals pass through a feedback equalizer and an analogue control of the setting parameters of the equalizers is performed. A pseudo-error monitor, which facilitates a high-speed adjustment of decision element thresholds, is also provided.

A grid-connected inverter includes first and second power conversion circuits, a contactor and a control circuit. The first conversion circuit converts a first DC voltage to a second DC voltage. The second conversion circuit converts the second DC voltage to an AC voltage. The contactor connects an output side of the second conversion circuit to a power system. The control circuit includes a decision circuit and controls start and stop operations of the conversion circuits, and opening and closing of the contactor. The decision circuit decides whether a condition of the contactor is abnormal by detecting, after the control circuit controls the contactor to be open, whether or not a value of the second DC voltage is less than a threshold value, and if the value of the second DC voltage is detected to be not less than the threshold value, decides that the condition of the contactor is abnormal.

A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was received first. In response, the phase decision circuit generates respective logic signals to reflect the phase relationship determination. The circuit also includes a latch circuit that receives the logic signals from the phase decision circuit and holds the phase relationship determination of the circuit a predetermined time after a predetermined transition of both clock signals have occurred. Methods and systems are also disclosed.

The present invention is related to a device for USB interface identification, wherein a universal serial bus (USB) connection interface is installed on one side of computer exterior as a connection for external electronic apparatus, and more specifically, the present invention installs a decision circuit connecting to a display device between the USB connection interface and the electronic apparatus. Thus, messages illustrated on the display device are employed by user to determine whether the transmission speed between the computer and the electronic apparatus is in the low speed, full speed, or hi-speed.

A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and which improves testability of the semiconductor storage device. A plural number of holding circuits (103) are provided holding write data for memory cells of a memory cell array (101-1). The write data from the holding circuits (103) are written in the memory cells of the selected address. A plural number of comparators (CCMPN) are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted value or the inverted value of the write data held by the holding circuits (103) is output as the write data to the memory cells and as expectation data to the comparators (CCMPN) depending on the value of the inversion control signal (DIM). A decision circuit (104) is provided which outputs an error flag based on a coincidence detection signal (MATCH0) coupled to the plural comparators.

A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.