59 results about "Decision circuit" patented technology

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

The utility model discloses a circuit for improving the safety of a bridge circuit for magnetic bearing suspension current. The circuit comprises an intercommunication detection module and a driving control module, the intercommunication detection module comprises a first logic circuit, a second logic circuit and a hybrid decision circuit; the first logic circuit comprises a first OR gate and two first NOT gates, in two paths of enable signals of the double-path magnetic suspension bearing, the negative current of the first enable signal and the positive current of the second enable signal are respectively input into the input ends of the two first NOT gates, and the output ends of the two first NOT gates are correspondingly connected with the two input ends of the first OR gate; the second logic circuit comprises a second OR gate and two second NOT gates, the positive current of the first enable signal and the negative current of the second enable signal are respectively input into the input ends of the two second NOT gates, and the output ends of the two second NOT gates are correspondingly connected with the two input ends of the second OR gate; according to the utility model, intercommunication of two MOS transistors on the same bridge arm can be avoided, the structure is simple and reliable, the cost is low, and the circuit is suitable for large-scale mass production.

An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.

The application discloses a dual-mode event trigger circuit based on light detection and optical synapse, comprising a detection module and a detection module; the detection module is used for triggering based on light events or voltage events, converting received optical signals or electrical signals into current signals, and transmitting the current signals to the detection module; the detection module is used for collecting current signals and performing corresponding event detection; wherein the detection module is configured with an optoelectronic device integrating light detection and optical synapse functions, when the optoelectronic device is subjected to light and no external voltage is applied, the optoelectronic device behaves as a light detection mode, at the same time, the detection module works in a light event detection mode; when the optoelectronic device is simultaneously subjected to an external voltage and light, the optoelectronic device behaves as an optical synapse mode, at the same time, the detection module works in a voltage event detection mode. The circuit realizes dual-mode event triggering by using simple devices, has compact circuit structure, high device integration, does not need a complex multi-stage decision circuit, and effectively reduces energy consumption.

A sequence detection device includes a feed-forward filter, a feedback filter, a combining circuit, a decision circuit, and a sequence detection circuit. The feed-forward filter processes a received signal to generate a first equalized signal. The feedback filter processes a symbol decision signal to generate a second equalized signal. The combining circuit combines the first and second equalized signals to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the first equalized signal, and includes a region estimation circuit and a trellis selection circuit. The region estimation circuit is independent of the decision circuit, and categorizes each sample of the sample signal into one region. The trellis selection circuit selects one trellis scheme for branch metric calculation according to region estimation results output from the region estimation circuit.

A cardiac treatment device, including:stimulation circuitry configured to generate a non-excitatory electrical signal which, when applied to ventricular tissue during a ventricular refractory period thereof improves a condition of heart failure in human patients;atrial arrhythmia detection circuitry; anddecision circuitry which controls the stimulation circuitry to delivery said signal, also when said atrial arrhythmia detection circuitry detects an atrial arrhythmia.

A pattern inspection device according to one embodiment of the present invention is characterized by being provided with: an optical image acquisition means for acquiring an optical image of a sample to be inspected on which a pattern is formed; a parameter range setting circuit that sets a range of reference image generation parameters on the basis of the degree of coincidence with past inspection condition parameters; a filter function generation circuit that generates a plurality of filter function candidates using values within the set range of the reference image generation parameters; a determination circuit that determines a filter function for creating a reference image from among the generated candidates of the plurality of filter functions; a reference image creation circuit that creates a reference image using the determined filter function; and a comparison circuit that compares the optical image with the reference image.

A power switch includes a power device connecting a supply input to an output, and a power switch controller comprising a gate control circuit that turns the power device on and off in response to a command signal and a decision circuit that produces an OFF signal indicating when the power device is fully off. The power device may be integrated or separate from the power switch controller. The gate control circuit may accept one or more enable signals that must be active to turn on the power device, so that OFF signals and enable inputs of multiple power switches can be interconnected to facilitate break-before-make operation using minimal additional circuitry. Coordinated systems of power switches connecting one or more power supplies to one or more loads and methods of coordinating systems of power switches having OFF indication are also provided.

The invention discloses a digital baseband communication receiving link circuit and a data receiving method, and relates to the technical field of data communication, the circuit comprises a downsampling module, a code element shaping module, a code element synchronization module, a decoding module and a CRC verification module; the down-sampling module comprises a CIC down-sampling circuit and a half-band filter down-sampling circuit; the code element shaping module comprises a delay circuit, a level comparison circuit and a level overturning circuit; the code element synchronization module comprises an interpolator circuit, an error detection circuit, a loop filter, a numerical control oscillator and a sampling decision circuit; the decoding module comprises a decoding state machine circuit and a data judgment circuit; and the CRC verification module comprises a CRC mode control circuit, a CRC (Cyclic Redundancy Check)-5 verification circuit and a CRC-16 verification circuit. According to the invention, the inter-symbol interference and the bit error rate caused by the synchronization error are reduced, so that the accuracy and the signal-to-noise ratio tolerance of the received data are improved on the whole.

The embodiment of the invention provides an inversion suppression circuit and an operational amplifier. The inversion suppression circuit comprises an inversion decision circuit which is connected with the operational amplifier input stage and is used for comparing an operational amplifier input signal with the ground and outputting a first control signal and a second control signal; when the positive phase input signal of the operational amplifier is smaller than the ground, the first control signal is a first logic level, and the second control signal is a second logic level. When the negative phase input signal of the operational amplifier is smaller than the ground, the second control signal is the first logic level and the first control signal is the second logic level. According to the invention, the phase inversion suppression effect is improved.

A falling-edge modulation signal receiver is configured to process an input signal having a duty cycle varying with a bit value of the input signal. The receiver includes: a phase-locked loop for generating an oversampling clock according to the input signal which correlates with a signal clock, wherein the oversampling frequency is not lower than five times the frequency of the signal clock; an oversampling circuit for sampling the input signal according to the oversampling clock and thereby generating multiple groups of data which as a whole is corresponding to a single bit of the input signal; and a decision circuit for ascertaining that X bits of the multiple groups of data are 1 and determining the value of the single bit according to the X. When the X is greater / less than a threshold, the decision circuit determines that the value of the single bit is 1 / 0.

An interpolation type time-to-digital converter based on pre-judgment partial activation comprises a reference voltage generating circuit, a parallel converter array, a parallel pre-judgment circuit array, an interpolation TDC, a one-hot code encoder and a binary encoder which are connected in sequence, and a pre-judgment auxiliary converter which is connected with the parallel converter array and the parallel pre-judgment circuit array respectively, dynamic partial activation is achieved through a pre-judgment mechanism, and the method is suitable for any VTC structure and has wider applicability and lower dynamic power consumption. Meanwhile, the decoding logic structure is simple, extra delay is not introduced, and the method is suitable for a high-speed low-power-consumption time domain ADC system.

This invention relates to a thin-film leakage current testing system, comprising a test voltage source that applies current to the thin film under test; a multi-stage current measurement unit, with its input connected to the thin film under test and its output connected to a window comparator; a window comparator used to define the linear output region of each stage unit and generate a flag signal; a pure hardware decision and gating circuit, composed of high-speed logic gates, which makes decisions according to the flag signal and preset priority to achieve seamless range switching and output gating; and a data output interface that transmits the collected leakage current and voltage data to an external device in a preset format. This invention integrates a multi-stage current measurement unit, a window comparator, and a pure hardware decision circuit, eliminating the need for combining multiple instruments and complex synchronous calibration. Users only need to connect the thin film and apply voltage; the system can automatically complete seamless measurements across the entire range, from weak leakage current to large breakdown current, significantly reducing setup barriers and operational complexity, and improving testing efficiency and result consistency.

The present application relates to a comparison circuit with adaptive comparison mechanism and its operation method. A comparison circuit with adaptive comparison mechanism. The comparator is enabled by an enable signal in an enabled state in a comparison phase, and compares a first voltage and a second voltage to generate a comparison result. A comparison judgment circuit respectively sets a phase indication signal in an incomplete comparison phase state and a completed comparison phase state before and after the comparison result is generated. A time accumulation circuit starts accumulating an accumulated time when the enable signal is in the enabled state, and stops accumulating when the phase indication signal is in the completed comparison phase state to generate a comparison time. A decision circuit counts the comparison time in the comparison phase to generate a preset threshold time, and further directly sets a preset comparison result as the comparison result when the accumulated time exceeds the preset threshold time and the comparison result has not been generated in the comparison phase.

The utility model relates to the field of RFID technology, specifically is a kind of high-frequency label FSK signal demodulation circuit that can realize high-frequency RFID label long-distance reading, it is characterized by being equipped with envelope detection circuit, active band-pass filter amplification circuit, phase shift circuit, analog multiplier circuit, low-pass filter amplification circuit and comparison decision circuit, wherein, envelope detection circuit receives data from antenna and data is sent into active band-pass filter amplification circuit, and one way output of active band-pass filter amplification circuit will received data send into analog multiplier circuit, and another way of active band-pass filter amplification circuit will received data send into phase shift circuit.

The invention discloses a negative power supply working level decision circuit, and relates to the technical field of electronic circuits. The level decision circuit for working of the negative power supply receives an enable signal through a signal receiving module and outputs a corresponding output logic level through a logic processing module according to the voltage of the enable signal, and the high level of the output logic level is zero potential; and the low level of the output logic level is negative potential. By implementing the level decision circuit for working of the negative power supply recorded by the embodiment of the invention, when the internal working voltage of the enable pin is negative voltage, the on and off of the circuit can be controlled under the two voltage conditions that the enable pin applies positive voltage and negative voltage at the same time.

A display device is disclosed that includes a display panel having pixels configured to display images during a first frame, a second frame, and a third frame, each of the first frame, the second frame, and the third frame including an active period and a blanking period; a counting circuit configured to count a duration of the blanking period of the first frame after the active period of the first frame; a comparison circuit configured to compare the counted duration of the blanking period of the first frame with a threshold time required for sensing at least one pixel or a threshold time required to prepare for driving the pixels during the second frame; and a delay decision circuit configured to determine whether to increase a duration of the blanking period of the first frame based on the comparison.

The invention belongs to the field of integrated circuits, and particularly relates to an ADC based on an RRAM delay chain and a neural network encoder. The method comprises the following steps: firstly, respectively processing an input signal by using a delay unit module and an RRAM (Resistance Random Access Memory) delay unit module to generate two types of delay signals; a D trigger is used as a decision circuit, and when the rising edge of the delay signal from the delay unit arrives, the D trigger captures the level of the delay signal from the RRAM delay unit module; when the delay signal of the RRAM module arrives at the D trigger earlier, the D trigger outputs a high level, otherwise, when the delay signal of the RRAM module arrives at the D trigger later, the D trigger outputs a low level; the relative delay length relation of two analog paths is ingeniously converted into a digital voltage judgment signal, and quantization from input voltage to initial digital output is completed. And intelligent correction of a neural network can be further combined, so that the quantization speed and precision of the input voltage are improved again, and the overall performance of the ADC circuit is improved.

The application discloses a native creativity realization method, system and circuit of an electronic system, and belongs to the technical field of hardware management and control chips. The method comprises the following steps: when a behavior intention is generated but there is no directly-matched execution scheme, a hardware logic circuit which is independent of instruction execution automatically retrieves a relevant experience entry from an experience set in the same physical chip package and recombines the experience entry to generate a brand-new candidate behavior scheme; the candidate scheme must be verified by an independent decision circuit which is physically separated from a behavior generation path before execution; the scheme which fails to pass the verification is permanently prohibited from output under standard working conditions; and the new scheme which passes the verification and is successfully executed is automatically added to the experience set. The application realizes the cross-scene recombination of experiences and the safe generation of brand-new behavior schemes by means of hardware, and is suitable for electronic systems such as intelligent robots, embodied intelligence and deep space exploration which need to cope with unknown scenes offline and autonomously.

The present application provides a loop filter for an encoder, which comprises a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is used to process a plurality of frames, wherein for a first frame of the plurality of frames, the constrained directional enhancement filter determines the best filter strength for each block in the first frame from a first filter strength list, and determines a second filter strength list according to the content of the first frame. The decision circuit is used to record which index number in the first filter strength list the best filter strength corresponding to each block in the first frame is, and provides the first filter strength list and the index number corresponding to each block to an encoding circuit of the encoder as the output of the encoder.

Methods, systems, and devices for command and address (CA) sampling are described. A memory system may implement a sampler that performs a first comparison of a CA sample with a first reference voltage and a second comparison of a CA sample with a second reference voltage. Such comparisons may be performed at the memory system using a first decision circuit and a second decision circuit. The memory system may determine to activate one of the first decision circuit or the second decision circuit based on a value of a previous CA sample. After activating the respective decision circuit, an output of the decision circuit may be input to a latch circuit, and the latch may determine a logical value of the CA sample. The latch circuit may send the output of the latch circuit as feedback to the first decision circuit and the second decision circuit.

The utility model relates to the technical field of electric power monitoring and power supply management, and discloses a low-power-consumption power supply state monitoring terminal which comprises a shell and an internal circuit board, and the circuit board is powered by a system main power supply and comprises an integrated sampling circuit, a reference voltage generating circuit, a three-level gradient power supply control framework and a power-off control circuit. In the three-stage gradient power supply control architecture, only a micro-power-consumption first comparator works continuously, other modules are powered on as required, sampling signals are validated through double comparators and an RC delay decision circuit, instantaneous interference of mains supply is filtered out, a power-off control circuit realizes active power-off and forced power-off dual modes, and the power-off control circuit is switched on and off. According to the utility model, through a three-stage gradient power supply control architecture, the standby power consumption of the system can be reduced to a microampere level, the requirement of high anti-interference performance is satisfied, and the system is suitable for long-term monitoring scenes without fixed power supply.

This application relates to a phase detector circuit, a phase detector chip, and a clock data recovery circuit. Under a preset level of the second sampling clock signal, a logic decision circuit directly generates a decision result based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal, instead of generating two intermediate signals first and then merging them. Subsequently, the second synchronization circuit latches the output after being synchronized by the second sampling clock signal. This scheme, because the entire decision process has only one combinational logic path, eliminates the problem of delay matching between the two signals, thus completely eliminating output transient fluctuations caused by inconsistent path delays. Simultaneously, the output is updated only at the edge of the second sampling clock signal, maintaining a constant output and avoiding additional phase differences introduced by delay mismatch, significantly improving the alignment accuracy of the clock and data. Furthermore, the phase detector circuit structure of this application is simpler than traditional structures, resulting in relatively smaller power consumption and area.

This application relates to time-varying decision feedback equalization. A memory device may be coupled to a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device via the conductive lines. The receiver may include decision circuitry for determining the voltage of the received signal based on the received signal and a feedback signal, and outputting an output signal. The receiver may include a variable time delay circuit configured to output a delayed version of the output signal, and a gain circuit configured to scale the delayed signal to generate the feedback signal. The variable time delay circuit may include a delay element with a variable delay parameter. The receiver may be coupled to a memory array storing information delivered by the output signal.

The invention discloses a triple redundancy safety instrument system and a voting and degradation control method of the system, relates to the technical field of safety control, and mainly aims to solve the problem that an existing safety instrument system is poor in safety protection flexibility and scene adaptability. The system mainly comprises three levels of an input module, a controller and an output module, each level comprises parallel channels with the same function, the input module comprises input channels with triple redundancy, the controller comprises controller channels with triple redundancy, and the output module comprises a hardware decision circuit based on a multi-switch circuit and output channels with triple redundancy. Five levels of voting are completed in the system and specifically comprise the first level of voting of an input module, the second level of voting and the third level of voting of a controller, the fourth level of voting of an output module and final driving of a hardware decision circuit, the voting of any level is executed according to a voting mode, and the voting mode is determined based on a degradation strategy of 3-3-2-2-1-0. The method is mainly used for safety control.

A control circuit controls a multiphase power converter which includes plural power stage circuits, so as to convert an input power to an output power. The control circuit includes: a current sensing circuit, for sensing an output current for generating a current sensing signal; a transient detection circuit, for generating a transient indication signal by an output voltage; and a phase decision circuit, for generating a phase decision signal by a processed sensing signal and the transient indication signal, for determining an activated phase number. The phase decision circuit includes: a low-pass filter, for generating a low-pass-filtered signal by low-pass filtering the current sensing signal; and a multiplexer, for adaptively selecting the current sensing signal or the low-pass-filtered signal to be the processed sensing signal according to the transient indication signal.

A cardiac therapy device includes a stimulation circuit configured to generate a non-excitatory electrical signal that improves a condition of heart failure in a human patient when the non-excitatory electrical signal is applied to ventricular tissue during a ventricular refractory period of the ventricular tissue; an atrial arrhythmia detection circuit; and a decision circuit that controls the stimulation circuit to deliver the signal when the atrial arrhythmia detection circuit detects an atrial arrhythmia.

An active matrix display comprising: a power supply V DD ; an array of pixels comprising columns and rows, each pixel for emitting light having a separately controlled segmented electrode and an opposing electrode; a drive circuit comprising at least one data line providing a data signal for each pixel along a column and at least one scan line providing a scan signal for each pixel along a row, wherein the data signal controls a gate of a drive transistor, a source and a drain of the drive transistor being connected between the power supply V DD and the segmented electrode, the scan signal controls a gate of a scan transistor to load the data signal from the data line to the gate of the drive transistor; and a pixel control circuit in electrical contact with the segmented electrode, wherein the pixel control circuit prevents light emission of the pixel based on a value of the data signal of the pixel. The pixel control circuit comprises a decision circuit outputting a signal controlling a branch transistor, thereby preventing emission whenever the data signal indicates that the pixel should not emit. Crosstalk effects are reduced, in particular in OLED microdisplays.

The invention provides a sequence detection device and a sequence detection method. The sequence detection device comprises a feed-forward filter, a feedback filter, a combining circuit, a decision circuit and a sequence detection circuit. The feed-forward filter processes a received signal to generate a first equalized signal. The feedback filter processes the symbol decision signal to generate a second equalized signal. The combining circuit combines the first and second equalized signals to generate a sample signal. The decision circuit performs a hard decision on the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection on the first equalization signal and comprises a region estimation circuit and a grid selection circuit. The region estimation circuit classifies each sample in the sample signal into a region. The grid selection circuit selects a grid scheme for branch metric calculation according to the area estimation result output by the area estimation circuit.