89 results about "Decision circuit" patented technology

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

A driver circuit that displays received display data on a display panel is provided. The driver circuit includes: a first register circuit, holding display control data used for controlling display of the display data on a display panel and outputting the display control data at a predetermined timing; multiple second register circuits, holding decision data with predetermined logic; a decision circuit, outputting a decision result indicating no abnormality has occurred in response to a logic of decision data held in second register circuits being a predetermined logic, respectively, and display control data held in the first register circuit being active; and a mask control circuit, controlling so that display control data held in the first register circuit is output to a circuit that performs display control of the display panel in response to a decision result output from the decision circuit indicating that no abnormality has occurred.

A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

A control circuit controls a multiphase power converter which includes plural power stage circuits, so as to convert an input power to an output power. The control circuit includes: a current sensing circuit, for sensing an output current for generating a current sensing signal; a transient detection circuit, for generating a transient indication signal by an output voltage; and a phase decision circuit, for generating a phase decision signal by a processed sensing signal and the transient indication signal, for determining an activated phase number. The phase decision circuit includes: a low-pass filter, for generating a low-pass-filtered signal by low-pass: filtering the current sensing signal; and a multiplexer, for adaptively selecting the current sensing signal or the low-pass-filtered signal to be the processed sensing signal according to the transient indication signal.

Apparatuses and techniques for local-bank-level scheduling enhancement of usage-based-disturbance mitigation based on global-bank-level control are described. To enable efficient utilization of timing resources, a memory device includes a refresh control circuit implemented at a global-bank level of the memory die and a mitigation decision circuit implemented at a local-bank level of the memory die. The refresh control circuit determines currently available timing resources for mitigating usage-based disturbance and generates a control signal to pass this information to the mitigation decision circuit. The mitigation decision circuit schedules the mitigation actions to efficiently utilize the currently available timing resources and ensure that different conditions associated with usage-based-disturbance are mitigated in order of priority. In this manner, available timing resources are efficiently utilized to decrease a risk of the memory device being subjected to usage-based disturbance. Furthermore, these techniques can be performed without significantly increasing cost or die size.

An external chip driving system includes a decision circuit, multiple first adjustable enhancement circuits, multiple second adjustable enhancement circuits, a pull-up circuit, and a pull-down circuit. The decision circuit outputs first and second decision signals based on a frequency signal and an input signal. In response to the first and second decision signals and one of the first selection signals, each of the first adjustable enhancement circuits generates a first control signal. In response to the first and second decision signals and one of the second selection signals, each of the second adjustable enhancement circuits generates a second control signal. Because the signal amplitude attenuates and becomes distorted during high-speed data transmission, in this disclosure, the first driver in the pull-up circuit is activated in response to the corresponding first control signal, and the second driver in the pull-down circuit is activated in response to the corresponding second control signal, thereby increasing the slew rate of the output signal and reducing the distortion of the output data.

The utility model discloses a circuit for improving the safety of a bridge circuit for magnetic bearing suspension current. The circuit comprises an intercommunication detection module and a driving control module, the intercommunication detection module comprises a first logic circuit, a second logic circuit and a hybrid decision circuit; the first logic circuit comprises a first OR gate and two first NOT gates, in two paths of enable signals of the double-path magnetic suspension bearing, the negative current of the first enable signal and the positive current of the second enable signal are respectively input into the input ends of the two first NOT gates, and the output ends of the two first NOT gates are correspondingly connected with the two input ends of the first OR gate; the second logic circuit comprises a second OR gate and two second NOT gates, the positive current of the first enable signal and the negative current of the second enable signal are respectively input into the input ends of the two second NOT gates, and the output ends of the two second NOT gates are correspondingly connected with the two input ends of the second OR gate; according to the utility model, intercommunication of two MOS transistors on the same bridge arm can be avoided, the structure is simple and reliable, the cost is low, and the circuit is suitable for large-scale mass production.

An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.

The application discloses a dual-mode event trigger circuit based on light detection and optical synapse, comprising a detection module and a detection module; the detection module is used for triggering based on light events or voltage events, converting received optical signals or electrical signals into current signals, and transmitting the current signals to the detection module; the detection module is used for collecting current signals and performing corresponding event detection; wherein the detection module is configured with an optoelectronic device integrating light detection and optical synapse functions, when the optoelectronic device is subjected to light and no external voltage is applied, the optoelectronic device behaves as a light detection mode, at the same time, the detection module works in a light event detection mode; when the optoelectronic device is simultaneously subjected to an external voltage and light, the optoelectronic device behaves as an optical synapse mode, at the same time, the detection module works in a voltage event detection mode. The circuit realizes dual-mode event triggering by using simple devices, has compact circuit structure, high device integration, does not need a complex multi-stage decision circuit, and effectively reduces energy consumption.

A sequence detection device includes a feed-forward filter, a feedback filter, a combining circuit, a decision circuit, and a sequence detection circuit. The feed-forward filter processes a received signal to generate a first equalized signal. The feedback filter processes a symbol decision signal to generate a second equalized signal. The combining circuit combines the first and second equalized signals to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the first equalized signal, and includes a region estimation circuit and a trellis selection circuit. The region estimation circuit is independent of the decision circuit, and categorizes each sample of the sample signal into one region. The trellis selection circuit selects one trellis scheme for branch metric calculation according to region estimation results output from the region estimation circuit.

The present invention relates to a floating omnidirectional maneuverable platform, method and application for surface clusters, belonging to the field of cluster intelligence technology; it includes a floating shell, a perception and decision module, a drive execution module and a power supply module. Through the cooperation of each module and in combination with a power distribution method, an omnidirectional maneuverable platform that can be used to verify the self-organizing motion algorithm of clusters in open water environments is obtained. The present invention integrates perception, decision-making and execution into one, and through the combined use of a 360° angle controllable servo and a camera module, it has the ability to actively perceive environmental information at 360°; the perception and decision circuit board has a built-in cluster self-organizing motion control algorithm, and the drive execution circuit board has a built-in thrust distribution algorithm. Combined with three propeller thrusters distributed at 120° intervals, it has the ability to move omnidirectionally on the water surface. It has the advantages of stable operation, strong flexibility and easy development, good engineering application value, and helps to improve the portability of cluster algorithms to machine clusters.

A cardiac treatment device, including:stimulation circuitry configured to generate a non-excitatory electrical signal which, when applied to ventricular tissue during a ventricular refractory period thereof improves a condition of heart failure in human patients;atrial arrhythmia detection circuitry; anddecision circuitry which controls the stimulation circuitry to delivery said signal, also when said atrial arrhythmia detection circuitry detects an atrial arrhythmia.

An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.

A pattern inspection device according to one embodiment of the present invention is characterized by being provided with: an optical image acquisition means for acquiring an optical image of a sample to be inspected on which a pattern is formed; a parameter range setting circuit that sets a range of reference image generation parameters on the basis of the degree of coincidence with past inspection condition parameters; a filter function generation circuit that generates a plurality of filter function candidates using values within the set range of the reference image generation parameters; a determination circuit that determines a filter function for creating a reference image from among the generated candidates of the plurality of filter functions; a reference image creation circuit that creates a reference image using the determined filter function; and a comparison circuit that compares the optical image with the reference image.

The present invention discloses an anti-misfire protection module for preventing the safety and control device of a carrier rocket from misfire, comprising: an A / D sampling circuit for collecting and measuring the voltage of the detonation preparation output terminal and the detonation output terminal of the safety and control device. A protection logic circuit electrically connected to the A / D sampling circuit and the safety and control logic module of the safety and control device, respectively, for receiving signals from the A / D sampling circuit and the safety and control logic module and performing protection operations, and outputting a detonation circuit breaker control signal when it is determined that there is a hidden danger of misfire. A protection decision circuit for receiving the detonation circuit breaker control signal and driving the protection switch array to disconnect. A protection switch array electrically connected to the detonation output terminal and the detonator of the safety and control device, respectively, is controlled by the protection decision circuit to cut off the detonation output terminal and the detonator to prevent the safety and control device from misfire. It has excellent integration and can effectively improve the safety and reliability of the safety and control device by controlling the on and off of the detonation path.

A switching regulator includes: a phase number signal generator circuit which includes: a current sensing signal differentiator circuit for performing differentiation on a current sensing signal to generate a current differentiation signal; a current sense signal filter circuit for filtering the current sense signal to generate a filtered current signal according to the current differentiation signal; and a phase number decision circuit for deciding a phase number signal according to the filtered current signal; and an AQR signal generator circuit which includes: a voltage sensing signal differentiator circuit for performing differentiation on a voltage sensing signal to generate a voltage differentiation signal; and plural comparator circuits for comparing the voltage differentiation signal with plural AQR threshold signals to generate plural AQR comparison signals, so as to generate an AQR signal to control an operation signal generator circuit to perform an adaptive quick response procedure.

A power switch includes a power device connecting a supply input to an output, and a power switch controller comprising a gate control circuit that turns the power device on and off in response to a command signal and a decision circuit that produces an OFF signal indicating when the power device is fully off. The power device may be integrated or separate from the power switch controller. The gate control circuit may accept one or more enable signals that must be active to turn on the power device, so that OFF signals and enable inputs of multiple power switches can be interconnected to facilitate break-before-make operation using minimal additional circuitry. Coordinated systems of power switches connecting one or more power supplies to one or more loads and methods of coordinating systems of power switches having OFF indication are also provided.

A universal serial bus device includes a resistor, a decision circuit, and a control circuit. The resistor is configured to receive a power supply voltage selectively. The decision circuit is configured to determine whether to remove the resistor based on at least one state of the universal serial bus device. If the decision circuit determines to remove the resistor based on the at least one state of the universal serial bus device, the decision circuit generates a removing signal. The control circuit is configured to remove the resistor based on the removing signal.

The present invention discloses a multi-bit read decision circuit, a memory, and a multi-bit binary data reading method. The multi-bit read decision circuit includes: a multiplexing module for performing gating control on a memory column; a voltage clamping module electrically connected to the multiplexing module, the voltage clamping module for reading a first current signal from a memory array, converting the first current signal into a first converted voltage signal for output; a multi-bit parallel comparison module electrically connected to the voltage clamping module, the multi-bit parallel comparison module for receiving the first converted voltage signal and converting the first converted voltage signal into multiple copied current signals according to a specific copy ratio relationship, comparing the multiple copied current signals with multiple reference current signals, and outputting a comparison result; and a biasing module electrically connected to both the voltage clamping module and the multi-bit parallel comparison module, the biasing module for providing the first clamping voltage signal to the voltage clamping module. The present invention avoids the generation of complex reference currents.

The application discloses an inductive coupling power transmission adaptive control system and method for a wireless three-dimensional stacked chip package. The system comprises a daughter chip and a mother chip connected through inductive coupling. The power transmission adaptive control system of the application converts the load feedback voltage received by the daughter chip into a feedback voltage data code word through a level decision circuit. The system can load the feedback voltage data code word onto the data link of the system and feed back to the mother chip. The mother chip of the application comprises a DPID control circuit composed of an error calculation unit and a DPID controller. The energy control code word output by the DPID control circuit controls the VCO and the frequency divider to adjust the frequency of the input clock in the energy transmission system, so as to achieve adaptive control of the transmission power of the sending chip, improve the transmission efficiency of the system, shorten the response time of the system and prevent the waste of the transmission power.

The invention discloses a digital baseband communication receiving link circuit and a data receiving method, and relates to the technical field of data communication, the circuit comprises a downsampling module, a code element shaping module, a code element synchronization module, a decoding module and a CRC verification module; the down-sampling module comprises a CIC down-sampling circuit and a half-band filter down-sampling circuit; the code element shaping module comprises a delay circuit, a level comparison circuit and a level overturning circuit; the code element synchronization module comprises an interpolator circuit, an error detection circuit, a loop filter, a numerical control oscillator and a sampling decision circuit; the decoding module comprises a decoding state machine circuit and a data judgment circuit; and the CRC verification module comprises a CRC mode control circuit, a CRC (Cyclic Redundancy Check)-5 verification circuit and a CRC-16 verification circuit. According to the invention, the inter-symbol interference and the bit error rate caused by the synchronization error are reduced, so that the accuracy and the signal-to-noise ratio tolerance of the received data are improved on the whole.

The present application provides a kind of error detection and correction device, including decision feedback equalizer (DFE), decision circuit, error detection circuit and error correction circuit.DFE equalizes data signal to generate first equalization signal.Decision circuit performs hard decision to first equalization signal to generate symbol decision signal.Error detection circuit performs forward error detection at the symbol position of the continuous symbol included in symbol decision signal to detect the first position of suspected error affecting at least one symbol in symbol decision signal.Error correction circuit performs error correction to symbol decision signal in response to the first position of suspected error detected by error detection circuit.Accordingly, the present application also provides a kind of error detection and correction method.

The embodiment of the invention provides an inversion suppression circuit and an operational amplifier. The inversion suppression circuit comprises an inversion decision circuit which is connected with the operational amplifier input stage and is used for comparing an operational amplifier input signal with the ground and outputting a first control signal and a second control signal; when the positive phase input signal of the operational amplifier is smaller than the ground, the first control signal is a first logic level, and the second control signal is a second logic level. When the negative phase input signal of the operational amplifier is smaller than the ground, the second control signal is the first logic level and the first control signal is the second logic level. According to the invention, the phase inversion suppression effect is improved.

A falling-edge modulation signal receiver is configured to process an input signal having a duty cycle varying with a bit value of the input signal. The receiver includes: a phase-locked loop for generating an oversampling clock according to the input signal which correlates with a signal clock, wherein the oversampling frequency is not lower than five times the frequency of the signal clock; an oversampling circuit for sampling the input signal according to the oversampling clock and thereby generating multiple groups of data which as a whole is corresponding to a single bit of the input signal; and a decision circuit for ascertaining that X bits of the multiple groups of data are 1 and determining the value of the single bit according to the X. When the X is greater / less than a threshold, the decision circuit determines that the value of the single bit is 1 / 0.

An interpolation type time-to-digital converter based on pre-judgment partial activation comprises a reference voltage generating circuit, a parallel converter array, a parallel pre-judgment circuit array, an interpolation TDC, a one-hot code encoder and a binary encoder which are connected in sequence, and a pre-judgment auxiliary converter which is connected with the parallel converter array and the parallel pre-judgment circuit array respectively, dynamic partial activation is achieved through a pre-judgment mechanism, and the method is suitable for any VTC structure and has wider applicability and lower dynamic power consumption. Meanwhile, the decoding logic structure is simple, extra delay is not introduced, and the method is suitable for a high-speed low-power-consumption time domain ADC system.

This invention relates to a thin-film leakage current testing system, comprising a test voltage source that applies current to the thin film under test; a multi-stage current measurement unit, with its input connected to the thin film under test and its output connected to a window comparator; a window comparator used to define the linear output region of each stage unit and generate a flag signal; a pure hardware decision and gating circuit, composed of high-speed logic gates, which makes decisions according to the flag signal and preset priority to achieve seamless range switching and output gating; and a data output interface that transmits the collected leakage current and voltage data to an external device in a preset format. This invention integrates a multi-stage current measurement unit, a window comparator, and a pure hardware decision circuit, eliminating the need for combining multiple instruments and complex synchronous calibration. Users only need to connect the thin film and apply voltage; the system can automatically complete seamless measurements across the entire range, from weak leakage current to large breakdown current, significantly reducing setup barriers and operational complexity, and improving testing efficiency and result consistency.

The present application relates to a comparison circuit with adaptive comparison mechanism and its operation method. A comparison circuit with adaptive comparison mechanism. The comparator is enabled by an enable signal in an enabled state in a comparison phase, and compares a first voltage and a second voltage to generate a comparison result. A comparison judgment circuit respectively sets a phase indication signal in an incomplete comparison phase state and a completed comparison phase state before and after the comparison result is generated. A time accumulation circuit starts accumulating an accumulated time when the enable signal is in the enabled state, and stops accumulating when the phase indication signal is in the completed comparison phase state to generate a comparison time. A decision circuit counts the comparison time in the comparison phase to generate a preset threshold time, and further directly sets a preset comparison result as the comparison result when the accumulated time exceeds the preset threshold time and the comparison result has not been generated in the comparison phase.

The utility model relates to the field of RFID technology, specifically is a kind of high-frequency label FSK signal demodulation circuit that can realize high-frequency RFID label long-distance reading, it is characterized by being equipped with envelope detection circuit, active band-pass filter amplification circuit, phase shift circuit, analog multiplier circuit, low-pass filter amplification circuit and comparison decision circuit, wherein, envelope detection circuit receives data from antenna and data is sent into active band-pass filter amplification circuit, and one way output of active band-pass filter amplification circuit will received data send into analog multiplier circuit, and another way of active band-pass filter amplification circuit will received data send into phase shift circuit.

The invention discloses a negative power supply working level decision circuit, and relates to the technical field of electronic circuits. The level decision circuit for working of the negative power supply receives an enable signal through a signal receiving module and outputs a corresponding output logic level through a logic processing module according to the voltage of the enable signal, and the high level of the output logic level is zero potential; and the low level of the output logic level is negative potential. By implementing the level decision circuit for working of the negative power supply recorded by the embodiment of the invention, when the internal working voltage of the enable pin is negative voltage, the on and off of the circuit can be controlled under the two voltage conditions that the enable pin applies positive voltage and negative voltage at the same time.

A display device is disclosed that includes a display panel having pixels configured to display images during a first frame, a second frame, and a third frame, each of the first frame, the second frame, and the third frame including an active period and a blanking period; a counting circuit configured to count a duration of the blanking period of the first frame after the active period of the first frame; a comparison circuit configured to compare the counted duration of the blanking period of the first frame with a threshold time required for sensing at least one pixel or a threshold time required to prepare for driving the pixels during the second frame; and a delay decision circuit configured to determine whether to increase a duration of the blanking period of the first frame based on the comparison.