225results about How to "Improve testability" patented technology

A method and apparatus for fabricating a semiconductor device are disclosed. The method attaches semiconductor chips (130) on a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias and with contact pads (103) in pad locations. A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold cavity. The substrate and the chip are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface. After pressuring encapsulation compound into the cavity, the mold is opened; the encapsulated device has apertures to the pad locations. Any residual compound formed on the pads is removed by laser, plasma, or chemical to expose the metal surface.

The RS-485 multipoint communication method includes balanced sending and differential receiving for the communication between one master machine and several slave machines. In the sending end, upper layer data is first received, protocol head is added before the data byte and CRC check is added behind the data byte, before initializing treatment and sending the data frame. In the receiving end, after the data frame is received, the frame decomposing treatment including frame head distinction, dingle board address comparison, frame length checking, data byte determination and CRC is performed before the corresponding treatment of received pure load. The present invention raises communication efficiency, facilitates RS-485 debugging, locates error correctly and increases the measurement performance while ensuring the reliability of multipoint communication.

An asset management system includes a distributed network of hierarchical controllers to manage the dispensation of assets, such as keys and the like, where the an asset is attached to an electronic fob, and the fobs are removably connected to a connection port. The hierarchical controllers are a plurality of system microprocessors and multiplexers that control a plurality of panel controllers, which in turn control a plurality of fob controllers, which in turn are physically and electronically interfaced with a plurality of fobs. The asset management system specifically manages a unique physical location of each fob on a panel. The system microprocessors are in communication with a host computer, which in turn can be in communication with other computers and other asset management systems. The system microprocessor can also control subsequent system microprocessors through a master-slave control hierarchical system.

The invention provides a service abnormity detection method and a management server. The method comprises following steps that: the management server calculates to obtain dynamic baseline values of service indexes and determines the normal interval of the service indexes; then the service index data of present time are obtained; if it is determined that the service index data are located out of the normal interval of the service indexes, warning information is generated. According to the method and the server of the invention, the normal interval of the service indexes is determined through the calculated dynamic baseline values, especially using an average value and a variance; whether the service index data are abnormal is determined; and the measurability and the maintainability of the service system are improved.

The invention provides an interface-oriented automatic test method for software fault injection, and aims at realizing the automatic test of interface fault injection. The method comprises the following steps of: firstly carrying out cross-linkage interface modeling, communication behavior modeling and protocol data modeling; designing a fault injection operator and carrying out test case modeling; automatically generating an XML-format test case on the basis of the model; and finally automatically generating the test case into a test script of C++ language on the basis of XSLT, calling windows SDK to automatically generate a test program and automatically executing the test program, realizing result collection through a Windows pipeline technology, and evaluating the test result so as to complete the fault injection test of the whole cross-linkage interface. According to the method, universality and usability realized by an interface fault injection test tool are effectively improved, the interface test efficiency is improved and the test cost is reduced.

The invention relates to a testing method for a field programmable gate array (FPGA). The method comprises the following steps: obtaining an initial design netlist and an initial design configuration of the FPGA; replacing a look-up table function of the initial design netlist and the initial design configuration with an exclusive or function of a logic function to obtain an initial testing netlist and an initial testing configuration; selecting an observation node of the initial testing netlist based on a preset rule of a testability analysis method, and obtaining a testing netlist and a corresponding testing vector; configuring an output terminal of an output and input unit from the observation node to the initial testing configuration to obtain a testing configuration; connecting the testing configuration to an configuration device according to an excitation signal of the configuration device to obtain an output logic value of the testing vector; and analyzing the output logic value and a response value of the testing vector to obtain the testing result. The method can effectively detect permanent faults of interconnection lines used in the application design of FPGA chips.

The invention discloses a DSP (digital signal processor) and FPGA (field programmable gate array) system on-line updating method, which is used for solving the problem of program online updating of a DSP and FPGA digital signal processing system. The method has the technical scheme that through a universal serial bus interface, the interconnection between a host computer and a DSP is completed; a DSP and FPGA program file to be updated is transmitted to the DSP; a Flash memory of the DSP or the FPGA is controlled to be updated by a DSP automatic updating algorithm; one group of SPI interface bus of the DSP is used for completing the hardware connection and erasing and writing of two Flashes; the bus address coding is completed through a multiplexer; the bus conflict is avoided. The program updating of the two chips of DSP and FPGA is simultaneously completed under the condition without dismounting the equipment; the interface is simple; the software and hardware design complexity is low; a simple and effective method is provided for the online updating of the digital signal processing system.

The invention relates to the technical field of electronics and discloses a DC-DC power supply device, a voltage regulation method and network equipment in order to improve the testability of circuits. In the invention, at least one regulation module and a control module are arranged in the DC-DC power supply device, wherein the control module controls the conduction states of upper and lower switch tubes in a resistor array in the regulation module so as to regulate the offset of an output voltage to control the size of the output voltage. Thus, the synchronous regulation of one or more DC-DC switch power supply modules can be realized without manual box opening and power-interrupting operation and the precision regulation of the output voltages of the DC-DCs switch power supply modules is realized without a large amount of circuit hardware regulation and change, so that the testability of the circuit and operation smoothness of the whole circuit test process are improved effectivelyand the product test and examination work is very convenient. The invention also discloses the power supply method and the network equipment.

The present invention relates to the testing technology field of electronic equipments, especially to a method and system used for assessing circuit boards corrosion risks. According to the method, the surface insulation resistance values of circuit boards are measured and are compared with the corrosion risks discrimination mapping of the circuit boards to get the corrosion risk levels of circuit boards. The present invention also provides a system used for quickly on-site assessing the circuit boards corrosion risks, which comprises a circuit board, a testing module and a discrimination module, wherein the testing module is used for measuring the surface insulation resistance value of the circuit board and sending the measured value to the discrimination module, the discrimination module is used for comparing the surface insulation resistance value measured with the corrosion risks discrimination mapping to get the corrosion risk level of the circuit board. By using surface insulation resistance values easily got on-site to indicate the circuit boards corrosion risks, the present invention is capable of quickly on-site assessing the corrosion risk of a circuit of a board, and then exhibits excellent effect about adopting some protection measures of the circuit board in time.

There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G₀, . . . , G_n−1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G₀, . . . , G_n−1) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G₀, . . . , G_n−1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

The invention provides a method for increasing the test coverage of a scan chain and a device thereof; wherein, the method for increasing the test coverage of the scan chain comprises: an input end of built-in self testing control signals of a memory being set to be zero in a scanning mode is connected into one register in the scan chain; scan test vector generated by a test vector generation tool is input into the scan chain comprising the register to test combinational logic; the test response and logic expected value of the combinational logic are compared. The method for increasing the test coverage of the scan chain provided by the invention causes that the built-in self testing control signals of the memory can be controlled when the scan chain tests, and realizes the testability of the built-in self testing logic of the memory in the scan mode, thus increasing the logic test coverage of the scan chain test and further increasing the whole test coverage of a chip.

An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a failure causing transition at a first node (t) or a second node (c) of the SRAM cell (10) by using information about the input data (data, data_b) to be written in the SRAM cell (10) and read data propagation paths to retain the output node (C, F) after a global bit line (gb_t, gb_c) at a precharge level independently from a logical level of the global bit line (gb_t, gb_c), if a corresponding node (c, t) of the SRAM cell (10) is performing the failure causing transition based on input data (data, data_b) to be written in the SRAM cell (10).

The invention provides a system and a method for debugging multiple field-programmable gate arrays (FPGAs). The method comprises the following steps: selecting and grouping to-be-tested signals according to a clock domain by virtue of a signal selection and transmission module for instantiating each to-be-tested FPGA, and configuring a high-speed serial transceiver bus port of signal transmission; performing logic synthesis and location wiring on the design logic of the to-be-tested FPGAs and the signal selection and transmission module together; finding displacement information aligned with all channels according to the longest time delay in high-speed serial bus channels of all the to-be-tested FPGAs by using a special tested FPGA in a channel alignment operating mode selected by a debugging host; and selecting a to-be-tested signal group of the to-be-tested FPGA by the debugging host, and configuring the channel time delay value by using frequency information of the to-be-tested signal group. According to the system and the method disclosed by the invention, the cross-FPGA chip signal is observed and captured by using a special tested FPGA, and the fault tracing and positioning efficiency of a debugging system is improved.

The invention provides a method and a device for testing a command line interface (CLI). The method comprises the following steps: acquiring a cluster command to be tested; conducting equivalent binary tree conversion to the cluster command from the root node of the cluster command; traversing the leaf node of the equivalent binary tree; accessing the path from the leaf node to the root node to acquire each single command and the corresponding expected prompting message; and testing the acquired single commands. The method simplifies the construction of the command tree through equivalent binary tree conversion and establishes a command tree which can be easily tested, thereby improving the testability, reducing the waste of computing resources of equipment and remarkably improving the testing efficiency.

The invention provides an electromechanical servo comprehensive control and energy source management device, which is used for servo motor control and energy source management, and comprises a microprocessing circuit, detecting circuits, a signal conversion circuit, an isolation driving amplifying circuit and an energy source management circuit, wherein the detecting circuits comprise a first voltage detecting circuit, a first current detecting circuit, a second voltage detecting circuit and a second current detecting circuit. The electromechanical servo comprehensive control and energy source management device provided by the invention has the advantages that the comprehensive management of absorption and release of energy sources can be realized, in addition, the system composition is simplified, the system weight is reduced, and meanwhile, the self test of an electromechanical servo system can be realized.