8results about How to "Improve testability" patented technology

The invention discloses an effective security domain-based post-power-grid-fault operation adequacy repairing method and system, belongs to the technical field of power grid fault repairing, and aims to solve the problems of conservative static limit, lack of visual representation of multi-section security situation and insufficient real-time cooperative correction capability in a traditional N-1 checking method. According to the method, the dynamic section limit is constructed by introducing the adjustable power flow transfer coefficient, and the visual depiction and the global strategy feasibility identification of the multi-section coupling safety boundary are realized based on the effective safety domain concept; and establishing a convex optimization collaborative repair model which takes the operation adequacy as a guide and takes the minimum total energy consumption of stored energy as a target. The improvement of quota formulation from static state to dynamic state, safety analysis from isolation to coupling and correction decision from experience to optimization is realized, and the observability of the operation state and the accuracy of the scheduling decision after the power grid breaks down are remarkably enhanced.

The application provides a voltage holding device and an electronic device using the same. The voltage holding device uses a hysteresis voltage of a hysteresis comparator to update the charge of a capacitor efficiently and pursue lower power consumption. On the other hand, because the advanced voltage holding circuit pursues lower power consumption, the refresh time must be designed to be longer, which results in the inability to perform a large amount of yield tests. However, the technical solution provided by the application can cooperate with related application circuits to greatly shorten the test time, increase the testability and reliability of the voltage holding device.

The invention discloses a three-dimensional indoor positioning method based on visual sense and 5G sensing fusion, and relates to the technical field of indoor positioning and space perception. The method comprises the following steps: modeling an indoor reflecting surface to obtain a virtual anchor point; a user azimuth vector detected, identified and tracked by a camera target is projected to a scene reflection surface to construct a candidate reflection path and identify a direct incidence path, and the candidate reflection path and the direct incidence path are mapped to a beam codebook of a base station, so that a beam search range is narrowed, and a higher angle resolution is obtained; the user terminal establishes a communication link through the reference signal, and the base station acquires channel state information; in the channel parameter processing stage, angle and time delay estimation is carried out on channel parameters; an estimation result is matched with a direct or virtual anchor point path, and pseudo paths which do not conform to scene constraints are eliminated, so that a direct path and an effective reflection path are distinguished; the position of the user is jointly solved by using multi-angle constraints formed by the direct path and the reflection path, and continuous estimation of the three-dimensional position of the user is realized by combining a filter.

This invention relates to an AGV task allocation and path planning system and method, specifically a multi-AGV task collaborative time-series allocation and path planning system and method. It addresses the problems of inflexible deployment, high costs, and inability to accurately trigger tasks based on map point arrivals in complex time-series task collaboration among multiple AGVs due to reliance on a central server. The invention includes a scheduling decision module, a status management module, a task distribution module, and a path planning service module. The status management module continuously collects real-time status and location information of the AGVs. The task distribution module sends task instructions or scheduling instructions generated by the scheduling decision module to the corresponding target AGVs. Through establishing a map network and task flow timeline, path planning, status monitoring, task issuance and execution, and fault tolerance handling steps, automated operation of multiple AGVs is achieved.

The application provides a SQL statement processing method and device and electronic equipment, and relates to the technical field of databases. The method comprises the following steps: obtaining an untyped syntax tree of a SQL statement; the untyped syntax tree comprises a plurality of nodes; determining a target node to be bound in the plurality of nodes according to a pre-obtained node binding sequence diagram; determining a previous node of the target node according to a node reference relationship diagram; obtaining a virtual table of the previous node; binding the target node based on the virtual table of the previous node, and determining a next target node to be bound until the binding of all nodes, so as to convert the untyped syntax tree into a typed syntax tree. The device is used for executing the above method. The SQL binding process in the SQL compiling process is independently implemented, and during the binding, the data type assignment and semantic verification are implemented according to the virtual table of the previous node. Since the binding methods of each node are the same, the code complexity can be reduced, and the expansibility and maintainability of the code are improved.

The invention discloses a method for efficiently testing a sealed chip by using an ATE machine, and belongs to the field of chip testing. The method is based on a test PCB integrating a manual test evaluation board and an ATE test board, and comprises the following steps: optimizing original test software; the ATE machine re-powers on the main test chip and the tested chip, and enters a functional module test stage of the tested chip; the main test chip receives a test command sent by the ATE machine table, analyzes a to-be-tested function module, sends information and test parameters of the to-be-tested function module to the tested chip, and outputs test excitation; after the tested chip receives the information and the parameters of the module to be tested, bottom layer driving operation of the function module is carried out, and a test result and a response after operation are returned to the main test chip; and the main test chip judges whether the to-be-tested functional module of the tested chip is normal or not according to the returned test data and response, and informs the ATE machine of a judgment result. According to the invention, the original factory dependence on each bare chip of the sealed chip is solved, and the testability of the sealed chip is improved.

This application provides a logic synthesis test point insertion method and related equipment based on intermediate representation, relating to the field of testability chip technology. By performing test point analysis and insertion during the intermediate representation stage of the circuit, and employing a process-independent and logically complete intermediate representation form, this method can flexibly determine the test point location without relying on specific process library features. Furthermore, it leverages the convenience of logic transformation in the intermediate representation form, providing ample space for subsequent structural optimization. This application treats the intermediate representation circuit containing test points as a unified whole for timing and area-driven process mapping, enabling the search for the optimal cell matching scheme globally. This naturally optimizes the test point structure while generating the gate-level netlist, ultimately achieving significant improvement in circuit testability while effectively controlling area overhead and ensuring the stability of timing performance.

Embodiments of the present application provide a display module, a test method thereof and a display device. The display module comprises a control circuit, a driving circuit and a display panel; the display panel comprises a test component, a test control circuit and a gate driving circuit; the driving circuit, the test component, the test control circuit and the gate driving circuit are connected in sequence; the control circuit is connected with the test control circuit, and is configured to control the test control circuit to be turned on based on a received first selection signal, so as to enable communication between the test component and the gate driving circuit; or control the test control circuit to be turned off based on a received second selection signal, so as to disable communication between the test component and the gate driving circuit. According to the embodiments of the present application, only by adding the auxiliary test circuit of the control circuit and the test control circuit, it can be determined whether the driving circuit is abnormal or the display panel itself is abnormal, the test time can be shortened, and the labor cost can be reduced.