18 results about "Self test" patented technology

An integrated circuit includes a memory having an array and a memory built-in self test (MBIST) controller. The MBIST controller is configured to perform memory testing rungs on the memory and includes a first counter and a repair control circuit. The first counter is configured to count uncorrectable errors during each memory testing run. The repair control circuit is configured to, in response to an error found during a memory testing run, determine whether at least one of row repair or column repair can be applied to repair the error.

An integrated circuit includes a comparator, a clock generator, and control circuitry. The comparator has a first input, a second input, and an output configured to provide an output clock. The clock generator is configured to generate a differential periodic signal formed from a first periodic signal and a second periodic signal. The clock generator provides the first periodic signal to the first input of the comparator and the second periodic signal to the second input of the comparator, and the clock generator is configured to vary an amplitude of the differential periodic signal based on a control input. The control circuitry is configured to measure hysteresis of the comparator by providing the control input to the clock generator to incrementally vary the amplitude of the differential periodic signal until detecting a predetermined number of state changes of the output clock.

A memory includes a data array divided into a plurality of input / output (IO) groups and a redundant IO group, each group including a set of columns. A column decoder selects one column from each IO group to provide selected data lines, and one column from the redundant group to provide a redundant data line. Repair circuitry, during normal operation, performs column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups. Read / write circuitry, in response to a read access during a test mode, outputs read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines. Control circuitry, in response to the read access during the test mode, provides the output read data sensed from the redundant data line external to the memory via a memory output pin.

An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input / output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input / output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.

A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

Illustrative integrated circuit devices are provided with built-in self test circuit designs and verification methods. One disclosed integrated circuit device includes: an analog circuit block configured to be powered by a current flow from a first power rail and an intermediate node; a current sensor configured to provide digital measurements of the current flow; a built-in self test circuit configured to set the analog circuit block in a sequence of operating modes and coupled to the current sensor to capture for each operating mode a corresponding one of the digital measurements.

A memory device comprising a memory core including a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks, a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank, and a control circuit configured to control the parallel test. The BIST circuit may determine at least one defective memory cell outputting a defective bit among target memory cells included in the target memory bank, and may determine whether the defective memory cell is a single defective memory cell or an adjacent double defective memory cell, and the control circuit May determine the target memory bank to be a defective memory bank when the defective memory cell is not the single defective memory cell and the adjacent double defective memory cell.

Aspects of the disclosure are directed to a built-in self test (BIST) mode save and restore operation. In accordance with one aspect, the disclosure includes executing a save directive for an initial state of a digital logic system in an operational mode; executing a built-in self test (BIST) sequence on the digital logic system in a built-in self test (BIST) mode; and executing a restore directive in the digital logic system in the operational mode.

A defect detecting system of an automotive apparatus is provided. The defect detecting system includes: a digital function block including: a memory device configured to store data, and a first Built-In Self Test (BIST) configured to detect a defect of the memory device; an analog function block including a verification parity generator configured to: receive the data through a first path, generate verification parity of the data, and transmit the verification parity to the digital function block through a second path; and a level shift block connected between the digital function block and the analog function block, wherein the level shift block is configured to: convert the first path from a first power supply voltage to a first level based on a second power supply voltage, and convert the second path from the second power supply voltage to a second level based on the first power supply voltage.

Aspects of the disclosure are directed to a built-in self test (BIST) mode save and restore operation. In accordance with one aspect, the disclosure includes executing a save directive for an initial state of a digital logic system in an operational mode; executing a built-in self test (BIST) sequence on the digital logic system in a built-in self test (BIST) mode; and executing a restore directive in the digital logic system in the operational mode.

In some implementations, an automated self-testing system may include an electric field source (204) and a controller (206). The controller (206) may detect a trigger event associated with initiating a self test of an electric field sensing device (202). The controller (206) may cause, based on the trigger event, the electric field source (204) to create a target electric field at a specific location sensed by the electric field sensing device (202). The controller (206) may receive measurement data indicating a measured electric field strength, detected by the electric field sensing device (202), of the target electric field. The controller (206) may determine, based on the target electric field strength and the measured electric field strength, whether the electric field sensing device (202) passes the self test or does not pass the self test. The controller (206) may provide an indication of a result of the self test.

A circuit self-test apparatus includes a circuit under test including a plurality of scan chains, where each of the plurality of scan chains includes a plurality of scan cells, and where each of the plurality of scan chains are configured based on a weight and a correlation obtained from a determination pattern input into each of the plurality of scan cells, and a test circuit including a linear feedback shift register (LFSR) configured to generate a random pattern for each of the plurality of scan chains, where the test circuit is configured to generate a modification pattern for each of the plurality of scan chains based on the random pattern and a state of the LFSR.

A circuit includes one or more functional circuits, and a clock generation circuit operatively coupled to the one or more functional circuits. The clock generation circuit is configured to: receive a control signal to switch the one or more functional circuits between a first operation mode and a second operation mode; receive a first clock signal and a second clock signal corresponding to the first operation mode and the second operation mode, respectively; and output, to the one or more functional circuits, a clock pulse signal based on either the first clock signal or the second clock signal. The clock generation circuit is configured to generate either a first conduction path to output the clock pulse signal or a second conduction path to output the clock pulse signal. Each of the first and second conduction paths includes a predefined number of gate delays.

A cryptocurrency miner includes compute modules and a controller. Each compute module includes a stats store, a manager, and compute engines. The controller is coupled to the compute modules via a serial bus and distributes one or more jobs to the compute modules via the serial bus. Each manager distributes jobs received by its respective compute module among the compute engines of its respective compute module. Each compute engine processes a job and reports a candidate hit found by processing the job. Each manager validates a candidate hit reported by one of the compute engines of its respective compute module, reports the validated candidate hit to the controller; and updates statistical information in the stats store of its respective compute module based on validation of the candidate hit.

A semiconductor device and a method of operating the semiconductor device and circuit are disclosed. In one aspect, the semiconductor device includes a memory array comprising a first memory cell and a second memory cell. The second memory cell has an operational characteristic different than that of the first memory cell. The semiconductor device includes a first write circuit configured to write first data to the first memory cell. The semiconductor device includes a second write circuit configured to write second data to the second memory cell, wherein the second write circuit is selectively configured to compensate for the operational characteristic of the second memory cell.

Various embodiments are directed to example system-on-chip integrated circuits configured to perform built-in self test operations on an embedded memory. An example system-on-chip integrated circuit includes dynamic BIST switching circuitry and an embedded memory. The dynamic BIST switching circuitry is configured to generate a dynamic BIST output based on a test state. The embedded memory is configured to receive the dynamic BIST output. The embedded memory includes fixed BIST switching circuitry configured to generate a fixed BIST output based on the test state. Wherein the fixed BIST switching circuitry is internal to the embedded memory, and the dynamic BIST switching circuitry is external to the embedded memory.

A projector system for a head up display within a vehicle includes a vehicle vector graphics projector adapted to project a second graphical image onto the inner surface of the windshield of the vehicle, the second graphical image having a greater brightness than the first graphical image and including at least one vehicle tell-tale, and a calibration system adapted to test and calibrate a displayed tell-tale within the second graphical image.

In some implementations, an automated self-testing system may include an electric field source and a controller. The controller may detect a trigger event associated with initiating a self test of an electric field sensing device. The controller may cause, based on the trigger event, the electric field source to create a target electric field at a specific location sensed by the electric field sensing device. The controller may receive measurement data indicating a measured electric field strength, detected by the electric field sensing device, of the target electric field. The controller may determine, based on the target electric field strength and the measured electric field strength, whether the electric field sensing device passes the self test or does not pass the self test.