24035 results about "Condensed matter physics" patented technology

A laminated structure comprises a first layer comprising a crystal with six-fold symmetry, and a second layer comprising a metal oxynitride crystal formed on the first layer, wherein the second layer comprises at least one element selected from the group consisting of In, Ga, Si, Ge and Al, N, O and Zn, as main elements, and wherein the second layer has in-plane orientation.

Described herein are improved capabilities for a source resonator having a Q-factor Q₁>100 and a characteristic size x₁ coupled to an energy source, and a second resonator having a Q-factor Q₂>100 and a characteristic size x₂ coupled to an energy drain located a distance D from the source resonator, where the source resonator and the second resonator are coupled to exchange energy wirelessly among the source resonator and the second resonator.

The invention provides a thin film transistor comprising an active layer, the active layer comprising an IGZO-based oxide material, the IGZO-based oxide material being represented by a composition formula of In_2-xGa_xZnO_4-δ, where 0.75<x<1.10 and 0<δ≦1.29161×exp(−x/0.11802)+0.00153 and being formed from a single phase of IGZO having a crystal structure of YbFe₂O₄, and a method of producing the thin film transistor.

In embodiments of the present invention improved capabilities are described for a method and system comprising a source resonator optionally coupled to an energy source and a second resonator located a distance from the source resonator, where the source resonator and the second resonator are coupled to provide near-field wireless energy transfer among the source resonator and the second resonator and where the field of at least one of the source resonator and the second resonator is shaped to avoid a loss-inducing object.

The present invention promotes incorporation of nitrogen (e.g., nitridation) into high-k dielectric films using a low temperature process. Further, the present invention provides an in-situ method; that is formation of the high-k dielectric film and nitridation of the film are carried out in the same process chamber during deposition of the film, as opposed to the conventional post processing techniques. In another aspect, a method for depositing a multi-layer material for use as a gate dielectric layer in semiconductor devices is provided.

A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, and PbZrO₃.

A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.

A method for growing a nitride crystal and a crystalline composition selected from one of AlN, InGaN, AlGaInN, InGaN, and AlGaNInN is provided. The composition comprises a true single crystal, grown from a single nucleus, at least 1 mm in diameter, free of lateral strain and tilt boundaries, with a dislocation density less than about 10⁴ cm⁻².

A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.

A method includes growing a first epitaxial layer of III-nitride material, forming a damaged region by implanting ions into an exposed surface of the first epitaxial layer, and growing a second epitaxial layer of III-nitride material on the exposed surface of the first epitaxial layer. A level of defects present in the second epitaxial layer is less than a level of defects present in the first epitaxial layer.

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material and has a second magnetization directed in the direction perpendicular to the film surface, the direction of the second magnetization reversing by the spin-polarized electrons, and a first nonmagnetic layer which is provided between the first pinned layer and the free layer. A saturation magnetization Ms of the free layer satisfies a relationship 0≧Ms<√{square root over ( )}{Jw/(6nAt)}. Jw is a write current density, t is a thickness of the free layer, A is a constant.

Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

The present invention provides a method and apparatus for preferential PVD conductor fill in an integrated circuit structure. The present invention utilizes a high density plasma for sputter deposition of a conductive layer on a patterned substrate, and a pulsed DC power source capacitively coupled to the substrate to generate an ion current at the surface of the substrate. The ion current prevents sticking of the deposited material to the field areas of the patterned substrate, or etches deposited material from the field areas to eliminate crowning or cusping problems associated with deposition of a conductive material in a trench, hole or via formed on the substrate.

In embodiments of the present invention improved capabilities are described for a method and system comprising a source resonator optionally coupled to an energy source and a second resonator located a distance from the source resonator, where the source resonator and the second resonator are coupled to provide near-field wireless energy transfer among the source resonator and the second resonator and where the field of at least one of the source resonator and the second resonator is shaped using a magnetic material to avoid a loss-inducing object.

A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also disclosed.