2476 results about "Condensed matter physics" patented technology

Crystal growth systems with a baffle are provided. In one example, a crystal growth system for growing crystalline material, the crystalline material including silicon carbide, includes a seed holder configured to hold a silicon carbide seed crystal. The seed crystal provides a growth surface for growth of the silicon carbide crystalline material. The system includes a crucible at least partially defining a crystal growth chamber. The system includes a source material. The system includes one or more baffles within the crystal growth chamber and spaced apart from the source material. The one or more baffles include one or more apertures defined through the one or more baffles. The baffle includes a long dimension that is non-perpendicular to the growth surface of the seed crystal.

The invention relates to a czochralski method-based crystal growth interface shape detection method and device. The method comprises the steps that: a seed crystal temperature T and an interface electromotive force U at the same time in a crystal growth process are collected, and a T-U curve of the interface electromotive force U changing with the seed crystal temperature T is obtained; the change trend of the shape of a crystal growth interface in real time is judged by observing the deviation between the T-U curve and a reference line, wherein the reference line is a straight line passing through the starting point of the T-U curve, and the slope of the straight line is the Seebeck coefficient of the crystal. The invention also relates to a device used by the method. The detection method provided by the invention can detect the change trend of the shape of the crystal growth interface in real time in the crystal growth process, and can be applied to Czochralski method growth equipment for various single crystals such as lithium niobate, lithium tantalate, sapphire, yttrium aluminum garnet and the like.

An optoelectronic device has a substrate layer having a first surface plane and a second surface plane opposite and parallel to the first surface plane. The device also has a mesa structure arranged on the first surface plane of the substrate layer. The mesa structure has at least one layer of III-V material; and a first surface arranged at an angle α with respect to the first surface plane of the substrate layer, wherein the angle α is different from 0˚ and 180˚. The device still further includes a first terminating oxide layer of a first type arranged on the first surface of the mesa structure and the first surface of the mesa structure has been cleaned by removing at least 75 % of native oxides on the first surface of the mesa structure before arranging the first terminating oxide layer of a first type thereon.

A semiconductor device includes an active region extending in a first direction; a gate structure on the active region and extending in a second direction intersecting the first direction; source / drain regions on side surfaces of the gate structure and on the active region; front side contacts on a first side of the source / drain regions; backside contacts at least partially penetrating the active region and on a second side of the source / drain regions opposite the first side; and an interlayer insulating layer on the gate structure, on the source / drain regions, and on the front side contacts. An entire upper surface of the gate structure that is opposite the active region in a third direction perpendicular to the first and second directions is in contact with the interlayer insulating layer.

Techniques for tuning the NP boundary between the gate electrode materials of NMOS and PMOS transistors so that the NP boundary is closer to the PMOS transistor can enable the fabrication of a PMOS transistor that is weaker than the adjacent NMOS transistor. In one example, an IC structure includes a first nanoribbon stack and a second nanoribbon stack adjacent to the first nanoribbon stack, a first gate electrode material (e.g., including an N-type work function metal) at least partially around nanoribbons of the first stack and a second gate electrode material (e.g., including a P-type work function metal) at least partially around the nanoribbons of the second stack, where a boundary between the first gate electrode material and the second gate electrode material is closer to the second nanoribbon stack than the first nanoribbon stack.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

The invention provides a transistor with a programmable horizontal double-floating-gate homojunction. The transistor comprises two floating gate layers which are independent from each other and are composed of multiple layers of graphene; the tunneling layer is positioned above the floating gate layer; the channel layer is positioned above the tunneling layer; the source electrode and the drain electrode are located above the two ends of the channel layer respectively, so that the floating gate layer can achieve regulation and control of source-drain contact, and then it is guaranteed that a floating gate electric field can achieve regulation and control of Schottky barriers of the source electrode and the drain electrode; and the two direct tunneling electrodes are respectively positioned above two ends of the tunneling layer and are not in contact with the channel layer, so as to inject charges into the floating gate layer. The invention also provides a preparation method of the transistor. According to the transistor provided by the invention, a bilateral floating gate is used for regulating and controlling an energy band in contact with two sides, and any one of four junctions (a p-n junction, an n-p junction, a p-p junction and an n-n junction) can be freely formed and switched.

This utility model discloses a high-temperature resistant cooling circulation structure for a fluoroplastic magnetic pump, specifically relating to the field of magnetic pumps. It includes a base, pump body, pump cover, connecting frame, isolation sleeve, inner magnetic rotor, outer magnetic rotor, motor, and impeller. The isolation sleeve, inner magnetic rotor, and outer magnetic rotor are all housed inside the connecting frame. The high-temperature resistant cooling circulation structure of this fluoroplastic magnetic pump features a spiral cooling channel inside the isolation sleeve. The coolant flows directly through the core area of ​​the heat source, rapidly absorbing heat transferred by magnetic eddy currents and high-temperature media through forced convection, thus improving cooling efficiency and effectively blocking heat transfer to the outer magnetic rotor, preventing permanent magnets from demagnetizing and failing due to high temperatures. Copper-nickel alloy heat-conducting fins are welded to the inner wall of the isolation sleeve, combined with a layer of thermally conductive silicone grease, accelerating the conduction of heat from the inner magnetic rotor to the cooling channel. A vacuum cavity is provided between the spiral cooling channel and the outer wall of the isolation sleeve to suppress heat conduction to the outer magnetic rotor, achieving double thermal isolation.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, which comprises: a substrate comprising an array region and a peripheral circuit active region, wherein the peripheral circuit active region comprises at least a first PMOS region and a second PMOS region, the gate oxide layer thickness of the PMOS tube formed in the first PMOS region is less than that of the PMOS tube formed in the second PMOS region; a first insulating layer covering the bottom and sidewall of the first PMOS region towards the substrate, and the top of the first insulating layer is flush with the top of the substrate; a dielectric layer covering the first insulating layer, and the top of the dielectric layer in the first PMOS region is lower than the top of the substrate; a second insulating layer covering the dielectric layer, and the top of the second insulating layer in the first PMOS region is flush with the top of the substrate; and a pad layer covering the top of the substrate in the first PMOS region, so as to improve the defect problem between the isolation structure of the first PMOS region in the peripheral circuit active region and the top of the substrate.

A magnetic component is disclosed and includes a first magnetic core, a second magnetic core and a coil. The first magnetic core includes a first magnetic cover and a first guiding portion. The second magnetic core includes a second magnetic cover and a second guiding portion. The first magnetic core and the second magnetic core are butted along an axial direction to form a winding column. The first guiding portion is located on the first magnetic cover, and increases a depth embedded into the first magnetic cover. The second guiding portion is located on the second magnetic cover, and increases a depth embedded into the second magnetic cover. The coil is wound on the winding column at a helical angle α relative to the winding column, and includes a first outlet terminal and a second outlet terminal led out along the first guiding portion and the second guiding portion, respectively.

The application relates to the technical field of motors, in particular to a rotor magnetic ring and a hollow cup motor. The rotor magnetic ring is a polar anisotropic magnetic ring, which comprises at least two pairs of magnetic poles, each pair of the magnetic poles is oppositely arranged on the two sides of the rotor magnetic ring, and the magnetic properties of adjacent magnetic poles are opposite; each magnetic pole comprises at least two magnetic force units arranged along the circumference of the magnetic pole in sequence, the magnetization directions of adjacent magnetic force units have a deflection angle beta, and the magnetization directions of all the magnetic force units are arranged along the circumference with the deflection angle beta, so that the magnetic field intensity on the outer side of the rotor magnetic ring is greater than that on the inner side, the magnetic field energy is concentrated in an effective working area, and the overall working performance of the hollow cup motor is improved.

To provide a magnetic recording device capable of stable recording operation.SOLUTION: A magnetic recording device 150 includes a magnetic recording medium group 20 and a magnetic head group 30. The magnetic recording medium group includes a first magnetic recording medium 21; a plurality of second magnetic recording media 22; and a plurality of third magnetic recording media 23. The magnetic head group includes a first magnetic head 31; a plurality of second magnetic heads 32; and a plurality of third magnetic heads 33. The first magnetic head can record data in the first magnetic recording medium by a first method. The plurality of second magnetic heads can record data in the plurality of second magnetic recording media by a second method. The plurality of third magnetic heads can record data in the plurality of third magnetic recording media by the second method. The first magnetic recording medium is provided between the plurality of second magnetic recording media and the plurality of third magnetic recording media in a first direction D1. The other magnetic recording medium in which the data is recorded by the first method does not overlap with the magnetic recording medium group in the first direction.SELECTED DRAWING: Figure 1

This document discloses a three-dimensional (3D) magnetoresistive random access memory (MRAM) device comprising a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to the main surface of a substrate of the 3D MRAM device. Each of the plurality of cells is separated from another cell of the plurality of cells by an insulating layer among the plurality of insulating layers. Each of the plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type, the second interconnect structure being configured to interface with the MTJ structure of the cell. The orientation of the first interconnect structure is orthogonal to the second interconnect structure of each of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

Provided are semiconductor structures and methods for fabricating semiconductor structures. A method includes forming a stack of semiconductor nanosheets over a substrate; forming a sacrificial gate structure over the stack of semiconductor nanosheets; forming a liner adjacent to the sacrificial gate structure; forming a dielectric layer adjacent to the liner; removing the sacrificial gate structure to form a gate cavity; performing an oxidation process to oxidize a portion of the liner adjacent to the gate cavity; and removing the portion of the liner adjacent to the gate cavity.

A fin transistor with discontinuous channel regions includes M gate terminal structures, N drain terminal structures, and a conductive structure. Each gate terminal structure includes a first channel structure including a source region and a first channel region, and a gate structure formed on surfaces of the first channel region. Each drain terminal structure includes a second channel structure including a second channel region and a drain region, where the second channel region and the first channel region are two discontinuous regions, and a reduced surface field structure formed on surfaces of the second channel region. The conductive structure is coupled to the first channel region of one of the M gate terminal structures and the second channel region of one of the N drain terminal structures. The fin transistor of the present invention can achieve high voltage withstand and low on-resistance simultaneously.

This invention provides a nitride LED epitaxial wafer, its fabrication method, and its application. The nitride LED epitaxial wafer includes a substrate, a composite buffer layer, a nitride buffer layer, a first nitride semiconductor layer, a nitride light-emitting layer, and a second nitride semiconductor layer stacked together. The composite buffer layer comprises n sets of stacked composite buffer sublayers. The first to (n-1)th sets of composite buffer sublayers respectively include a modulation sublayer, a first capping sublayer, a composite structure sublayer, and a second capping sublayer stacked together. The nth set of composite buffer sublayers includes a modulation sublayer, a first capping sublayer, and a composite structure sublayer stacked together, where n ≥ 2. The composite structure sublayer has a nanostructured pattern. By employing the solution provided by this invention, the problems of dislocations or defects caused by lattice constant and thermal mismatch can be overcome, enabling the development of multifunctional buffer technology.

In a general aspect, a multilayer board structure is used to mechanically support and electrically connect a quantum processing unit. In some aspects, a multilayer board structure includes a stack of printed circuit boards. Each printed circuit board in the stack includes a dielectric substrate, a copper layer on a surface of the dielectric substrate; and a superconductive layer electroplated on a surface of the copper layer such that the copper layer is sandwiched between the superconductive layer and the dielectric substrate.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a source region and a drain region formed therein, a drift region formed in the substrate between the source region and the drain region, the drift region being in contact with the drain region, a gate structure formed on a top of the substrate at an interface of the source region and the drift region; forming a first dielectric layer on the top of the substrate at the source region, the drain region and the drift region, the first dielectric layer also covering sidewalls of the gate structure; forming a recess in a middle region of a top surface of the first dielectric layer at the drift region; after forming the recess, forming a first trench in a portion of the first dielectric layer at the drift region, the first trench being in communication with the recess, forming a second trench through the first dielectric layer at the source region and the drain region; forming a field plate contact hole in the first trench, the field plate contact hole covering the first dielectric layer at a bottom of the first trench, forming an interconnection via structure in the second trench, the interconnection via structure being in electrical connection with the source region and the drain region. The thickness uniformity of the first dielectric layer below the bottom of the first trench is improved.

A method for forming a semiconductor structure is provided. The method includes forming a first transistor and a second transistor on a substrate, respectively. The first transistor includes a first source / drain feature adjoining first channel layers and a first gate stack surrounding the first channel layers. The second transistor includes a second source / drain feature adjoining second channel layers, and a second gate stack surrounding the second channel layers. The method further includes forming a first contact plug that partially passes through the first source / drain feature from the backside surface of the first source / drain feature, and forming a second contact plug that partially passes through the second source / drain feature from the backside surface of the second source / drain feature. The first contact plug is shallower than the second contact plug.

A magnetic internal sealing device for a soft oxygen chamber is installed at the chamber door and chamber entrance. The chamber door seals the chamber entrance. The magnetic internal sealing device includes an inner sealing element and a sealing strip. The sealing strip includes a left magnetic strip and a right magnetic strip. The inner sealing element is a sealing magnetic strip, which includes a left magnetic strip and a right magnetic strip. The left magnetic strip is located on the side of the left magnetic strip away from the right magnetic strip, and the right magnetic strip is located on the side of the right magnetic strip away from the left magnetic strip. The left and right magnetic strips are respectively installed on the inner edge of the chamber entrance and the inner edge of the chamber door. When the left and right magnetic strips are magnetically attracted, the edges of the left and right magnetic strips are completely fitted together and sealed. This magnetic internal sealing device has the characteristics of high reliability, good sealing performance, wide applicability, and ease of use.

This application discloses a Si-based GaN epitaxial wafer, a semiconductor device, a method for manufacturing the Si-based GaN epitaxial wafer, and a method for manufacturing the semiconductor device, belonging to the field of semiconductor epitaxial growth. The Si-based GaN epitaxial wafer includes: a Si substrate; an AlN nucleation layer located on the Si substrate; and a buffer layer located on the AlN nucleation layer, wherein the buffer layer includes at least Al... x Y 1‑x N sublayer and Al y Y 1‑y N sublayer, Al x Y 1‑x The N-sublayer is located near the epitaxial wafer growth direction, Al y Y 1‑y The N sublayer is located on the far side of the growth direction, and y <x,Al y Y 1‑y The lattice constant of the N sublayer is greater than that of GaN; GaN insertion layer; GaN channel layer; HEMT functional layer; The Si-based GaN epitaxial wafer disclosed in this application can provide stronger voltage withstand performance with a thinner buffer layer thickness.

The application provides a full-bridge magnetoresistance sensor and an electronic device. The circuit structure of the full-bridge magnetoresistance sensor is a full-bridge circuit structure, and the long axis directions of each sensing unit on adjacent bridge arms in the full-bridge circuit structure are parallel. The sensing unit comprises a flip function layer, a dielectric layer and a magnetoresistance thin film arranged from bottom to top. The flip function layers of the sensing units on two parallel bridge arms are connected to the same current input end, and the flip function layers of the sensing units on the other two parallel bridge arms are connected to the same ground end. By applying a single current to the current input end, the current flowing through the flip function layers of the adjacent bridge arms is opposite, so that the pinning direction of the anti-ferromagnetic layer of the sensing unit in which the heat generated by the flip function layer and the local magnetic field are reversed is opposite, and then the magnetization direction of the reference layer in the sensing unit on the adjacent bridge arm is opposite, so that a complete full-bridge structure is realized on a single chip, and the effect of flexibly setting or resetting the reference layer direction after production or during use can be achieved.

The application discloses a sound production monomer and an electronic device. The sound production monomer comprises a magnetic circuit system, a vibration system and a shell. The magnetic circuit system comprises a magnetic yoke and a magnet assembly arranged on the magnetic yoke. The magnet assembly forms a magnetic gap. The magnet assembly comprises a first magnet, a second magnet, a third magnet and a fourth magnet. The first magnet and the third magnet are magnetized along a second direction and the magnetization directions are opposite. The second magnet and the fourth magnet are magnetized along a first direction. The first direction is perpendicular to the second direction. The polarity of the magnetic pole of the second magnet facing the first magnet is the same as the polarity of the magnetic pole of the first magnet close to the magnetic gap. The polarity of the magnetic pole of the fourth magnet facing the third magnet is the same as the polarity of the magnetic pole of the third magnet close to the magnetic gap, so that the magnet assembly forms a magnetic field enhancement side facing the magnetic gap. The vibration system comprises a diaphragm and a flat voice coil. The magnet assembly forms a magnetic field enhancement side facing the magnetic gap, which improves the magnetic field driving force and the acoustic performance of the loudspeaker.

This invention relates to a graphene spin device, its construction method, and a method for measuring nonlocal signals. The construction method of the graphene spin device includes the step of setting electrodes on the graphene surface; wherein, the electrodes are set by magnetron sputtering, using a direct current, and the magnetron sputtering power is 200±10W. This invention creates defects at the contact point between the graphene and the electrodes through magnetron sputtering under specific conditions, forming serrated graphene edges. Then, it utilizes the unique magnetism of graphene to construct a spin device. This spin device has high spin polarization and long spin transport distance. More importantly, this spin device relies solely on the magnetism of the graphene itself for spin injection and spin detection, providing a new approach for the development of graphene spin devices. It can be used for nonlocal measurements at room temperature, has low requirements for experimental environmental conditions, and is beneficial for exploring some nontrivial electrical mechanisms.

A coil component, a circuit board, and an electronic device are provided. A coil component of one embodiment includes a magnetic core including a plurality of ferrite crystal grains and a plurality of Bi-segregation regions existing at grain boundaries of the plurality of ferrite crystal grains, and a winding wound around the magnetic core. In one embodiment, a plurality of line profiles obtained by detecting the content of Bi along a plurality of scan lines intersecting the grain boundaries includes at least one first line profile including a detected peak of Bi at the grain boundary, and a plurality of second line profiles not including the detected peak.

The utility model provides a novel silicon base MOSFET super junction structure relates to the field of silicon base MOSFET, including silicon base MOSFET body, the lower surface of silicon base MOSFET body is connected with the conductive type epitaxial layer, the outside of silicon base MOSFET body is equipped with the heat dissipation assembly for cooling structure, the inside of silicon base MOSFET body is equipped with the super junction assembly for silicon base MOSFET super junction, the heat dissipation assembly includes the encapsulation board, the encapsulation board is fixed in the lateral wall of silicon base MOSFET body, the lower end of silicon base MOSFET body is connected with N cylinder. The utility model discloses a heat dissipation assembly, the heat absorption end of heat pipe is connected with N cylinder and P cylinder, makes heat pipe to pass through the evaporation and condensation of liquid to transfer heat, and then effectively carries out the heat dissipation to the silicon base MOSFET super junction structure, reduces the condition of the leakage current increase of high temperature occurrence, improves the long-term reliability of device.

A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises an active region. A gate trench (360) is provided in an upper portion of the semiconductor layer structure, the gate trench having a first rounded lower corner and a second rounded lower corner (366). A gate electrode (380) is provided in the gate trench. Within the active region, an upper surface of the gate electrode is below or coplanar with an upper surface of the semiconductor layer structure.

A flux-mnemonic permanent magnet synchronous machine (FMPMSM) includes: an annular stator having a winding; a rotor disposed concentric with the stator; and a power inverter for dispensing an excitation current and at least one current pulse. The rotor includes: at least two circumferentially magnetized adjustable permanent magnets, each permanent magnet having two poles normal to an air gap between the stator and rotor; and one or more flux adjusters adjacent to one or more magnet poles of the permanent magnets. A polarization ratio of magnetization of at least one of the permanent magnets is adjustable during operation of the FMPMSM by application of the at least one current pulse.