179 results about "Epitaxial material" patented technology

The invention discloses a solar cell with alloy as a flexible substrate and a preparation method thereof, a kovar alloy sheet is used as the flexible substrate to be bonded with an epitaxial layer, the coefficient of thermal expansion of the kovar alloy sheet is similar to that of an epitaxial material, and dark cracks of the epitaxial layer caused by cold and hot temperature difference are avoided; moreover, the metal bonding layer adopts a thick-silver thin-gold structure taking silver as a substrate, so that the production cost is greatly reduced, and the weldability of the back electrode is enhanced; and the back electrode also adopts a thick silver and thin gold structure taking silver as a substrate, so that the front warping of the Kovar alloy sheet can be balanced, the weldability of the back electrode is enhanced, the drawing force of the back electrode is improved, the thin gold plated on the thick silver can also prevent silver oxidation and resist the impact of atomic oxygen, and the service life of the solar cell is prolonged.

The invention provides an optimized II-type superlattice infrared detector chip bottom filling method, a preparation method and an infrared detector, and belongs to the field of infrared detectors. The problem that the performance of an infrared detector is affected due to the fact that the filling glue filled in an existing bottom filling process is prone to generating holes and finally causes defects during imaging of an infrared focal plane detector chip is solved. The method comprises the following steps that a dielectric layer is deposited on the surface of an epitaxial material after table top etching is completed, and the height of the dielectric layer is larger than the table top etching depth; after the dielectric layer is deposited, the surface of the dielectric layer is polished to be flat; opening holes in the dielectric layer on the surface of the table board; preparing an indium column in the opening of the dielectric layer, and then performing flip-chip bonding interconnection on the indium column at the epitaxial material end and the indium column on the readout circuit; filling bottom filling glue between the dielectric layer and the reading circuit after the reverse welding interconnection, and then curing the filling glue at high temperature; the invention is applied to the type-II superlattice infrared detector.

The invention discloses a low-divergence-angle narrow-linewidth high-power semiconductor laser. Relates to the technical field of semiconductor lasers, in particular to a low-divergence-angle narrow-linewidth high-power semiconductor laser. According to the invention, the parabolic waveguide structure is etched in the light field expansion area, and the metal reflector is introduced to realize a novel light field expansion and metal reflector integrated structure, and the transverse divergence angle of a laser mode is reduced through the expansion structure at the tail end of the waveguide. The laser comprises a laser gain area, a light field expansion area and a spectrum purification area at the tail of the light field expansion area. The laser gain region, the light field expansion region and the spectrum purification region at the tail part of the light field expansion region are made of the same laser epitaxial material in the longitudinal direction, the laser gain region is adjacent to the light field expansion region along the horizontal light emitting direction, and the light field expansion region is adjacent to the spectrum purification region at the tail part of the light field expansion region along the horizontal light emitting direction; the longitudinal direction is the direction from the substrate to the contact layer.

The invention relates to the technical field of semiconductor equipment, and provides vertical epitaxy equipment and an epitaxy method. The apparatus comprises: a vertical reaction chamber; the wafer boat is used for vertically loading a plurality of wafers at intervals; the driving device is used for driving the boat to enter / exit the vertical reaction cavity; the material supply assembly comprises a process supply pipeline and a switching unit; the process material source comprises a cleaning material source for removing an oxide layer on the surface of the wafer and an epitaxial material source for executing an epitaxial process; the process monitoring device is used for monitoring process end points of the cleaning process and the epitaxial process; and the control device is in communication connection with the switching unit and the process monitoring device, and controls the switching unit to switch the supply of the material source according to the monitoring result of the process monitoring device. According to the vertical epitaxial equipment, the epitaxial process can be continuously executed without transferring the wafers after the oxide removal process of the plurality of wafers is executed in situ in the equipment, so that the output rate and the yield of the equipment are improved, the cost is reduced, and the fragment and pollution risks are reduced.

The invention discloses a preparation method and a structure of a photonic integrated device, and the method comprises the steps: sequentially dividing a substrate into a front modulator region, a rear modulator region, a front grating region, a gain region and a rear grating region, and growing a first active layer after manufacturing a selected region epitaxial mask pattern in the gain region, the method comprises the following steps of: growing a first active layer in a front modulator region after mask etching operation, growing a second active layer in a front modulator region after mask etching operation, growing a third active layer in a grating region after mask etching operation, finally performing grating manufacturing, and completing manufacturing of a cladding layer, an electric contact layer, an inverted table shallow ridge waveguide structure, an electric isolation trench and an electrode. According to the method, integration of multiple materials is achieved through one-time selective area epitaxial growth and one-time butt joint growth, the material growth frequency is reduced, and the manufacturing cost is saved; the gain region and the rear modulator region realize forbidden band width offset through selective region epitaxial material growth, and multi-wavelength tuning and efficient modulation are realized through fluorescence wavelength difference design of each region, so that a solution can be provided for integration of a wide-wavelength tunable laser and a double-electro-absorption modulator.

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure and a preparation method thereof. The light-emitting diode epitaxial structure comprises a substrate, an h-BN / O2 layer, a low-temperature GaN buffer layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer which are arranged in sequence, the h-BN / O2 layer subjected to oxygen plasma treatment is inserted between the heterogeneous substrate and the GaN epitaxial layer, the low-temperature GaN buffer layer is grown on the h-BN / O2 layer by controlling the process conditions, and the h-BN / O2 layer and the low-temperature GaN buffer layer are matched, so that lattice mismatch dislocation, residual stress and thermal mismatch of an epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, and the light emitting efficiency is improved. The probability of radiation recombination of the heteroepitaxial material is improved, and the requirement for heteroepitaxy is lowered.

The invention relates to a semiconductor device with a temperature sensor and a preparation method thereof, and the key points of the technical scheme are that the method comprises the steps: constructing a super-junction charge balance region on the surface of a substrate, and forming a body region at the top of the super-junction charge balance region; generating a first shallow trench and a second shallow trench on the body region; sequentially depositing an oxidation dielectric layer and first polycrystalline silicon in each of the first shallow trench and the second shallow trench; etching the first polycrystalline silicon in the second shallow trench, and depositing second polycrystalline silicon above the first polycrystalline silicon in the second shallow trench; depositing a dielectric layer on the surface of the body region, and etching in the dielectric layer to form a contact hole; the contact hole is communicated with the first polycrystalline silicon and the second polycrystalline silicon; the temperature detection diode structure is integrated in the epitaxial material of the device, and the problem that the internal thermal characteristics of the device cannot be fed back in time is solved by improving the manufacturing process under the condition that the characteristics of the device are not influenced by utilizing the linear relation between the forward conduction voltage and the temperature of the diode.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention provides a manufacturing method of a type-II superlattice medium-wave infrared focal plane array chip and an infrared detector, and belongs to the field of infrared focal plane array chips. The problem that in the prior art, the surface leakage current of an infrared focal plane array chip is large due to the fact that the mesa etching depth is large is solved. The method comprises the following steps: growing and cleaning an epitaxial material; hard mask deposition, mesa photoetching and etching: obtaining a required mesa pattern on the hard mask through a photoetching technology, then etching an epitaxial material, etching the epitaxial material to form the mesa pattern, the mesa pattern comprising an upper electrode region and a lower electrode region, etching the upper electrode region to the boundary of the barrier layer and the absorption region, and etching the lower electrode region to the boundary of the barrier layer and the absorption region; etching a lower electrode region to the lower ohmic contact layer; manufacturing a metal electrode; a connecting piece is manufactured on the metal electrode to be connected with a reading circuit, and manufacturing of the infrared focal plane array chip is completed; the invention is applied to the II-type superlattice medium-wave infrared detector.

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure which comprises a substrate, and a graphene composite nano layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer are sequentially stacked on the substrate. The graphene composite nano layer comprises a modified graphene layer and a ZnO sub-layer which are stacked in sequence, the modified graphene layer is arranged on the substrate, and the ZnO sub-layer is arranged on the modified graphene layer; the modified graphene layer is subjected to nitrogen plasma treatment, and the thickness of the modified graphene layer is 10-100 nm; and the thickness of the ZnO sub layer is 20 nm to 200 nm. According to the invention, lattice mismatch dislocation, residual stress and thermal mismatch of the epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, the probability of radiation recombination of the heterogeneous epitaxial material is improved, and the requirement of heterogeneous epitaxy is relaxed at the same time.

The invention discloses a packaging structure of a micro-VCSEL chip and a manufacturing method of the packaging structure. The packaging structure of the micro-VCSEL chip comprises a bearing substrate, the micro-VCSEL chip, an isolation insulating layer and a metal interconnection structure, a bearing substrate is selected from a Si composite substrate, an insulating composite substrate, a TGV substrate or an insulating transparent substrate, a micro-VCSEL chip is fixed on substrate bonding metal through mass transfer, and an isolation insulating layer window and a metal interconnection structure are utilized to realize transfer of an electrode from an epitaxial structure to a low-cost substrate; the method comprises the steps of epitaxial wafer preparation, chip miniaturization, mass transfer, insulating layer manufacturing, metal interconnection forming and the like, supports vertical / flip chips and P-side / N-side light emission, and is adaptive to multi-scene requirements. Waste of epitaxial materials is avoided, cost is remarkably reduced, meanwhile, electrical performance, optical performance and reliability of the device are guaranteed, and the application prospect is wide.

The application provides a laser chip with improved reliability and a preparation process thereof, and aims to solve the technical problem that an edge-emitting laser is prone to end face failure.The laser chip comprises a substrate, the back surface of the substrate is provided with an N electrode, the front surface of the substrate is provided with an epitaxial material, the top layer of the epitaxial material is an ohmic contact layer, the epitaxial material is provided with a waveguide, and the vicinity of the waveguide is a waveguide region; an insulating medium layer is arranged on the surface of the epitaxial material, the waveguide region and the insulating medium layer are provided with a P electrode, but the ohmic contact layer in the waveguide region is not provided with the insulating medium layer, and the P electrode is in contact with the ohmic contact layer; the end surface of the laser chip is provided with an electrode-free area, and the electrode-free area is not provided with the insulating medium layer and the P electrode above the electrode-free area.The application further comprises a preparation method of the laser chip.The electrode-free area is arranged on the end surface of the laser, and the electrode-free area can improve the COD threshold level and improve the reliability.

The invention discloses a method for composite etching of an electroplating gold plating layer, which comprises the following steps of: manufacturing a photoetching pattern on the front surface of gallium arsenide epitaxy, then evaporating a metal contact layer, depositing a SiNx protective mask layer, performing Mesa mesa etching on the gallium arsenide epitaxy, exposing a high-aluminum layer on the side surface of an epitaxial material, and forming an aluminum oxide limiting layer by adopting a wet oxidation process; a second SiNx protective mask layer continues to be deposited, and the metal contact layer is exposed through dry etching; forming a seed gold layer by adopting magnetron sputtering TiW / Au metal, and forming a photoresist mask with a target electrode pattern on the seed gold layer; electroplating thick gold on the photoresist mask pattern; the photoresist mask layer is removed after completion; the method of combining dry etching and wet etching is adopted to remove the gold plating layer in the non-electroplating area, so that the lateral corrosion of the metal layer is obviously reduced, the high-precision and high-fidelity electrode pattern transfer is realized, the lateral corrosion of the metal layer is reduced, and the passivation protection effect of the device is improved.

The invention discloses a high-linearity AlGaN / GaN device based on a ferroelectric medium, a conductor layer and an AlGaN layer are arranged on a GaN layer, a barrier layer is formed, a ferroelectric film is arranged between a grid electrode and the barrier layer, and the high-linearity AlGaN / GaN device based on the ferroelectric medium is obtained. In the prior art, the linearity of a device is improved to a certain extent, but the complexity of the device is increased due to higher design requirements on a process and an epitaxial material. According to the invention, a layer of ferroelectric medium is introduced under the gate, and polarization regulation and control of the AlGaN / GaN HEMT are realized by utilizing the characteristic that the polarization intensity of the ferroelectric medium can be modulated by an external electric field and an extremely high dielectric constant, so that relatively flat transconductance is obtained. According to the high-linearity AlGaN / GaN HEMT device, the ferroelectric material is introduced and the parameters of the ferroelectric material are optimized, so that the electrical characteristics of the AlGaN / GaN HEMT device are successfully regulated and controlled, the peak transconductance is broadened, and the high-linearity AlGaN / GaN HEMT device based on the ferroelectric gate medium is realized. Therefore, an important theoretical and experimental basis is provided for further improving the performance of the device and expanding the application field.

The invention discloses a vacuum packaging method of an MEMS device and the MEMS device, relates to the field of semiconductor packaging, and aims to solve the problem that the vacuum degree is low when the device is packaged in a wafer cap through a bonding material. The packaging method comprises the following steps: providing a substrate, an MEMS structure and a silicon cap, wherein the silicon cap is provided with a first surface and a second surface which are opposite to each other; a groove is machined in the second face, close to the substrate, of the silicon cap, a plurality of through holes penetrating through the first face and the second face are formed in the silicon cap, and the through holes are communicated with the groove; connecting the MEMS structure to the substrate through the first bonding layer; connecting the second surface of the silicon cap to the substrate through a second bonding layer, so that an accommodating cavity for accommodating the MEMS structure is defined between the groove and the substrate; placing the substrate, the MEMS structure and the silicon cap in a vacuum environment suitable for a molecular beam epitaxy process; and carrying out a molecular beam epitaxy process in the through hole of the silicon cap, so that the epitaxial material epitaxially extends in the through hole along the direction from the first surface to the second surface and is continuously filled to block the through hole, thereby realizing high-vacuum packaging of the device.

This invention discloses a method and structure for fabricating a photonic integrated device. The method includes: dividing a substrate sequentially into a pre-modulator region, a post-modulator region, a pre-grating region, a gain region, and a post-grating region; growing a first active layer after fabricating a selected-area epitaxial mask pattern in the gain region; growing a second active layer in the pre-modulator region after mask etching; growing a third active layer in the grating region after mask etching; finally, fabricating the grating; and completing the fabrication of the cladding, electrical contact layer, inverted shallow ridge waveguide structure, electrical isolation trench, and electrodes. This method achieves the integration of multiple materials through a single selected-area epitaxial growth and a single docking growth, saving material growth steps and reducing manufacturing costs. The gain region and post-modulator region achieve bandgap shift through selected-area epitaxial material growth, and the design of photofluorescence wavelength differences in each region enables multi-wavelength tuning and efficient modulation, providing a solution for the integration of wide-wavelength tunable lasers and dual-electric absorption modulators.

Methods and devices that include forming a first epitaxial region and a second epitaxial region above the first epitaxial region. An opening may be formed extending from the first region to the second region. And a liner layer is deposited on a sidewall and a bottom of the opening. A plasma treatment is performed on the liner layer, which can form a conditioned or passivated region of the first epitaxial region that may be maintained during the growth of additional epitaxial material on the second epitaxial region.

The preparation method of the semiconductor structure comprises the following steps: firstly, providing a silicon substrate; and then a patterned mask layer is formed on the silicon substrate, the patterned mask layer comprises a first pattern located in the middle area of the silicon substrate and a second pattern located in the annular area on the edge of the silicon substrate, and the width of the annular area covered by the second pattern is larger than 5 mm. And etching the silicon substrate by taking the patterned mask layer as a mask to form a deep trench. The patterned mask layer is then removed. And then filling epitaxial material in the deep trench. And finally, carrying out surface planarization treatment on the silicon substrate to remove the excessive epitaxial material on the surface of the silicon substrate. According to the preparation method of the semiconductor structure, the patterned mask layer is formed in the annular area, with the width larger than 5 mm, of the edge of the silicon substrate, and damage to the edge area in the etching and epitaxial filling process is avoided. Therefore, the stress resistance of the edge of the silicon substrate is remarkably enhanced, and wafer cracking or dark damage in the subsequent chemical mechanical polishing process is prevented, so that the overall integrity and reliability of the silicon substrate are improved.

The invention relates to the technical field of integrated circuits, and discloses a double-sided heterogeneous communication integrated circuit and a preparation method thereof, and the circuit comprises a substrate which comprises a first surface and a second surface, and the first surface and the second surface are located at the two opposite sides of the substrate; a first epitaxial material layer arranged corresponding to the first surface, wherein the first epitaxial material layer is used for manufacturing an electronic integrated circuit; a second epitaxial material layer arranged corresponding to the second surface, wherein the second epitaxial material layer is used for manufacturing a photon integrated circuit; a channel is arranged in the substrate, and the electronic integrated circuit is connected with the photon integrated circuit through the channel. Different functional devices can be arranged on the same chip substrate, so that the device size of the communication integrated circuit is smaller, the thickness is thinner, and the integration level is higher.

A semiconductor structure having a high-temperature silicide contact for backside source / drain (S / D) contacts and method for making the same is disclosed. In an aspect, the semiconductor structure comprises a substrate; a source / drain (S / D) structure comprising a lower S / D portion disposed above the substrate and an upper S / D portion disposed above the lower S / D portion, the lower S / D portion comprising a high temperature silicide structure and an etch stop material structure surrounding at least a portion of the high temperature silicide structure, the upper S / D portion comprising an epitaxial (EPI) material in contact with the high temperature silicide structure; and a backside metal structure that extends through the substrate and is in contact with the high temperature silicide structure.

The present application relates to the technical field of liquid phase epitaxy growth of thin film materials, and particularly to a vertical liquid phase epitaxy graphite boat and a method for epitaxy using the same. The graphite boat comprises a sample holder, a stirring rod, a stirring base, and a crucible. The graphite boat can improve the uniformity of epitaxial materials, reduce surface defects, reduce the epitaxial composition and thickness difference caused by the inhomogeneity of the mother liquor, and avoid the melting of the surface layer of the substrate at high temperature in the mother liquor, which causes the change of the composition of the mother liquor. While ensuring the uniformity of the epitaxial thickness and composition, the epitaxial carbon contamination defects can be effectively reduced, and the batch yield can be effectively improved.

The present invention belongs to the field of infrared detector manufacturing technology and specifically provides a method for liquid phase epitaxy of HgCdTe material based on a patterned sapphire substrate. The method comprises: providing a sapphire substrate having a polished surface on one side and a nanoimprinted surface on the other, the nanoimprinted surface being imprinted with a regular hexagonal pyramid convex lattice structure; growing a CdZnTe transition layer on the surface of the regular hexagonal pyramid convex lattice structure using metal organic chemical vapor deposition (MOCVD); performing in-situ annealing after growth, and then placing the substrate in a liquid phase epitaxy system for liquid phase epitaxy of HgCdTe material on the CdZnTe transition layer. The sapphire substrate has high strength and will not crack during device fabrication or when subjected to high and low temperature shock during device operation. This method can reduce the defect density of the epitaxial material, improve material uniformity, and enable the production of large-area HgCdTe epitaxial materials, thereby meeting the requirements of third-generation infrared focal plane arrays for low-cost, large-area detectors.

The invention discloses a semi-insulating silicon carbide epitaxial wafer and a preparation method thereof, a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. At least one semi-insulating silicon carbide epitaxial layer located on one side of the substrate; and the first epitaxial layer is positioned on one side, far away from the substrate, of the at least one semi-insulating silicon carbide epitaxial layer. The semi-insulating silicon carbide epitaxial material can be effectively prepared, the quality of the first epitaxial layer is improved, the defects of the first epitaxial layer are reduced, and therefore the preparation requirements of different devices are met.

The invention provides an ultra-wide-band gain spectrum epitaxial material structure of a tunable laser and application of the ultra-wide-band gain spectrum epitaxial material structure. The epitaxial material structure comprises a substrate, a lower cladding, a waveguide layer, an upper limiting layer, an upper cladding and a contact layer which are sequentially arranged from bottom to top, the waveguide layer comprises an intrinsic waveguide layer and a bismuth compound quantum dot layer embedded in the intrinsic waveguide layer, and the gain bandwidth is widened through the energy band anti-cross effect instead of suppressing radiation recombination. The epitaxial material structure grows in a molecular beam epitaxy or metal organic vapor phase epitaxy mode, and the crystal quality is optimized in combination with a rapid thermal annealing process. By regulating and controlling the number of layers of the quantum dots and the bismuth component, the ultra-wideband gain spectrum coverage from near ultraviolet to near infrared bands is realized, the gain spectrum is wide, the gain peak value of the material is relatively high, and meanwhile, the material has a low linewidth enhancement factor and high temperature stability. The epitaxial material structure can be monolithically integrated in a DFB laser array and a semiconductor optical amplifier, and a core gain medium is provided for a high-performance tunable semiconductor laser.

The present invention relates to the field of LED technology, and more specifically, to a method for preparing an ITO-structured LED with a GaP surface treatment. The method comprises the following specific steps: growing LED epitaxial material; etching a SiO2 mask and GaP; surface treatment of the GaP window layer; deposition of an ITO thin film; preparation of a P electrode; preparation of an N electrode; and cutting to obtain the desired chip. The method utilizes argon plasma bombardment to treat the thinned GaP material surface, effectively reducing the P-type doping concentration of the thin surface layer. The surface layer is then etched into a rough interface, increasing contact resistance at that location, improving the lateral current expansion capability, and enhancing light extraction efficiency.

Methods for surface conditioning based on cyclic processing are disclosed. The method includes activating the surface, removing excess material from the surface, applying a low energy particle treatment to the surface, and repeating the above steps until the surface has a desired smoothness. The method can be applied to various surfaces, including semiconductor surfaces, metal surfaces, dielectric surfaces, and 2D material surfaces, as well as patterned and non-patterned surfaces. The low energy particle treatment may be etch or deposition, and the process may be combined with ion beam shaping techniques and angled particle beam etch to improve surface conditioning. Methods of making substrates and epitaxial material grown surfaces are also provided.

The invention discloses a growth method for an epitaxial structure of a group III nitride heterojunction material system. The method comprises the following steps: determining a material of an insertion layer according to an in-plane lattice constant of a template layer and an in-plane lattice constant of a target epitaxial layer; based on the determined material of the insertion layer, selecting a first preset temperature to grow on the upper surface of the template layer to obtain the insertion layer with a preset thickness; and based on the insertion layer with the preset thickness, annealing recrystallization treatment is firstly carried out at a second preset temperature within a first preset time range, and then growth of a target epitaxial layer is carried out. According to the invention, the stress state required by the epitaxial layer can be accurately and reasonably controlled through the appropriate growth temperature and growth thickness of the insertion layer, so that high-quality growth of the target epitaxial structure is realized. The growth method for the epitaxial structure of the III-group nitride heterojunction material system can be widely applied to the technical field of epitaxial growth of materials.

A memory device and a method of manufacturing the same are disclosed. The disclosed manufacturing method of the memory device may include the steps of: forming a structure, the structure includes an epitaxial material plug extending in a vertical direction on a substrate, an epitaxial channel material layer extending in a horizontal direction from a side surface of the epitaxial material plug, and a gate insulating material layer formed at least on a surface portion of the epitaxial channel material layer. The manufacturing method of the memory device can also comprise the following step of forming a filling insulating layer for filling the peripheral space of the epitaxial material plug and the epitaxial channel material layer on the gate insulating material layer. The manufacturing method of the memory device can also comprise the following steps of: forming a transistor comprising the epitaxial channel material layer; and forming a capacitor electrically connected to the transistor.

The invention discloses a material-level forward radiation-proof reinforced gallium oxide MOSFET and a preparation method thereof. The preparation method comprises the following steps: growing a gallium oxide buffer layer and a channel layer on an iron-doped gallium oxide semi-insulating substrate layer; performing ionizing radiation regulation and control on the beta-Ga2O3 epitaxial material to generate an optimized beta-Ga2O3 epitaxial material; preparing a source electrode and a drain electrode at two ends of the gallium oxide channel layer; a plurality of uniformly distributed [102] crystal orientation trapezoidal grooves are etched in the oblique fin gate region along the gate width direction; preparing passivation layers on the inner walls, close to the drain electrode and the source electrode, of the gallium oxide channel layer and the trapezoidal groove; preparing a first dielectric layer on the gallium oxide channel layer; preparing a second dielectric layer on the first dielectric layer; and preparing a gate electrode on the second dielectric layer of the inclined fin gate region and the part of the channel outside the inclined fin gate. According to the invention, the side wall depth of the oblique fin gate three-dimensional structure is increased, and the probability of material degradation caused by particle incidence into the MOS sensitive region is reduced; and [102] crystal orientation trapezoidal oblique fin gate design reduces the working temperature and peak electric field of the device, and alleviates the influence of radiation on the degradation of the device.

The invention discloses a germanium epitaxy method, which is characterized by comprising the following steps of S1, providing a substrate, and forming a groove structure in the substrate; s2, performing a germanium epitaxial process at a first target temperature, and forming a germanium epitaxial layer with a first thickness in the trench structure; s3, a germanium epitaxial process is carried out at a second target temperature, a germanium epitaxial layer with a second thickness is formed in the groove structure, and the second target temperature is higher than the first target temperature; s4, carrying out annealing treatment on the substrate; s5, performing a germanium epitaxial process at the second target temperature, and forming a germanium epitaxial layer with a third thickness in the groove structure; s6, carrying out annealing treatment on the substrate; and S7, repeating the steps S5 and S6 until the germanium epitaxial layer at least fills the groove structure. The method has the advantages that the epitaxial material is redistributed by adjusting the proportion of the low-temperature growth time to the high-temperature growth time and matching repeated annealing, meanwhile, the wall hanging phenomenon in the epitaxial process caused by a window with the high aspect ratio is avoided, and high-quality epitaxy of the germanium absorption layer is achieved.