119 results about "Epitaxial material" patented technology

The invention discloses a low-divergence-angle narrow-linewidth high-power semiconductor laser. Relates to the technical field of semiconductor lasers, in particular to a low-divergence-angle narrow-linewidth high-power semiconductor laser. According to the invention, the parabolic waveguide structure is etched in the light field expansion area, and the metal reflector is introduced to realize a novel light field expansion and metal reflector integrated structure, and the transverse divergence angle of a laser mode is reduced through the expansion structure at the tail end of the waveguide. The laser comprises a laser gain area, a light field expansion area and a spectrum purification area at the tail of the light field expansion area. The laser gain region, the light field expansion region and the spectrum purification region at the tail part of the light field expansion region are made of the same laser epitaxial material in the longitudinal direction, the laser gain region is adjacent to the light field expansion region along the horizontal light emitting direction, and the light field expansion region is adjacent to the spectrum purification region at the tail part of the light field expansion region along the horizontal light emitting direction; the longitudinal direction is the direction from the substrate to the contact layer.

The invention relates to the technical field of semiconductor equipment, and provides vertical epitaxy equipment and an epitaxy method. The apparatus comprises: a vertical reaction chamber; the wafer boat is used for vertically loading a plurality of wafers at intervals; the driving device is used for driving the boat to enter / exit the vertical reaction cavity; the material supply assembly comprises a process supply pipeline and a switching unit; the process material source comprises a cleaning material source for removing an oxide layer on the surface of the wafer and an epitaxial material source for executing an epitaxial process; the process monitoring device is used for monitoring process end points of the cleaning process and the epitaxial process; and the control device is in communication connection with the switching unit and the process monitoring device, and controls the switching unit to switch the supply of the material source according to the monitoring result of the process monitoring device. According to the vertical epitaxial equipment, the epitaxial process can be continuously executed without transferring the wafers after the oxide removal process of the plurality of wafers is executed in situ in the equipment, so that the output rate and the yield of the equipment are improved, the cost is reduced, and the fragment and pollution risks are reduced.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure which comprises a substrate, and a graphene composite nano layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer are sequentially stacked on the substrate. The graphene composite nano layer comprises a modified graphene layer and a ZnO sub-layer which are stacked in sequence, the modified graphene layer is arranged on the substrate, and the ZnO sub-layer is arranged on the modified graphene layer; the modified graphene layer is subjected to nitrogen plasma treatment, and the thickness of the modified graphene layer is 10-100 nm; and the thickness of the ZnO sub layer is 20 nm to 200 nm. According to the invention, lattice mismatch dislocation, residual stress and thermal mismatch of the epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, the probability of radiation recombination of the heterogeneous epitaxial material is improved, and the requirement of heterogeneous epitaxy is relaxed at the same time.

The invention discloses a packaging structure of a micro-VCSEL chip and a manufacturing method of the packaging structure. The packaging structure of the micro-VCSEL chip comprises a bearing substrate, the micro-VCSEL chip, an isolation insulating layer and a metal interconnection structure, a bearing substrate is selected from a Si composite substrate, an insulating composite substrate, a TGV substrate or an insulating transparent substrate, a micro-VCSEL chip is fixed on substrate bonding metal through mass transfer, and an isolation insulating layer window and a metal interconnection structure are utilized to realize transfer of an electrode from an epitaxial structure to a low-cost substrate; the method comprises the steps of epitaxial wafer preparation, chip miniaturization, mass transfer, insulating layer manufacturing, metal interconnection forming and the like, supports vertical / flip chips and P-side / N-side light emission, and is adaptive to multi-scene requirements. Waste of epitaxial materials is avoided, cost is remarkably reduced, meanwhile, electrical performance, optical performance and reliability of the device are guaranteed, and the application prospect is wide.

The application provides a laser chip with improved reliability and a preparation process thereof, and aims to solve the technical problem that an edge-emitting laser is prone to end face failure.The laser chip comprises a substrate, the back surface of the substrate is provided with an N electrode, the front surface of the substrate is provided with an epitaxial material, the top layer of the epitaxial material is an ohmic contact layer, the epitaxial material is provided with a waveguide, and the vicinity of the waveguide is a waveguide region; an insulating medium layer is arranged on the surface of the epitaxial material, the waveguide region and the insulating medium layer are provided with a P electrode, but the ohmic contact layer in the waveguide region is not provided with the insulating medium layer, and the P electrode is in contact with the ohmic contact layer; the end surface of the laser chip is provided with an electrode-free area, and the electrode-free area is not provided with the insulating medium layer and the P electrode above the electrode-free area.The application further comprises a preparation method of the laser chip.The electrode-free area is arranged on the end surface of the laser, and the electrode-free area can improve the COD threshold level and improve the reliability.

The invention discloses a method for composite etching of an electroplating gold plating layer, which comprises the following steps of: manufacturing a photoetching pattern on the front surface of gallium arsenide epitaxy, then evaporating a metal contact layer, depositing a SiNx protective mask layer, performing Mesa mesa etching on the gallium arsenide epitaxy, exposing a high-aluminum layer on the side surface of an epitaxial material, and forming an aluminum oxide limiting layer by adopting a wet oxidation process; a second SiNx protective mask layer continues to be deposited, and the metal contact layer is exposed through dry etching; forming a seed gold layer by adopting magnetron sputtering TiW / Au metal, and forming a photoresist mask with a target electrode pattern on the seed gold layer; electroplating thick gold on the photoresist mask pattern; the photoresist mask layer is removed after completion; the method of combining dry etching and wet etching is adopted to remove the gold plating layer in the non-electroplating area, so that the lateral corrosion of the metal layer is obviously reduced, the high-precision and high-fidelity electrode pattern transfer is realized, the lateral corrosion of the metal layer is reduced, and the passivation protection effect of the device is improved.

The invention discloses a high-linearity AlGaN / GaN device based on a ferroelectric medium, a conductor layer and an AlGaN layer are arranged on a GaN layer, a barrier layer is formed, a ferroelectric film is arranged between a grid electrode and the barrier layer, and the high-linearity AlGaN / GaN device based on the ferroelectric medium is obtained. In the prior art, the linearity of a device is improved to a certain extent, but the complexity of the device is increased due to higher design requirements on a process and an epitaxial material. According to the invention, a layer of ferroelectric medium is introduced under the gate, and polarization regulation and control of the AlGaN / GaN HEMT are realized by utilizing the characteristic that the polarization intensity of the ferroelectric medium can be modulated by an external electric field and an extremely high dielectric constant, so that relatively flat transconductance is obtained. According to the high-linearity AlGaN / GaN HEMT device, the ferroelectric material is introduced and the parameters of the ferroelectric material are optimized, so that the electrical characteristics of the AlGaN / GaN HEMT device are successfully regulated and controlled, the peak transconductance is broadened, and the high-linearity AlGaN / GaN HEMT device based on the ferroelectric gate medium is realized. Therefore, an important theoretical and experimental basis is provided for further improving the performance of the device and expanding the application field.

This invention discloses a method and structure for fabricating a photonic integrated device. The method includes: dividing a substrate sequentially into a pre-modulator region, a post-modulator region, a pre-grating region, a gain region, and a post-grating region; growing a first active layer after fabricating a selected-area epitaxial mask pattern in the gain region; growing a second active layer in the pre-modulator region after mask etching; growing a third active layer in the grating region after mask etching; finally, fabricating the grating; and completing the fabrication of the cladding, electrical contact layer, inverted shallow ridge waveguide structure, electrical isolation trench, and electrodes. This method achieves the integration of multiple materials through a single selected-area epitaxial growth and a single docking growth, saving material growth steps and reducing manufacturing costs. The gain region and post-modulator region achieve bandgap shift through selected-area epitaxial material growth, and the design of photofluorescence wavelength differences in each region enables multi-wavelength tuning and efficient modulation, providing a solution for the integration of wide-wavelength tunable lasers and dual-electric absorption modulators.

Methods and devices that include forming a first epitaxial region and a second epitaxial region above the first epitaxial region. An opening may be formed extending from the first region to the second region. And a liner layer is deposited on a sidewall and a bottom of the opening. A plasma treatment is performed on the liner layer, which can form a conditioned or passivated region of the first epitaxial region that may be maintained during the growth of additional epitaxial material on the second epitaxial region.

The preparation method of the semiconductor structure comprises the following steps: firstly, providing a silicon substrate; and then a patterned mask layer is formed on the silicon substrate, the patterned mask layer comprises a first pattern located in the middle area of the silicon substrate and a second pattern located in the annular area on the edge of the silicon substrate, and the width of the annular area covered by the second pattern is larger than 5 mm. And etching the silicon substrate by taking the patterned mask layer as a mask to form a deep trench. The patterned mask layer is then removed. And then filling epitaxial material in the deep trench. And finally, carrying out surface planarization treatment on the silicon substrate to remove the excessive epitaxial material on the surface of the silicon substrate. According to the preparation method of the semiconductor structure, the patterned mask layer is formed in the annular area, with the width larger than 5 mm, of the edge of the silicon substrate, and damage to the edge area in the etching and epitaxial filling process is avoided. Therefore, the stress resistance of the edge of the silicon substrate is remarkably enhanced, and wafer cracking or dark damage in the subsequent chemical mechanical polishing process is prevented, so that the overall integrity and reliability of the silicon substrate are improved.

The invention relates to the technical field of integrated circuits, and discloses a double-sided heterogeneous communication integrated circuit and a preparation method thereof, and the circuit comprises a substrate which comprises a first surface and a second surface, and the first surface and the second surface are located at the two opposite sides of the substrate; a first epitaxial material layer arranged corresponding to the first surface, wherein the first epitaxial material layer is used for manufacturing an electronic integrated circuit; a second epitaxial material layer arranged corresponding to the second surface, wherein the second epitaxial material layer is used for manufacturing a photon integrated circuit; a channel is arranged in the substrate, and the electronic integrated circuit is connected with the photon integrated circuit through the channel. Different functional devices can be arranged on the same chip substrate, so that the device size of the communication integrated circuit is smaller, the thickness is thinner, and the integration level is higher.

A semiconductor structure having a high-temperature silicide contact for backside source / drain (S / D) contacts and method for making the same is disclosed. In an aspect, the semiconductor structure comprises a substrate; a source / drain (S / D) structure comprising a lower S / D portion disposed above the substrate and an upper S / D portion disposed above the lower S / D portion, the lower S / D portion comprising a high temperature silicide structure and an etch stop material structure surrounding at least a portion of the high temperature silicide structure, the upper S / D portion comprising an epitaxial (EPI) material in contact with the high temperature silicide structure; and a backside metal structure that extends through the substrate and is in contact with the high temperature silicide structure.

The present application relates to the technical field of liquid phase epitaxy growth of thin film materials, and particularly to a vertical liquid phase epitaxy graphite boat and a method for epitaxy using the same. The graphite boat comprises a sample holder, a stirring rod, a stirring base, and a crucible. The graphite boat can improve the uniformity of epitaxial materials, reduce surface defects, reduce the epitaxial composition and thickness difference caused by the inhomogeneity of the mother liquor, and avoid the melting of the surface layer of the substrate at high temperature in the mother liquor, which causes the change of the composition of the mother liquor. While ensuring the uniformity of the epitaxial thickness and composition, the epitaxial carbon contamination defects can be effectively reduced, and the batch yield can be effectively improved.

The invention provides an ultra-wide-band gain spectrum epitaxial material structure of a tunable laser and application of the ultra-wide-band gain spectrum epitaxial material structure. The epitaxial material structure comprises a substrate, a lower cladding, a waveguide layer, an upper limiting layer, an upper cladding and a contact layer which are sequentially arranged from bottom to top, the waveguide layer comprises an intrinsic waveguide layer and a bismuth compound quantum dot layer embedded in the intrinsic waveguide layer, and the gain bandwidth is widened through the energy band anti-cross effect instead of suppressing radiation recombination. The epitaxial material structure grows in a molecular beam epitaxy or metal organic vapor phase epitaxy mode, and the crystal quality is optimized in combination with a rapid thermal annealing process. By regulating and controlling the number of layers of the quantum dots and the bismuth component, the ultra-wideband gain spectrum coverage from near ultraviolet to near infrared bands is realized, the gain spectrum is wide, the gain peak value of the material is relatively high, and meanwhile, the material has a low linewidth enhancement factor and high temperature stability. The epitaxial material structure can be monolithically integrated in a DFB laser array and a semiconductor optical amplifier, and a core gain medium is provided for a high-performance tunable semiconductor laser.

Methods for surface conditioning based on cyclic processing are disclosed. The method includes activating the surface, removing excess material from the surface, applying a low energy particle treatment to the surface, and repeating the above steps until the surface has a desired smoothness. The method can be applied to various surfaces, including semiconductor surfaces, metal surfaces, dielectric surfaces, and 2D material surfaces, as well as patterned and non-patterned surfaces. The low energy particle treatment may be etch or deposition, and the process may be combined with ion beam shaping techniques and angled particle beam etch to improve surface conditioning. Methods of making substrates and epitaxial material grown surfaces are also provided.

A memory device and a method of manufacturing the same are disclosed. The disclosed manufacturing method of the memory device may include the steps of: forming a structure, the structure includes an epitaxial material plug extending in a vertical direction on a substrate, an epitaxial channel material layer extending in a horizontal direction from a side surface of the epitaxial material plug, and a gate insulating material layer formed at least on a surface portion of the epitaxial channel material layer. The manufacturing method of the memory device can also comprise the following step of forming a filling insulating layer for filling the peripheral space of the epitaxial material plug and the epitaxial channel material layer on the gate insulating material layer. The manufacturing method of the memory device can also comprise the following steps of: forming a transistor comprising the epitaxial channel material layer; and forming a capacitor electrically connected to the transistor.

The invention discloses a material-level forward radiation-proof reinforced gallium oxide MOSFET and a preparation method thereof. The preparation method comprises the following steps: growing a gallium oxide buffer layer and a channel layer on an iron-doped gallium oxide semi-insulating substrate layer; performing ionizing radiation regulation and control on the beta-Ga2O3 epitaxial material to generate an optimized beta-Ga2O3 epitaxial material; preparing a source electrode and a drain electrode at two ends of the gallium oxide channel layer; a plurality of uniformly distributed [102] crystal orientation trapezoidal grooves are etched in the oblique fin gate region along the gate width direction; preparing passivation layers on the inner walls, close to the drain electrode and the source electrode, of the gallium oxide channel layer and the trapezoidal groove; preparing a first dielectric layer on the gallium oxide channel layer; preparing a second dielectric layer on the first dielectric layer; and preparing a gate electrode on the second dielectric layer of the inclined fin gate region and the part of the channel outside the inclined fin gate. According to the invention, the side wall depth of the oblique fin gate three-dimensional structure is increased, and the probability of material degradation caused by particle incidence into the MOS sensitive region is reduced; and [102] crystal orientation trapezoidal oblique fin gate design reduces the working temperature and peak electric field of the device, and alleviates the influence of radiation on the degradation of the device.

The invention discloses a germanium epitaxy method, which is characterized by comprising the following steps of S1, providing a substrate, and forming a groove structure in the substrate; s2, performing a germanium epitaxial process at a first target temperature, and forming a germanium epitaxial layer with a first thickness in the trench structure; s3, a germanium epitaxial process is carried out at a second target temperature, a germanium epitaxial layer with a second thickness is formed in the groove structure, and the second target temperature is higher than the first target temperature; s4, carrying out annealing treatment on the substrate; s5, performing a germanium epitaxial process at the second target temperature, and forming a germanium epitaxial layer with a third thickness in the groove structure; s6, carrying out annealing treatment on the substrate; and S7, repeating the steps S5 and S6 until the germanium epitaxial layer at least fills the groove structure. The method has the advantages that the epitaxial material is redistributed by adjusting the proportion of the low-temperature growth time to the high-temperature growth time and matching repeated annealing, meanwhile, the wall hanging phenomenon in the epitaxial process caused by a window with the high aspect ratio is avoided, and high-quality epitaxy of the germanium absorption layer is achieved.

The invention discloses a high-efficiency reverse mismatched two-junction GaInP / GaInAs battery, the outer edge structure of the reverse mismatched two-junction GaInP / GaInAs battery comprises a gallium arsenide substrate, and a GaAs buffer layer, a GaInP barrier layer, a GaAs cap layer, an AlGaInP top battery, a first tunneling junction, a GaInAs bottom battery and an AlGaInAs cap layer which are arranged on the gallium arsenide substrate in sequence, and the AlGaInP top battery comprises multiple layers of MQW-MM quantum well gradient layers. According to the epitaxial material growth, the absorption spectrum range of the AlGaInP top cell material is expanded through the quantum well gradient layer (MQW-MM), and the short-circuit current density of the top cell is improved, so that the AlGaInP top cell is better matched with a GaInAs bottom cell with excessive current. The MQW-MM quantum well gradient layer serves as a bottom cell lattice constant gradient layer to achieve growth of a target lattice material, red shift is conducted on the absorption cut-off wavelength of a GaAs bottom cell material matched with a top cell GaInP lattice, the overall spectral absorption range is widened, and the GaInAs bottom cell material high in quality and low in defect grows.

A dielectric layer is formed at the bottom of a source / drain opening for a p-type source / drain region of a nanostructured field-effect transistor (NSFET) device. Next, a source / drain region having a multilayer structure is formed within the source / drain opening on the dielectric layer. In some examples, forming the source / drain region includes forming a first epitaxial material within the source / drain opening, wherein the first epitaxial material comprises individual portions disposed along the sidewalls of the channel material of the NSFET device exposed to the source / drain opening. Subsequently, a second epitaxial material is formed on the first epitaxial material and partially fills the source / drain opening. The second epitaxial material may extend continuously from a first individual portion of the first epitaxial material to a second individual portion of the first epitaxial material. Subsequently, a third epitaxial material is formed on the second epitaxial material to fill the source / drain opening.

The present invention belongs to the technical field of substrate processing. Disclosed is a substrate processing method for improving the imaging quality of an infrared focal plane hybrid integrated chip. The infrared focal plane hybrid integrated chip is fabricated from an array die and a silicon readout integrated circuit by means of flip-chip bonding using indium bumps; and an epitaxial layer, a substrate / epitaxial layer interface and a substrate are sequentially arranged above the indium bumps along a first direction. The method comprises the following steps: step S1, thinning a substrate, and performing an adhesive and wax removal treatment; step S2, forming a protective layer on an electrode of a silicon readout integrated circuit; step S3, adhering a treated die and a dummy wafer to a glass substrate, and removing the thinned substrate by means of a chemico-mechanical polishing treatment; and step S4, removing, by means of a chemical polishing treatment, the portion of the epitaxial layer that is close to the substrate / epitaxial layer interface and has a set thickness, and performing cleaning. The technical solution has the following beneficial effects: a tellurium-zinc-cadmium substrate is removed by means of chemico-mechanical polishing, thereby reducing the loss rate and overcoming the problem of uneven corrosion; and an epitaxial material close to the substrate / epitaxial layer interface is removed by means of chemical polishing, thereby improving the imaging quality.

The invention discloses a composite barrier epitaxial material structure of an indium phosphide high-mobility transistor and a buried gate control method of the composite barrier epitaxial material structure. The device sequentially comprises a semi-insulating indium phosphide substrate, a buffer layer, a channel layer, an isolation layer, a doping layer, an inner barrier layer, a buried gate stop layer, a surface barrier layer, an InP corrosion self-stop layer and a cap layer from bottom to top. The buried gate control method comprises the following steps: firstly, preparing a 4-inch InP wafer, and simultaneously completing isolation and source-drain ohmic contact pre-process; an InP HEMT grid electrode is prepared; performing buried gate process heat treatment; other front and back processes are completed, and independent chips are formed through cutting-up. According to the invention, an InP-InAlAs-InGaP composite barrier structure is provided in an epitaxial structure, stable diffusion Schottky contact is formed by adopting a buried gate process, and an InGaP buried gate stop layer is added, so that the buried gate depth is controllable. The InP HEMT device has the characteristics of low noise, low power consumption, high breakdown voltage and the like, and can meet the use requirements of an InP HEMT low-noise amplifier in application scenes of quantum bit reading, radio astronomy, remote sensing imaging and the like.

The present disclosure is directed toward architectures that combine DWDM and CWDM concepts in a single PIC. Transmitter stages in accordance with the present disclosure include a plurality of multiwavelength lasers having regions of separately grown epitaxial material whose gain peaks are centered at different wavelengths. Each laser launches a wavelength comb comprising a plurality of wavelength signals into a PLC, where the wavelengths within each wavelength comb are separated by a wavelength spacing that is smaller than that between adjacent wavelength combs. In some embodiments, the PLC includes modulator banks for encoding data on the wavelength signals and combining them to produce a composite DWDM output signal. In some embodiments, a receiver stage is included for demultiplexing a composite DWDM input signal and detecting each wavelength channel within it. In some embodiments, the receiver stage employs polarization-diversity techniques to enable it to operate on unpolarized / randomly polarized input signals.

The present application relates to a kind of high-voltage Schottky diode with vertical AlGaN / GaN heterojunction and its preparation method, the preparation method includes the following steps: one, epitaxial material growth;Two, re-growth groove production and re-growth;Three, cathode production;Four, dielectric layer growth;Five, anode production.It utilizes the 2DEG (two-dimensional electron gas) in vertical direction formed by re-growth, can significantly improve the forward current of diode;While utilizing the PN junction formed by re-growth, can uniformly disperse peak electric field, improve electric field concentration effect, improve breakdown voltage, and, when reverse, PN junction can be more effectively reduced reverse leakage than Schottky junction.

The invention provides a manufacturing method of a zero-layer alignment mark suitable for a multi-material active region substrate. The method comprises the following steps: forming a first dielectric layer on a substrate with a zero-layer alignment mark region and a channel region; etching the zero layer alignment mark area, and forming a groove in the substrate; forming a second dielectric layer for blocking epitaxial growth on the inner surface of the groove and the channel region; chemical mechanical planarization is carried out on the second dielectric layer, so that the second dielectric layer is reserved in the groove to form a lining; and removing the first dielectric layer. According to the method, the dielectric layer lining is formed in the zero-layer alignment marked groove in advance, so that the epitaxial material in the subsequent multi-material active region process is effectively prevented from filling the groove, and the marked step morphology is ensured to be kept after being subjected to chemical mechanical planarization. According to the method, the problem that in the prior art, the zero-layer alignment mark is rubbed down, so that the alignment signal disappears is solved, and stable and clear alignment signals can be provided for the subsequent photoetching step.

The application discloses a manufacturing method of a diode and the diode manufactured by the method, wherein the method comprises the following steps: S1, setting a substrate layer and an epitaxial material parameter of a diode model, and establishing a diode physical model; S2, changing a concentration gradient factor of acceptor ions of an active region of the diode physical model, simulating a reverse breakdown voltage under different concentration gradient factors, and obtaining a relationship curve graph of the concentration gradient factor and the reverse breakdown voltage; S3, obtaining a concentration gradient factor range corresponding to a maximum reverse breakdown voltage from the relationship curve graph of the concentration gradient factor and the reverse breakdown voltage; S4, formulating and simulating a manufacturing process of the diode, and obtaining a process parameter for enabling the concentration gradient factor of the acceptor ions of the active region of the diode to fall within the concentration gradient factor range; and S5, manufacturing the diode according to the manufacturing process of the diode and the obtained process parameter. The diode manufactured by the method has an optimal reverse breakdown voltage and an optimal anti-avalanche capability under the same thickness of the epitaxial layer.

This invention provides a HEMT device and its fabrication method. The HEMT device includes: a partially removed substrate layer; an epitaxial layer located on the substrate layer, the epitaxial layer including a nucleation layer in contact with the substrate layer; a source electrode region and a drain electrode region located on opposite sides above the epitaxial layer; and a patterned blank region provided in the drain electrode region, the blank region penetrating the epitaxial layer and extending to the portion of the substrate layer that has been removed. By partially removing the substrate layer, this invention avoids the formation of a conductive layer between the removed portion of the substrate layer and the nucleation layer, reducing parasitic resistance introduced by the substrate layer and decreasing radio frequency losses. Simultaneously, the blank region penetrating the source and drain electrode regions and the epitaxial layer improves the device's heat dissipation capability and controls thermal effects. Furthermore, by using a low-resistivity silicon substrate, the bending problem of high-resistivity silicon-based GaN epitaxial materials is avoided, thereby expanding the wafer size.

The application relates to a GaN-based diode designed by body heat dissipation and a preparation method thereof. ‑ The equivalent resistance of the GaN transmission layer is reduced, so that the forward current of the diode is improved; meanwhile, the heat-conducting material is filled between each conductive unit, so that the heat dissipation capacity of the diode is improved.

This invention proposes a superluminescent light-emitting diode (SLD), belonging to the technical field of light-emitting diodes, to solve the technical problem of SLDs being sensitive to cavity surface reflection and prone to spectral ripple. The SLD of this invention includes a substrate, on the front side of which an epitaxial material is grown. A waveguide structure is formed on the upper surface of the epitaxial material. The waveguide structure includes a short curved waveguide absorption region, a straight waveguide emitting region, and a long curved waveguide absorption region connected end-to-end. The length of the long curved waveguide absorption region is greater than the length of the short curved waveguide absorption region. The long curved waveguide absorption region is located at one end of the front cavity surface, and the short curved waveguide absorption region is located at one end of the rear cavity surface. The front face of the long curved waveguide absorption region is the light-emitting surface. Electrodes are provided on the straight waveguide emitting region to form a beam-emitting region. The SLD prepared by this invention exhibits high power, wide spectrum, and low spectral ripple output performance.