352results about How to "Reduce dislocation" patented technology

Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm⁻² or less and high-quality AlN substrates having surfaces of any desired crystallographic orientation fabricated from these bulk crystals.

Methods, and structures formed thereby, are disclosed for forming laterally grown structures with nanoscale dimensions from nanoscale arrays which can be patterned from nanoscale lithography. The structures and methods disclosed herein have applications with electronic, photonic, molecular electronic, spintronic, microfluidic or nano-mechanical (NEMS) technologies. The spacing between laterally grown structures can be a nanoscale measurement, for example with a spacing distance which can be approximately 1-50 nm, and more particularly can be from approximately 3-5 nm. This spacing is appropriate for integration of molecular electronic devices. The pitch between posts can be less than the average distance characteristic between dislocation defects for example in GaN (ρ=10¹⁰/cm²→d=0.1 μm) resulting an overall reduction in defect density. Large-scale integration of nanoscale devices can be achieved using lithographic equipment that is orders of magnitude less expensive that that used for advanced lithographic techniques, such as electron beam lithography.

Semiconductor structures and devices based thereon include an aluminum nitride single-crystal substrate and at least one layer epitaxially grown thereover. The epitaxial layer may comprise at least one of AlN, GaN, InN, or any binary or tertiary alloy combination thereof, and have an average dislocation density within the semiconductor heterostructure is less than about 10⁶ cm⁻².

The invention relates to a silver alloy wire and a preparation method thereof. The silver alloy wire is prepared from the following components of 0.5-10 percent of Au, 0-1 percent of Pt, 1-6 percent of Pd, 0-1 percent of Rh, 0-1 percent of Cu, 0-500ppm of Ln, 0-200ppm of Ce, 0-0.5 percent of Al, 0.7-3 percent of Ti, 0-0.2 percent of Si, 0-0.3 percent of Zn, 0-1 percent of Sn, 0-10 percent of Be and the balance of Ag. A directional continuous casting process is adopted. The prepared silver alloy wire overcomes the problem that the bonded silver wire is easily subjected to sulfur corrosion in the prior art, and has a series of other excellent characteristics.

The invention discloses an LED (light emitting diode) epitaxy structure and a preparation method thereof. The LED epitaxy structure successively comprises a substrate, a GaN nucleating layer, multiple pairs of superlattice buffer layers, an n-GaN layer, an MQW luminescent layer, a p-GaN layer and a p-type contact layer from bottom to top, wherein each superlattice buffer layer is formed by an AlGaN/n-GaN alternately stacked structure. The LED epitaxy structure is characterized in that Al(n) is defined to represent an Al component value in the nth pair of AlGaN/n-GaN superlattice buffer layer; N(n) represents the n-type impurity concentration value in the nth pair of AlGaN/n-GaN superlattice buffer layer; the variation trend of Al(n) is gradually lowered after being gradually raised; and the variation trend of N(n) is gradually lowered after being gradually raised. According to the LED epitaxy structure provided by the invention, lattice stress caused by lattice mismatch due to that a sapphire substrate and the GaN lattice are not matched can be effectively and fully released on a bottom layer growth section so as to greatly lower the warping of an epitaxial wafer in the whole high-temperature growth process and improve the wavelength concentricity and yield of the epitaxial wafer. Meanwhile, the GaN lattice quality is effectively improved, the lattice dislocation density is reduced, and the optical-electrical characteristic of the device is more stable.

The invention relates to a structure using graphite alkene as buffer layer epitaxy GaN (gallium nitride) and a preparation method of the structure. The method comprises the following steps of: adopting a graphite alkene layer as a buffer layer between the substrate and a gallium nitride epitaxy layer; and inserting a nitride thin layer between the graphite alkene layer and a GaN layer so as to obtain a gallium nitride epitaxy layer with low stress and high quality. The defective rate of LED (light emitting diode) devices is reduced, the quality of the LED devices is increased, and the life cycle is prolonged. The problem of lattice mismatch and thermal expansion coefficient mismatch between the substrate and the gallium nitride are solved effectively.

The present invention discloses the large area high quality quasi group III-nitride substrates comprising two categories: electrically conductive and isolating. The methods manufacturing the same comprise the following process steps in the order presented: disposing a first intermediate layer on a large area silicon (Si) original growth substrate, disposing a group III-nitride epitaxial layer including a n- or p-type epitaxial layer, disposing a reflector/Ohmic layer, disposing a second intermediate layer, disposing a supporting plate, removing the silicon original growth substrate and the first intermediate layer, then the group III-nitride epitaxial layer exposed. Vertical and lateral GaN based LEDs growing on electrically conductive and isolating quasi group III-nitride substrates respectively are disclosed.

The present invention discloses a TiAlN/TiAlCN multilayer coating of substrate surface and preparing method thereof, wherein a transitional layer is between a substrate and a TiAlN/TiAlCN multilayer coating; the multilayer coating is formed by alternating periodic arrangement of TiAlN films and TiAlCN films; in a period, the thickness sum of the TiAlN films and the TiAlCN films is 1-20 nano; the percentage by weight of C atom in the TiAlCN films is 0.1-5%. The multilayer coating of the present invention has the advantages of high hardness, low internal stress and high tenacity; the cutting efficiency and corrosion resistance of the substrate can be improved, and the service life of the substrate can be prolonged. In the present invention, the multilayer coating is deposited by high power pulse magnetron sputtering technique; the problems that cathode arc ion plating and depositing speed is too fast to prepare a nano epitaxial film and that target poisoning is caused during the procedure for preparing films by DC magnetron sputtering are solved; the nano modulation period is controlled via adjusting the autorotation and revolution speeds of the substrate and adjusting the quantity of targets.

The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

The invention relates to a white light-emitting diode (LED) chip and a forming method thereof. The white LED chip comprises a silicon substrate, a first buffer layer, a first active layer, a first cap layer, a first groove and a second groove, wherein the first buffer layer, the first active layer and the first cap layer are positioned on the silicon substrate sequentially; the first groove passes through the first buffer layer and the first active layer respectively to extend to the first cap layer, and a second buffer layer, a second active layer and a second cap layer are arranged in the first groove; the second groove passes through the first buffer layer and the first active layer respectively to extend to the first cap layer, and a third buffer layer, a third active layer and a third cap layer are arranged in the second groove; and the first active layer, the second active layer and the third active layer are selected from one of a blue light active layer, a green light active layer and a red light active layer respectively and are the active layers with different colors. When used, the white LED chip can emit red light, green light and blue light simultaneously, and can emit white light after the light with three colors is mixed; and due to the adoption of the silicon substrate which deviates 1 to 9 degrees from a crystal plane (111) in the crystal orientation, dislocation between the buffer layers and the silicon substrate can be reduced.

The GaN facet growth method produces defect accumulating regions H on masks by forming a dotmask or a stripemask on an undersubstrate, growing GaN in a reaction furnace in vapor phase, inducing GaN crystals on exposed parts without covering the masks, inviting facets starting from verges of the masks and producing defect accumulating regions H on the mask. The defect accumulating regions H have four versions, that is, non (O), polycrystal (P), c-axis inclining single crystal (A) and orientation inversion (J). The best is the orientation inversion region (J). A sign of occurrence of the orientation inversion regions (J) is beaks of inversion orientation appearing on facets. GaN is grown on a masked undersubstrate by supplying a carbon material at a hydrocarbon partial pressure of 10 Pa to 5 kPa for 0.5 hour to 2 hour by an HVPE facet growth method without burying facets.

The invention provides a laying method of seed crystals and is used for the casting of quasi-monocrystalline silicon piece. The method comprises the steps of: seed crystals are laid on the crucible bottom, the seed crystals have a same growth surface crystal orientation of [001] or [001<->]; the seed crystals in close contact and fully cover the crucible bottom to form a seed crystal layer; the side crystal orientation of two adjacent contact the seed crystals belongs to the same crystal to the same crystal orientation family and constitute a coincidence position lattice type of grain boundary; when the side crystal orientation of the seed crystal is <110>, the crystal orientation of growth face of the adjacent seed crystals alternately splices front and back according to [001] [001<->], or one of the adjacent seed crystals rotates 90 DEG; when the side crystal orientation of the seed crystals is not <110> crystal orientation family, the crystal orientation of growth face of the adjacent seed crystals alternately splices front and back, or after the front and back alternate splicing, one of the adjacent seed crystals rotates 90 DEG. The laying of seed crystals reduces the occurrence of dislocation sources in the crystal introduction process. The invention also provides a preparation method of a quasi-monocrystalline silicon piece and the quasi-monocrystalline silicon piece.

The invention discloses a multilayer composite membrane passivation structure of a table top high-power semiconductor device. The multilayer composite membrane passivation structure comprises P-type boron junction areas and an N-type phosphorus junction area, the upper end and the lower end of the N-type phosphorus junction area are provided with the P-type phosphorus areas respectively, and an alpha-polycrystalline silicon layer, a semi-insulating polycrystalline silicon thin membrane, a low-temperature heat oxidation layer, a high-temperature Si3N4 thin membrane, a negative charge glass passivation layer and a low-temperature heat oxidation layer are sequentially arranged on the surface of a PN junction of a table top of the table top high-power semiconductor device from inside to outside. A manufacturing technology of the multilayer composite membrane passivation structure of the table top high-power semiconductor device includes the following steps: a, depositing the alpha-polycrystalline silicon, b, depositing semi-insulating polycrystalline silicon, c, depositing the low-temperature heat oxidation layer, d, depositing Si3N4, e, conducting passivation on glass, and f, depositing the low-temperature heat oxidation layer in the outmost layer. The multilayer composite membrane passivation structure and the manufacturing technology have the advantages that the alpha-polycrystalline silicon layer is deposited, so that crystal lattice adaptation can be achieved, damage to crystal lattices of a silicon wafer in a groove can be repaired, leaked currents in the surfaces of junctions are reduced, and the stability and the reliability of the device at the high temperature are improved.

An object of the present invention is to provide a Group III nitride semiconductor stacked structure with a low dislocation density obtained by stacking only a semiconductor layer on a flat substrate by the use of a normal epitaxial growth method without processing the substrate or a deposit layer on the substrate, wherein the dislocation density is 1×10⁷ cm⁻² or less. The inventive Group III nitride semiconductor stacked structure comprises a substrate having a surface roughness (Ra) of 1 nm or less and a Group III nitride semiconductor layer directly stacked on the substrate, wherein the Group III nitride semiconductor layer comprises a plurality of layers put into contact with each other, the plurality of layers comprise a high-concentration impurity atom layer and a low-concentration impurity atom layer, and the high-concentration impurity atom layer is present on the substrate side.

The invention relates to the field of processing of metal laminated plate belts, in particular to a method for rolling a magnesium-aluminum laminated plate by a drum-shaped corrugated roller. The method comprises the following steps of selecting a magnesium alloy plate with the same length and width as a clad plate and a pure aluminum or aluminum alloy plate as a base plate, cleaning the surface of the metal plate, buckling and assembling the ground surfaces of the base plate and the clad plate together, or buckling and stacking and assembling together. In the first pass, when the drum rolleris used for rolling the magnesium-aluminum laminated plate, a stress peak value can be formed on the lowest metal interface of the laminated plate, and the combination of the middle part of the laminated plate and the wave trough of the wave interface is promoted. In the second pass flattening process, a stress peak value is formed on the edge part of the laminated plate with poor bonding and themetal interface at the wave peak part during the first pass rolling of the plate, large plastic deformation is generated at the same time, and the bonding of the edge part of the laminated plate is promoted. According to the process, rolling is carried out twice in sequence, the bonding of the whole interface is promoted, and the bonding strength of the interface of the laminated plate is improved.

The invention relates to a gallium nitride (GaN) based personal identification number (PIN) detector based on an imaging sapphire substrate and a preparation method. The structure is that a thick cushion layer grows on the imaging sapphire substrate, the thick cushion layer comprises low temperature cushion layer growing, recrystallization, three-dimensional growing and two-dimensional growing, and a GaN film material with good quality is obtained. An n+ type GaN layer, an intrinsic GaN layer and a p type GaN layer sequentially grow. A p ohmic contact electrode is deposited on the surface of a p layer, a p type film layer and an intrinsic layer are etched to an n+ type film layer, the shape of an etching table face is round, square or hexagon, an n type ohmic contact electrode is deposited on an n+ type layer, and an n type electrode is annular or square. A passivation layer grows and holes are drilled, the p electrode and the n electrode are exposed out, and a thickening electrode grows on the p electrode and the n electrode respectively. Devices prepared by using the method are high in growth material quality, small in dislocation and defect density, small in dark current and stable in performance. The dark current under reversal biasing voltage almost has no change, and quantum efficiency is substantially improved.

The invention discloses a growing method for a light-emitting diode epitaxial wafer, and belongs to the technical field of semiconductors. The growing method comprises the following steps: growing a low-temperature buffer layer, a high-temperature buffer layer, an N-type GaN layer, an N-type inserting layer, an active layer, an electron barrier layer and a P-type GaN layer in sequence on a substrate, wherein the growth temperature of the N-type GaN layer is greater than that of the N-type inserting layer which is greater than that of the active layer; the N-type inserting layer comprises a first sublayer, a second sublayer and a third sublayer which are laminated in sequence; the first sublayer is a superlattice structure formed by alternately laminating two GaN layers in which the doping concentrations of the N-type doping agents are different, and the doping concentration of the N-type doping agent in the first sublayer is smaller than that of the N-type doping agent in the N-type GaN layer; the second sublayer is an AlGaN layer or a superlattice structure formed by alternately laminating at least three AlGaN layers and at least three GaN layers; and the third sublayer is an InGaN layer. The N-type inserting layer in the invention plays a buffer role, and is beneficial for the growth of the active layer.

The invention discloses a preparation method of crystalline silicon, which comprises the following steps: a mono-crystal silicon seed crystal is randomly paved in the center of the bottom of a crucible to form a seed crystal layer; a nucleation source is paved at the residual part of the bottom to form a nucleation source layer; a silicon material in a melting state is arranged on the seed crystal layer and the nucleation source layer to control the temperature of the bottom of the crucible so as to prevent the seed crystal layer and the nucleation source layer from being completely molten; and the temperature in the crucible is controlled to gradually increase to form temperature gradient in the direction vertical to the upward direction of the bottom of the crucible, so that the molten silicone material can form nuclear crystallization on the mono-crystal silicone seed crystal and the nucleation source and the crystalline silicon of which the center is mono-like and the periphery is high-effective polycrystal. The invention further discloses the crystalline silicon prepared by the preparation method for crystalline silicon. The preparation method for crystalline silicon reduces the consumption of the mono-crystal silicone seed crystal, saves the production cost, improves the quality of the silicon block in the area close to the side wall of the crucible; and monocrystal-like silicon and high-effective polycrystal silicone coexist in the prepared crystalline silicone, and the complementary advantages of the monocrystal-like silicone and the high-effective polycrystal silicone are realized.